Data Sheet

1. General description
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The
device features latch enable (LE) and output enable (OE
) inputs. When LE is HIGH, data
at the inputs enter the latches. In this condition the latches are transparent, a latch output
will change each time its corresponding D-input changes. When LE is LOW the latches
store the information that was present at the inputs a set-up time preceding the
HIGH-to-LOW transition of LE. A HIGH on OE
causes the outputs to assume a
high-impedance OFF-state. Operation of the OE
input does not affect the state of the
latches. Inputs include clamp diodes. This enables the use of current limiting resistors to
interface inputs to voltages in excess of V
CC
.
2. Features and benefits
 Input levels:
 For 74HC573: CMOS level
 For 74HCT573: TTL level
 Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
 Useful as input or output port for microprocessors and microcomputers
 3-state non-inverting outputs for bus-oriented applications
 Common 3-state output enable input
 Multiple package options
 Complies with JEDEC standard no. 7 A
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 Specified from 40 Cto+85C and from 40 Cto+125C
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Rev. 7 — 4 March 2016 Product data sheet