Data Sheet

Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 5 — 21 August 2017
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6.2 Pin description
Table 2. Pin description
Symbol Pin Description
PL 1 asynchronous parallel load input (active LOW)
CP 2 clock input (LOW-to-HIGH edge-triggered)
Q7 7 complementary output from the last stage
GND 8 ground (0 V)
Q7 9 serial output from the last stage
DS 10 serial data input
D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn)
CE 15 clock enable input (active LOW)
V
CC
16 positive supply voltage
7 Functional description
Table 3. Function table
[1]
Inputs Qn registers OutputsOperating modes
PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7
L X X X L L L to L L Hparallel load
L X X X H H H to H H L
H L ↑ l X L q0 to q5 q6 q6
H L ↑ h X H q0 to q5 q6 q6
H ↑ L l X L q0 to q5 q6 q6
serial shift
H ↑ L h X H q0 to q5 q6 q6
H H X X X q0 q1 to q6 q7 q7hold "do nothing"
H X H X X q0 q1 to q6 q7 q7
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
↑ = LOW-to-HIGH clock transition.