Data Sheet

Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 5 — 21 August 2017
13 / 22
t
h
t
su
t
su
t
h
t
W
V
M
V
M
GND
V
I
GND
V
I
DS input
t
su
V
M
mna990
GND
V
I
CP, CE input
CP, CE input
(1)
(1) CE may change only from HIGH-to-LOW while CP is LOW.
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Figure 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE)
inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable
input (CE)
mna991
Dn input
PL input
t
su
t
h
V
I
GND
V
I
GND
V
M
V
M
t
su
t
h
V
M
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Figure 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
Table 8. Measurement points
Input OutputType
V
I
V
M
V
M
74HC165 V
CC
0.5V
CC
0.5V
CC
74HCT165 3 V 1.3 V 1.3 V