Data Sheet

Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 5 — 21 August 2017
11 / 22
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
CP input; see Figure 7
V
CC
= 4.5 V 26 44 - 21 - 17 - MHz
f
max
maximum
frequency
V
CC
= 5.0 V; C
L
= 15 pF - 48 - - - - - MHz
C
PD
power
dissipation
capacitance
per package;
V
I
= GND to V
CC
- 1.5 V
[3]
- 35 - - - - - pF
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in μW).
P
D
= C
PD
× V
CC
2
× f
i
+ Σ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
Σ (C
L
× V
CC
2
× f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
11.1 Waveforms and test circuit
mna987
CP or CE input
Q7 or Q7 output
90 %
10 % 10 %
90 %
t
PHL
t
THL
t
TLH
t
PLH
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Figure 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the
maximum clock frequency and the output transition times