Data Sheet
Table Of Contents
- 1 Design guidelines
- 2 Ordering Information
- 3 Pinout and Terminal Descriptions
- 4 Packaging
- 5 Power control
- 6 Interfaces
- 7 Block diagram
- 8 Example schematics
- 9 802.11 Radio
- 10 Firmware
- 11 Host interfaces
- 12 Electrical characteristics
- 13 RF Characteristics
- 14 Physical dimensions
- 15 Layout guidelines
- 16 Soldering recommendations
- 17 Certifications
- 18 Qualified Antenna Types for WF121-E
Silicon Labs
Page 21 of 45
6.8 RF Debug Interface
Pad number Pad function Description
52 SPI_MISO RF Debug data out
53 SPI_CLK RF Debug clock
54 SPI_MOSI RF Debug data in
55 SPI_CS RF Debug chip select
Table 9: RF Debug SPI pads
Four pads are provided for the debug interface of the WiFi chipset in the module bottom. This is meant for RF
calibration and testing during module production and product certification measurements. These should in
most applications be left unconnected, but should be taken into account when doing the application board
layout. Avoid placing vias or signals without a solder mask under these pads. If separate radiated emission
compliance measurements need to made for the application, these should be connected to a header. More
information on the certification measurements can be obtained from support via http://www.silabs.com/
.
6.9 CPU Clock
Pad number Function Description
30 OSC1 External crystal input
31 OSC2 External crystal output
Table 10: Clock crystal pads
WF121 uses an internal 26 MHz crystal as the WiFi reference clock. The internal processor uses an
integrated 8 MHz RC oscillator and associated phase locked loop (PLL) to create its clock signals, but cannot
share the internal crystal-stabilized WiFi clock. The internal CPU uses a PLL to create an 80 MHz core clock.
To use the USB functionality or when using the UART with speeds above 115.2 kbps, an external crystal and
the associated capacitors must be connected to pads OSC1 and OSC2 to provide a sufficiently accurate
clock. Typically the load capacitors should be 22 to 33 pF. If an external crystal is not needed, these pads are
available for GPIO use.
For firmware versions lower than 1.3, the external crystal frequency must be 8 MHz, for version 1.3 and later,
the frequency should be a multiple of 4 MHz, with a maximum frequency of 24 MHz. The desired frequency
can be set in the hardware configuration file and programmed to the module with the firmware.
Due to the protected nature of the oscillator divider settings, the crystal frequency cannot be programmed
using the DFU interface. A PICkit3 or other PIC32 compatible programmer is required.
The WF121 with the default settings will detect the presence of an 8 MHz crystal and will use that, or if
missing, will automatically use the internal RC oscillator. If the crystal frequency is set to a different frequency
in the hardware configuration file, the autodetect will be disabled.
The Ethernet connection requires the external PHY to provide the 50 MHz RMII reference clock. A separate
external crystal is not required for the module CPU for Ethernet operation, the internal RC oscillator is
sufficient.