Data Sheet

Silicon Labs
Page 19 of 45
Other functions are present on the same pins; please refer to Table 2 for details.
6.5 Ethernet
Pad number Function Description
2 EMDC Management bus clock
3 ERXD1 Receive data 1
4 ERXD0 Receive data 0
5 ECRSDV Receive data valid
6 EREFCLK Reference clock
7 ERXERR Receive error
10 ETXEN Transmit enable
11 ETXD0 Transmit data 0
12 ETXD1 Transmit data 1
42 ETXERR Transmit error
47 EMDIO Management bus data
Table 6: Ethernet pads
An RMII interface to an external Ethernet PHY is available. The PHY should supply EREFCLK with a 50 MHz
RMII reference clock. Other functions are present on the same pads; please refer to Table 2 for details.
The current firmware contains support for using a Micrel PHY type KSZ8081RNA (the evaluation board
schematic shows the fully compatible but now obsolete KSZ8031RNL) to implement a 10/100Mbps Ethernet
connection and using it as an endpoint, allowing data to be streamed from and to the Wi-Fi interface or other
end points.
Ethernet MAC-to-MAC connection is also supported using an Ethernet switch chip.
Notices:
If MDIO is not required, place a 1-10 kohm pull-up resistor on the EMDIO line and don’t wire it to Ethernet
chip.
An RMII bus clock (50 MHz) must be fed to EREFCLK from an external clock source, Ethernet PHY or from
an Ethernet switch chip.