Customer Notification VR4133 TM 64-bit Microprocessor Operating Precautions µPD30133F3-266-GA3-A Document No.
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Table of Contents (A) Table of Operating Precautions ............................................................................................. 4 (B) Description of Operating Precautions................................................................................... 5 (C) Valid Specification................................................................................................................. 10 (D) Revision History .....................................................................
Operating Precautions for VR4133 TM (A) Table of Operating Precautions No. Outline µPD30133 1.3 1.4 P X Rev. Rank Note Simultaneous locking of cache lines with the same index Reception of non IEEE802.3 conformant packages 1.1 I,K 1.
Operating Precautions for VR4133 TM (B) Description of Operating Precautions No. 1 Simultaneous locking of cache lines with the same index (Specification change notice) Details Simultaneous locking of two cache lines with the same index (i.e. in both cache ways) is prohibited. No. 2 Reception of non IEEE802.3 conformant packages (Specification change notice) Details In case of the reception of a non-IEEE802.
Operating Precautions for VR4133 TM No. 5 Write access to external I/O area (Direction of usage) Details A write cycle to external I/O or Flash area after • a CPU read/write access to a BCU-managed registersNote • or a CPU I/O read after a bus hold • or a DMA I/O read after a bus hold • or a Flash memory read may drive the wrong write data.
Operating Precautions for VR4133 TM No.
Operating Precautions for VR4133 TM No. 9 Ethernet: excessive data transfer into memory (Direction of usage) Details If two or more packets are received continuously, excessive data may be written at the end of a packet. The length of excessive data depends on the value of the DRBS0/1 bits of register RCV_CFGR0/1 (0x0f00 1618 / 0x0f00 1918) and becomes up to [burst length -1].
Operating Precautions for VR4133 TM No. 11 Usage PCI and Ether/CEU/BCU/CSI (using DMA mode) simultaneously (Direction of usage) Details Using PCI and Ether / CEU / BCU / CSI (using DMA mode) simultaneously may occur a hangup, if following 3 conditions are all satisfied: (1) CPU reads PCI bus or PCIU register (0x0f000cxx / 0x0f000dxx). (2) External PCI master reads or writes SDRAM connected to VR4133. (3) When using DMA between Ether/CEU/external I/O(ROM)/CSI and SDRAM.
Operating Precautions for VR4133 TM (C) Valid Specification Item Date published Document No.
Operating Precautions for VR4133 TM (D) Revision History Item Date published Document No.
