Mos Integrated Circuit Data Sheet

µµ
µµ
µ
PD75P3116
39
Data Sheet U11369EJ3V0DS
SBI mode (SCK...Internal clock output (master)): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
SCK cycle time t
KCY3 VDD = 2.7 to 5.5 V 1300 ns
V
DD = 1.8 to 5.5 V 3800 ns
SCK high-/low-level tKL3, tKH3 VDD = 2.7 to 5.5 V tKCY3/2–50 ns
width V
DD = 1.8 to 5.5 V tKCY3/2–150 ns
SB0, 1 setup time t
SIK3 VDD = 2.7 to 5.5 V 150 ns
(to SCK↑)V
DD = 1.8 to 5.5 V 500 ns
SB0, 1 hold time (from SCK↑) tKSI3 tKCY3/2 ns
SB0, 1 output delay tKSO3 RL = 1 kΩ,VDD = 2.7 to 5.5 V 0 250 ns
time from SCK↓ CL = 100 pF
Note
VDD = 1.8 to 5.5 V 0 1000 ns
SB0, 1↓ from SCK↑ tKSB tKCY3 ns
SCK↓ from SB0, 1↓ t
SBK tKCY3 ns
SB0, 1 low-level width t
SBL tKCY3 ns
SB0, 1 high-level width tSBH tKCY3 ns
Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
SBI mode (SCK...External clock input (slave)): (T
A = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
SCK cycle time tKCY4 VDD = 2.7 to 5.5 V 800 ns
VDD = 1.8 to 5.5 V 3200 ns
SCK high-/low-level tKL4, tKH4 VDD = 2.7 to 5.5 V 400 ns
width VDD = 1.8 to 5.5 V 1600 ns
SB0, 1 setup time tSIK4 VDD = 2.7 to 5.5 V 100 ns
(to SCK↑)VDD = 1.8 to 5.5 V 150 ns
SB0, 1 hold time (from SCK↑) tKSI4 tKCY4/2 ns
SB0, 1 output delay tKSO4 RL = 1 kΩ,VDD = 2.7 to 5.5 V 0 300 ns
time from SCK↓ CL = 100 pF
Note
VDD = 1.8 to 5.5 V 0 1000 ns
SB0, 1↓ from SCK↑ tKSB tKCY4 ns
SCK↓ from SB0, 1↓ tSBK tKCY4 ns
SB0, 1 low-level width tSBL tKCY4 ns
SB0, 1 high-level width tSBH tKCY4 ns
Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.