Mos Integrated Circuit Data Sheet

µ PD75P3116
25
Data Sheet U11369EJ3V0DS
Instruction Mnemonic Operand No. of Machine Operation Addressing Skip
Group Bytes Cycle Area Condition
Branch BR
Note 1
addr ——PC13-0 ← addr *6
Use the assembler to select the
most appropriate instruction
among the following.
• BR !addr
• BRCB !caddr
• BR $addr
addr1 ——PC13-0 ← addr1 *11
Use the assembler to select
the most appropriate instruction
among the following.
• BRA !addr1
• BR !addr
• BRCB !caddr
• BR $addr1
!addr 3 3 PC13-0 ← addr *6
$addr 1 2 PC13-0 ← addr *7
$addr1 1 2 PC13-0 ← addr1
PCDE 2 3 PC13-0 ← PC13-8+DE
PCXA 2 3 PC13-0 ← PC13-8+XA
BCDE 2 3 PC13-0 ← BCDE
Note 2
*6
BCXA 2 3 PC13-0 ← BCXA
Note 2
*6
BRA
Note 1
!addr1 3 3 PC13-0 ← addr1 *11
BRCB !caddr 2 2 PC13-0 ← PC13, 12+caddr11-0 *8
Notes 1. The sections in double boxes are only supported in the Mk II mode. The other sections are only supported in
the MK I mode.
2. Only the lower two bits in the B register are valid.