User's Manua switch

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CHAPTER 3 CPU ARCHITECTURE

User’s Manual U12978EJ3V0UD

Table 3-2. Special Function Register List (1/3)

Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset

1 Bit 8 Bits 16 Bits

FF00H Port 0 P0 R/W √√— 00H

FF01H Port 1 P1 √√—

FF02H Port 2 P2 √√—

FF04H Port 4 P4 √√—

FF07H Receive data PID USBRD R — √ —

FF08H Receive data address 0

USBR0 USBR10

— √√Undefined

FF09H Receive data address 1

USBR1

— √

FF0AH Receive data address 2

USBR2 USBR32

— √√

FF0BH Receive data address 3

USBR3

— √

FF0CH Receive data address 4

USBR4 USBR54

— √√

FF0DH Receive data address 5

USBR5

— √

FF0EH Receive data address 6

USBR6 USBR76

— √√

FF0FH Receive data address 7

USBR7

— √

FF10H Transmit/receive shift register 10 SIO10 R/W — √ —

FF14H Handshake packet transmit reservation

HTX

RSV

USB

CON

√√ √00H

FF15H Data packet transmit reservation register DTX

RSV

√√

FF20H Port mode register 0 PM0 √√— FFH

FF21H Port mode register 1 PM1 √√—

FF22H Port mode register 2 PM2 √√—

FF24H Port mode register 4 PM4 √√—

FF30H Port output mode register 0 POM0 √√— 00H

FF31H Port output mode register 1 POM1 √√—

FF42H Timer clock select register 2 TCL2 — √ —

FF50H 8-bit compare register 00 CR00 W — √ — Undefined

FF51H 8-bit timer counter 00 TM00 R — √ — 00H

FF53H 8-bit timer mode control register 00 TMC00 R/W √√—

FF54H 8-bit compare register 01 CR01 W — √ — Undefined

FF55H 8-bit timer counter 01 TM01 R — √ — 00H

FF57H 8-bit timer mode control register 01 TMC01 R/W √√—

FF60H Token PID compare register TIDCMP W — √ —

FF61H Token address compare register ADRCMP — √ —

Note 16-bit access is possible only in short direct addressing.

Note