User’s Manual µPD789800 Subseries 8-Bit Single-Chip Microcontrollers µPD789800 µPD78F9801 Document No.
[MEMO] 2 User’s Manual U12978EJ3V0UD
NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity.
These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products.
Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors.
Major Revisions in This Edition Page Throughout Contents Deletion of CU-type and GB-3BS type packages Deletion of indication “under development” for µPD78F9801 p. 21 Modification of operating ambient temperature when flash memory is written in 1.1 Features p. 27 Addition of outline of timer in 1.7 Functions pp. 29, 31 to 33 Modification of handling of REGC and VPP pins pp. 35, 36 Correction of address values in Figure 3-1 Memory Map (µPD789800) and Figure 3-2 Memory Map (µPD78F9801) p.
INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the µPD789800 Subseries and who design and develop its application systems and programs. Target products: • µPD789800 Subseries: µPD789800 and µPD78F9801 Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization Two manuals are available for the µPD789800 Subseries: This manual and the Instruction Manual (common to the 78K/0S Series).
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µPD789800 Subseries User’s Manual This manual 78K/0S Series Instructions User’s Manual U11047E Documents Related to Development Tools (Software) (User’s Manuals) Document Name RA78K0S Assembler Package Document No.
Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice.
TABLE OF CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features ...................................................................................................................................... 21 Applications................................................................................................................................ 21 Ordering Information .................................................................................................................
3.3.4 3.4 3.4.1 Direct addressing ..........................................................................................................................51 3.4.2 Short direct addressing .................................................................................................................52 3.4.3 Special function register (SFR) addressing...................................................................................53 3.4.4 Register addressing ......................................
CHAPTER 7 7.1 7.2 7.3 7.4 Watchdog Timer Functions....................................................................................................... 91 Watchdog Timer Configuration ................................................................................................ 92 Registers Controlling Watchdog Timer ................................................................................... 93 Watchdog Timer Operation ............................................................................
11.4.2 Maskable interrupt acknowledgment operation...........................................................................173 11.4.3 Multiplexed interrupt servicing.....................................................................................................175 11.4.4 Interrupt request hold ..................................................................................................................177 CHAPTER 12 STANDBY FUNCTION..........................................................
B.1 B.2 Register Index (Alphabetic Order of Register Name) ........................................................... 229 Register Index (Alphabetic Order of Register Symbol)........................................................ 231 APPENDIX C 14 REVISION HISTORY ....................................................................................................
LIST OF FIGURES (1/4) Figure No. Title Page 2-1 Pin I/O Circuits ......................................................................................................................................... 34 3-1 Memory Map (µPD789800) ...................................................................................................................... 35 3-2 Memory Map (µPD78F9801)....................................................................................................................
LIST OF FIGURES (2/4) Figure No. 16 Title Page 6-7 Interval Timer Operation Timing of 8-Bit Timer/Event Counter 01............................................................ 86 6-8 Timing of External Event Counter Operation (with Rising Edge Specified) .............................................. 87 6-9 Timing of Square-Wave Output ................................................................................................................ 89 6-10 Start Timing of 8-Bit Timer Counter ......
LIST OF FIGURES (3/4) Figure No. Title Page 8-31 Flow Chart of NRZI Encoder Operation ................................................................................................. 150 8-32 Timing of Bit Stuffing/Strip Controller Operation .................................................................................... 151 8-33 Flow Chart of Bit Stuffing Control Operation ..........................................................................................
LIST OF FIGURES (4/4) Figure No. 18 Title Page 14-3 Example of Connection with Dedicated Flash Programmer ................................................................... 193 14-4 VPP Pin Connection Example.................................................................................................................. 195 14-5 Signal Conflict (Input Pin of Serial Interface)..........................................................................................
LIST OF TABLES (1/2) Table No. Title Page 2-1 Type of Pin I/O Circuit Recommended Connection of Unused Pins ........................................................ 33 3-1 Vector Table............................................................................................................................................. 37 3-2 Special Function Register List..................................................................................................................
LIST OF TABLES (2/2) Table No. 20 Title Page 12-3 STOP Mode Operation Status ................................................................................................................ 183 12-4 Operation After Release of STOP Mode ................................................................................................ 185 13-1 Hardware Status After Reset ..................................................................................................................
CHAPTER 1 GENERAL 1.1 Features • On-chip USB functions • Implements a USB (Universal Serial Bus) by connecting to Hub and Host. • Transfer speed: 1.5 Mbps (at 6.0 MHz operation with system clock) • On-chip regulator • Controls the USB port voltage by using a bus power supply (VREG = 3.3 ±0.3 V) dedicated to the USB driver/receiver.
CHAPTER 1 GENERAL 1.
CHAPTER 1 GENERAL 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products under development Products in mass production Y subseries supports SMB.
CHAPTER 1 GENERAL The major differences between subseries are shown below. Series for General-Purpose and LCD Drive Function Subseries Smallscale package, generalpurpose applications ROM Timer 8-Bit 10-Bit Capacity 8-Bit 16-Bit Watch WDT A/D A/D (Bytes) µPD789046 16 K µPD789026 4 K to 16 K µPD789088 16 K to 32 K 3 ch µPD789074 2 K to 8 K 1 ch µPD789014 2 K to 4 K 2 ch µPD789062 4K 1 ch 1 ch 1 ch 1 ch − − Serial Interface I/O VDD 1 ch (UART: 1ch) 34 1.
CHAPTER 1 GENERAL Series for ASSP Function Subseries ROM Timer 8-Bit 10-Bit Capacity 8-Bit 16-Bit Watch WDT A/D A/D (Bytes) − − I/O VDD Remarks MIN.Value 1 ch − − 2 ch (USB: 1ch) 31 4.0 V − 1 ch 8 ch − 1 ch (UART: 1ch) 30 4.0 V − − 1 ch 4 ch − 2 ch (UART: 1ch) 18 4.0 V − − 1 ch − − − 14 1.
CHAPTER 1 GENERAL 1.6 Block Diagram KR00 to KR07 Key return 0 8-bit timer 00 TI01/TO01/P26/INTP0 8-bit timer/event counter 01 78K/0S CPU core ROM Flash memory Port 0 P00 to P07 Port 1 P10 to P17 Port 2 P20 to P26 Port 4 P40 to P47 Watchdog timer REGC Regulator VREG USBDM USBDP Remark 26 USB function 0 RAM System control SCK10/P20 SO10/P21 SI10/P22 Serial interface 1 INTP0/P26 Interrupt control VDD0 VDD1 VSS0 VSS1 IC (VPP) The parenthesized values apply to the µPD78F9801.
CHAPTER 1 GENERAL 1.7 Functions µPD789800 Product µPD78F9801 Item Internal memory ROM Mask ROM 8 KB High-speed RAM 256 bytes Flash memory 16 KB Minimum instruction execution time 0.33 µs/1.33 µs (at 6.0 MHz operation with system clock) Instruction set • 16-bit operation • Bit manipulation (set, reset, and test) etc. I/O ports CMOS I/O 31 (Of the above COMS I/O ports, 18 ports can be switched to N-ch open-drain I/O ports.
CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions (1) Port pins Pin Name P00 to P07 I/O I/O Function Port 0 After Reset Alternate Function Input — Input — 8-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, use of on-chip pull-up resistors can be specified by pull-up resistor option register 0 (PU0). When used as an output port, CMOS output or N-ch open-drain output can be specified in 8-bit units by port output mode register 0 (POM0).
CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name I/O Function After Reset Alternate Function INTP0 Input External interrupt request input for which valid edge (rising and/or falling edge) can be specified Input P26/TI01/TO01 KR00 to Input Input for detecting key return signals Input P40 to P47 KR07 NC — No connection. Can be left open. — — REGC — Internally generated power supply for driving USB driver/receiver. Connect this pin to VSS via a 22 µF capacitor.
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port and can be set to the input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0). When these pins are used as an output port, CMOS output or N-ch open-drain output can be specified in 8-bit units by setting port output mode register 0 (POM0). 2.
CHAPTER 2 2.2.4 PIN FUNCTIONS P40 to P47 (Port 4) These pins constitute an 8-bit I/O port. In addition, they also function as key return signal detection pins. The following operation modes can be specified in 1-bit units. (1) Port mode In this mode, port 4 functions as an 8-bit I/O port. Port 4 can be set to the input or output mode in 1-bit units by using port mode register 4 (PM4). When used as an input port an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0).
CHAPTER 2 PIN FUNCTIONS 2.2.12 VPP (µPD78F9801 only) A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Handle this pin in either of the following ways. • Independently connect a 10 kΩ pull-down resistor. • Switch this pin to be directly connected to the dedicated flash programmer in programming mode or to VSS0 in normal operation mode using a jumper on the board. 2.2.
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 lists the types of I/O circuits for each pin and explains how unused pins are handled. Figure 2-1 shows the configuration of each type of I/O circuit. Table 2-1. Type of Pin I/O Circuit Recommended Connection of Unused Pins Pin Name P00 to P07 I/O Circuit Type 5-R I/O Input: I/O P10 to P17 P20/ SCK10 Recommended Connection of Unused Pins Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor.
CHAPTER 2 PIN FUNCTIONS Figure 2-1.
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µPD789800 Subseries can access 64 KB of memory space. Figures 3-1 and 3-2 show the memory maps. Figure 3-1.
CHAPTER 3 CPU ARCHITECTURE Figure 3-2.
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The following areas are allocated to the internal program memory space. (1) Vector table area A 26-byte area of addresses 0000H to 0019H is reserved as a vector table area. This area stores program start addresses to be used when branching by RESET input or interrupt request generation.
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing The µPD789800 Subseries provides a variety of addressing modes which take account of memory manipulability, etc. Especially at addresses corresponding to data memory area (FE00H to FFFFH), particular addressing modes are possible to meet the functions of the special function registers (SFR) and general-purpose registers. Figures 3-3 and 3-4 show the data memory addressing modes. Figure 3-3.
CHAPTER 3 CPU ARCHITECTURE Figure 3-4.
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µPD789800 Subseries provides the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence, statuses and stack memory. A program counter, a program status word, and a stack pointer are the control registers. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledgment operations of the CPU. When 0, the IE flag is set to the interrupt disabled status (DI), and interrupt requests other than nonmaskable interrupts are all disabled. When 1, the IE flag is set to the interrupt enabled status (EI). Interrupt request acknowledgment enable is controlled by the interrupt mask flag corresponding to each interrupt source.
CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-7. Configuration of Stack Pointer 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory.
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL). They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 3-10.
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike general-purpose registers, each special function register has a special function. The special function registers are allocated in the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register type.
CHAPTER 3 CPU ARCHITECTURE Table 3-2.
CHAPTER 3 CPU ARCHITECTURE Table 3-2.
CHAPTER 3 CPU ARCHITECTURE Table 3-2.
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. The CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions 7 0 CALL or BR Low Addr. High Addr.
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower-5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH.
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed.
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. An internal highspeed RAM and special function registers (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH), where short direct addressing is applied, is a part of the whole SFR area.
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by the register specification code or function name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code. This addressing can be carried out for all the memory spaces.
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µPD789800 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS. Figure 4-1.
CHAPTER 4 PORT FUNCTIONS Table 4-1. Functions of Ports Pin Name P00 to P07 I/O I/O Function Port 0 After Reset Alternate Function Input — Input — 8-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, use of on-chip pull-up resistors can be specified by pull-up resistor option register 0 (PU0). When used as an output port, CMOS output or N-ch open-drain output can be specified in 8-bit units by port output mode register 0 (POM0).
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports consists the following hardware. Table 4-2. Configuration of Port Parameter Control registers Configuration Port mode register (PMm: m = 0 to 2, 4) Pull-up resistor option register (PU0) Port output mode register (POMm: m = 0, 1) Ports Total: 31 (N-ch open-drain output is specifiable for 18 ports.
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 This is an 8-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using port mode register 0 (PM0). When the P00 to P07 pins are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (PU0). CMOS output or N-ch open-drain output can also be specified in 8-bit unit by using port output mode register 0 (POM0).
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is an 8-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1). When the P10 to P17 pins are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (PU0). CMOS output or N-ch open-drain output can also be specified in 8-bit unit by using port output mode register 0 (POM0).
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 This is a 7-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2). When using the P20 to P26 pins as input port pins, on-chip pull-up resistors can be connected in 7-bit units by using pull-up resistor option register 0 (PU0). When P25 or P26 is used, CMOS output or N-ch open-drain output can be specified in 1-bit units by using port output mode register 1 (POM1).
CHAPTER 4 PORT FUNCTIONS Figure 4-5.
CHAPTER 4 PORT FUNCTIONS Figure 4-6.
CHAPTER 4 PORT FUNCTIONS Figure 4-7.
CHAPTER 4 PORT FUNCTIONS Figure 4-8.
CHAPTER 4 PORT FUNCTIONS Figure 4-9.
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 4 This is an 8-bit I/O port with an output latch. Port 4 can be specified in the input or output mode in 1-bit units by using port mode register 4 (PM4). When using P40 to P47 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (PU0). The port is also used as a key return input. This port is set in the input mode when the RESET signal is input. Figure 4-10 shows a block diagram of port 4.
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function The following three types of registers control the ports. • Port mode registers (PM0, PM1, PM2, PM4) • Pull-up resistor option register (PU0) • Port output mode registers (POM0, POM1) (1) Port mode registers (PM0, PM1, PM2, PM4) These registers are used to set port input/output in 1-bit units. The port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets registers to FFH.
CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Secondary Function Pin Name Name P26 P40 to P47Note PMxx Pxx Input/Output TO01 Output 0 0 TI01 Input 1 × INTP0 Input 1 × KR00 to KR07 Input 1 × Note Set key return mode register 00 (KRM00) to 1 when using the alternate function (see Section 11.3 (5) Key return mode register 00 (KRM00)).
CHAPTER 4 PORT FUNCTIONS (3) Port output mode registers (POM0 and POM1) The port output mode registers (POM0 and POM1) are used to switch from CMOS output to N-ch open-drain output for port 0, port 1, pin P25, and pin P26. Set POM0 and POM1 with a 1-bit or 8-bit memory manipulation instruction. RESET input sets P0M0 and POM1 to 00H. Figure 4-13.
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operation The operation of a port differs depending on whether the port is set to the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port. The data once written to the output latch is retained until new data is written to the output latch.
CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is used. • System clock oscillator This circuit oscillates at 6.0 MHz. Oscillation can be stopped by executing the STOP instruction. 5.2 Clock Generator Configuration The clock generator consists of the following hardware. Table 5-1.
CHAPTER 5 CLOCK GENERATOR 5.3 Register Controlling Clock Generator The clock generator is controlled by the following register. • Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC selects the CPU clock and sets the of division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the PCC to 02H. Figure 5-2.
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillators 5.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal resonator (6.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and leave the X2 pin open. Figure 5-3 shows the external circuit of the system clock oscillator. Figure 5-3.
CHAPTER 5 CLOCK GENERATOR 5.4.2 Examples of incorrect resonator connection Figure 5-4 shows examples of incorrect resonator connection. Figure 5-4.
CHAPTER 5 CLOCK GENERATOR Figure 5-4. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched VSS0 X1 X2 5.4.3 Frequency divider The frequency divider divides the output of the system clock oscillator (fX) to generate various clocks. 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode.
CHAPTER 5 CLOCK GENERATOR 5.6 Changing Setting of CPU Clock 5.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed; the old clock is used for the duration of several instructions after that (see Table 5-2). Table 5-2.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 6.1 Functions of 8-Bit Timer/Event Counters 00 and 01 The 8-bit timer/event counters (TM00 and TM01) have the following functions. • Interval timer (TM00 and TM01) • External event counter (TM01 only) • Square wave output (TM01 only) The µPD789800 Subseries is provided with a 1-channel (TM01) 8-bit timer/event counter and a 1-channel (TM00) 8-bit timer. When reading the description of TM00, “timer/event counter” should be read as “ timer”.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Square wave output A square wave of arbitrary frequency can be output. Table 6-3. Square Wave Output Range of 8-Bit Timer/Event Counter 01 Minimum Pulse Width 2 /fX (2.67 µs) Maximum Pulse Width 2 /fX (682.7 µs) 4 2 /fX (42.7 µs) 8 Resolution 12 2 /fX (2.67 µs) 16 28/fX (42.7 µs) 4 2 /fX (10.9 ms) Remarks 1. fX: System clock oscillation frequency 2. The parenthesized values apply to operation at fX = 6.0 MHz 6.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-2.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 6.3 Registers Controlling 8-Bit Timer/Event Counters 00 and 01 The following two types of registers are used to control 8-bit timer/event counters 00 and 01. • 8-bit timer mode control registers 00 and 01 (TMC00 and TMC01) • Port mode register 2 (PM2) (1) 8-bit timer mode control register 00 (TMC00) This register enables/stops operation of 8-bit timer counter 00 (TM00) and sets the counter clock of 8-bit timer 00.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) 8-bit timer mode control register 01 (TMC01) TMC01 determines whether to enable or disable 8-bit timer counter 01 (TM01), specifies the count clock for the 8-bit timer/event counter, and controls the operation of the output controller. TMC01 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC01 to 00H. Figure 6-4.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Port mode register 2 (PM2) This register sets port 2 input/output in 1-bit units. When using the P26/TO01/INTP0/TI01 pin for timer output, set P26 and the output latch of P26 to 0. When P26/TO01/INTP0/TI01 pin is used as a timer input, set PM26 to 1. PM2 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH. Figure 6-5.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4 Operation of 8-Bit Timer/Event Counters 00 and 01 6.4.1 Operation as interval timer Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare registers 00 and 01 (CR00 and CR01) in advance. To operate the 8-bit timer/event counter as an interval timer, the following settings are required.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-6. Interval Timer Operation Timing of 8-Bit Timer 00 t Count clock TM00 count value 00 01 N 00 01 N Clear CR00 N 00 01 N Clear N N N Interrupt acknowledged Interrupt acknowledged TCE00 Count starts INTTM00 Interval time Remark Interval time Interval time Interval time = (N + 1) × t where N = 00H to FFH Figure 6-7.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.2 Operation as external event counter (timer 01 only) The external event counter counts the number of external clock pulses input to the TI01/P26/INTP0/TO01 pin by using timer counter 01 (TM01). To operate the 8-bit timer/event counter as an external event counter, the following settings are required. <1> Disable operation of 8-bit timer counter 01 (TM01) by setting TCE01 (bit 7 of 8-bit timer mode control register 01 (TMC01)) to 0.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.3 Operation as square-wave output (timer 01 only) The 8-bit timer/event counter can generate output square waves of arbitrary frequency at intervals specified by the count value set to 8-bit compare register 01 (CR01) in advance. To operate 8-bit timer/event counter 01 as square wave output, the following settings are required. <1> Set P26 to output mode (PM26 = 0) and the output latch of P26 to 0.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-9. Timing of Square-Wave Output Count clock TM01 count value CR01 00 01 N N 00 01 N 00 Clear Clear N N 01 N N TCE01 Count start INTTM01 Interrupt acknowledged Interrupt acknowledged TO01Note Note The initial value of TO01 when output is enabled (TOE01 = 1) becomes low level.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 6.5 Notes on Using 8-Bit Timer/Event Counters 00 and 01 (1) Error on starting timer An error of up to 1 clock occurs after the timer is started until a match signal is generated. This is because 8-bit timer counters 00 and 01 (TM00 and TM01) are started asynchronously to the count pulse. Figure 6-10.
CHAPTER 7 WATCHDOG TIMER 7.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect inadvertent program loops. When an inadvertent loop is detected, a nonmaskable interrupt or the RESET signal can be generated. Table 7-1.
CHAPTER 7 WATCHDOG TIMER 7.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 7-3. Configuration of Watchdog Timer Item Configuration Control register Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 7-1.
CHAPTER 7 WATCHDOG TIMER 7.3 Registers Controlling Watchdog Timer The following two registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Figure 7-2.
CHAPTER 7 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. The WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the WDTM to 00H. Figure 7-3.
CHAPTER 7 WATCHDOG TIMER 7.4 Watchdog Timer Operation 7.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started.
CHAPTER 7 WATCHDOG TIMER 7.4.2 Operation as interval timer When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a count value set in advance. Select the count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2).
CHAPTER 8 USB FUNCTION 8.1 USB Overview The USB (Universal Serial Bus) is suitable for connecting personal computers and external devices such as audio equipment, keyboards, pointing devices, and telephones. Two data transfer rates, 12 Mbps and 1.5 Mbps, are provided. Plug & Play can also be realized. Figure 8-1 shows an example of USB connection to a desktop PC.
CHAPTER 8 USB FUNCTION 8.2 USB Function Features The features of the on-chip USB function provided for the µPD789800 Subseries are described below. (1) Video display devices and human interface devices are assumed to be the target applications. For this reason, only Endpoint 0 for control transfer and Endpoint 1 for interrupt transfer are supported. (2) 1.5 Mbps (low speed) data transfer using a 6.0 MHz system clock is supported. (3) The following buffers are provided on-chip.
CHAPTER 8 USB FUNCTION Figure 8-2.
CHAPTER 8 USB FUNCTION Figure 8-3. Block Diagram of USB Timer INTUSBTM Shift register In highIn lowspeed mode speed mode UWDERR Clear circuit RESUME RXNote fX USBCLK Clock controller JUDGE TX Note JUDGE TOKEN Note TX MASTER ENNote SETRXNote OUT RXNote DATATX SETORX USB timer start reservation control register (USBTCL) Internal bus Note As these signals are used internally, confirmation by software is not possible.
CHAPTER 8 USB FUNCTION (1) Receive bank switching ID detection buffer (internal buffer) This is an internal 2-bit buffer placed before a receive buffer. It detects the lower 2 bits below the packet ID during packet reception and determines the store bank of a packet. The following controls are performed depending on the stored 2-bit data. For details, see Section 8.5.3 Receive bank switching ID detection buffer operation.
CHAPTER 8 USB FUNCTION (3) Receive token bank (a) Receive token PID (USBRTP) This is the receive token packet ID area. The data input to the token PID compare register (TIDCMP) is stored here. USBRTP is read with an 8-bit memory manipulation instruction. RESET input sets USBRTP to 00H. (b) Receive token address L and H (USBRAL and USBRAH) This stores the token packet to be transferred from the host. USBRAL and USBRAH consist of 16 bits.
CHAPTER 8 USB FUNCTION (4) Receive data bank (a) Receive data PID (USBRD) This is the receive data packet ID area. The data input to the data/handshake PID compare register (DIDCMP) is stored here. USBRD is read with an 8-bit memory manipulation instruction. RESET input sets USBRD to 00H. (b) Receive data address (USBR0 to USBR7) This is an 8-byte register that stores the data/handshake packet transferred from the host. USBR0 to USBR7 are read with an 8-bit memory manipulation instruction.
CHAPTER 8 USB FUNCTION (5) Transmit data banks 0 and 1 (a) Transmit data PID banks 0 and 1 (USBTD0 and USBTD1) USBTD0 and USBTD1 correspond to the transmit buffer 0 ID area and transmit buffer 1 ID area, respectively. USBTD0 and USBTD1 store DATA0 (C3H) or DATA1 (4BH). USBTD0 and USBTD1 are set with an 8-bit memory manipulation instruction. RESET input makes both USBTD0 and USBTD1 undefined.
CHAPTER 8 USB FUNCTION Figure 8-7. Configuration of Transmit Data Bank 1 (Buffer 1) USBPOB address 07H 06H 05H 04H USBTD1 03H 02H 01H 00H 30H ID area USBT10 31H USBT11 32H USBT12 33H USBT13 34H Data area (8 bytes) USBT14 35H USBT15 36H USBT16 37H USBT17 38H USBPOW address Symbol The operation during transmission appears as follows. Packet from host controller ACK IN Response packet ACK IN DATA1 DATA0 1st byte USBT00 . .. . .. .. .
CHAPTER 8 USB FUNCTION (6) Data/handshake packet receive byte number counter (DRXCON) This register sets the number of data of the data/handshake packet to be received. During data/handshake packet reception, if this register value and the transmit/receive pointer (USBPOW) value match, a match signal is output from the comparator. During data packet reception, set the USBPOW address at which the last byte before the appended CRC redundant bits is stored to DRXCON.
CHAPTER 8 USB FUNCTION (9) Token address compare register (ADRCMP) This register sets the address specified from the host during control transfer. If this register value and the address area of the receive token bank (bits 0 to 6 of receive token address L (USBRAL)) match during token packet reception coincide, ADRRST (bit 2 of the token packet receive result store register (TRXRSL)) is set. 00H must be set by software when an USB reset is received.
CHAPTER 8 USB FUNCTION (10) Data/handshake PID compare register (DIDCMP) This register sets the data/handshake packet ID to be received. If this register value and the value of the receive data PID (USBRD) match during data/handshake packet reception coincide, the DIDRST (bit 1 of the data/handshake packet receive result store register (DRXRSL)) is set. DIDCMP is set with an 8-bit memory manipulation instruction. RESET input sets DIDCMP to C3H. SETUP reception Note also sets DIDCMP to C3H.
CHAPTER 8 USB FUNCTION 8.4 Registers Controlling USB Function The following nine registers are used to control the USB function.
CHAPTER 8 USB FUNCTION Figure 8-11. Format of Data/Handshake Packet Receive Mode Register Symbol 7 6 5 4 3 URXMOD 0 0 0 0 0 <2> <1> <0> Address After reset R/W FF66H 00H R/W RESMOD DINTEN DWRMSK USB reset signal detection mode setting RESMOD 0 Reject USB reset signal less than 3.0 µ s SE0 (Single-ended 0) period. 1 Detect transition from J state to SE0 as USB reset signal.
CHAPTER 8 USB FUNCTION (3) Packet receive status register (RXSTAT) This register indicates the receive status of each packet. Bits 0 to 2 (TOSTAT, DASTAT, and HSSTAT) are flags that indicate that a token packet, data packet, or handshake packet is currently being received. These flags are set upon detection of a packet ID by an ID detection buffer, and cleared upon reception of EOP. Bits 3 to 6 (EOPRX, URESRX, SE0RX, RESMRX) are flags that detect bus status transition.
CHAPTER 8 USB FUNCTION Figure 8-12. Format of Packet Receive Status Register Symbol 7 6 5 4 3 2 1 0 RXSTAT UWDERR RESMRX SE0RX URESRX EOPRX HSSTAT DASTAT TOSTAT UWDERR After reset R/W FF67H 00H R/W USB timer inadvertent program loop detection 0 No USB timer inadvertent program loop was detected. 1 USB timer inadvertent program loop (USB clock operation faster than 85.3 µs (at 6.0 MHz)) was detected, forcibly terminating USB clock.
CHAPTER 8 USB FUNCTION Table 8-2 shows the state of each flag after receiving the USB reset signal and the Resume signal during the bus idle state and bus suspend state. Table 8-2.
CHAPTER 8 USB FUNCTION Figure 8-14. Format of Token Packet Receive Result Store Register Symbol <7> <6> TRXRSL CRC5ER TBITER CRC5ER <5> <4> <3> <2> TBYER END1RX END0RX ADRRST TIDRST CRC error did not occur in received token packet. 1 CRC error occurred in received token packet. Bit stuffing error did not occur in received token packet. 1 Bit stuffing error occurred in received token packet. Packet length of received token packet is normal.
CHAPTER 8 USB FUNCTION (6) Data packet transmit reservation register (DTXRSV) This register sets the bank where the data packet to be transmitted is stored. By setting each flag of this register, the stored data is transmitted following normal reception of the IN token packet. DTXRSV is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 8 USB FUNCTION (7) Handshake packet transmit reservation register (HTXRSV) This register sets the handshake packet to be transmitted. By setting each flag of this register, a handshake packet is transmitted following normal reception of an IN packet, or normal or abnormal reception of a data packet.
CHAPTER 8 USB FUNCTION Figure 8-16. Format of Handshake Packet Transmit Reservation Register (2/2) E1NAEN NAK packet transmit reservation flag for Endpoint 1 after IN packet 0 No data is transmitted. 1 NAK handshake is transmitted when all the following conditions are satisfied in EOP during IN packet reception. INRX (internal signal) = 1, ADRRST = 1, END1RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0 E0NAEN NAK packet transmit reservation flag for Endpoint 0 after IN packet 0 No data is transmitted.
CHAPTER 8 USB FUNCTION Table 8-3.
CHAPTER 8 USB FUNCTION Figure 8-17. Configuration of Handshake Packet Transmit Reservation Register E1STEN E0STEN DSTEN STALEN E1NAEN E0NAEN DNAEN ACKEN END1RX END0RX IN RXNote TIDRST ADRRST TBYER TBITER CRC5ER JUDGE TOKENNote TX MASTER ENNote JUDGE DATANote DIDRST DBYER DBITER CR16ER Note Because these signals are used internally, confirmation by software is not possible.
CHAPTER 8 USB FUNCTION (8) USB timer start reservation control register (USBTCL) This register reserves USB timer start after reception of a SETUP/OUT packet or transmission of a data packet. USBTCL is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets USBTCL to 01H. SETUP reception Note also sets USBTCL to 01H. Note SETUP reception implies the satisfaction of all the following three conditions. • Matching of address • Endpoint 0 received • No error in reception Figure 8-18.
CHAPTER 8 USB FUNCTION (9) Remote wake-up control register (REMWUP) This register transmits the Resume signal to perform remote wakeup. Remote wakeup must be performed after confirming that bus idle has continued longer than 5 ms. REMWUP is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets REMWUP to 08H. Figure 8-19.
CHAPTER 8 USB FUNCTION 8.5 USB Function Operation 8.5.1 USB timer operation The USB timer is a 7-bit counter that performs time management during packet transmission and reception and inadvertent program loop detection of the USB clock. The USB timer has two modes: high-speed mode (source clock = fX) and low-speed mode (source clock = USB clock: fX = 1.5 MHz during 6.0 MHz operation). In the high-speed mode, the USB functions as a 6-bit counter.
CHAPTER 8 USB FUNCTION Figure 8-20.
CHAPTER 8 USB FUNCTION Figure 8-20.
CHAPTER 8 USB FUNCTION 8.5.2 Remote wakeup control operation Figure 8-21.
CHAPTER 8 USB FUNCTION Notes 1. Be sure to follow the exact instruction sequence when the Resume signal (“K” state) is output. SET1 REMWUP.3 ; (PULLDM ← 1) CLR1 REMWUP.2 ; (PULLDP ← 0) MOV A, #00000111B ; (A ← 00000111B) “J” state generation SET1 REMWUP.1 ; (PULLEN ← 1) SET1 REMWUP.0 ; (WAKEUP ← 1), MOV REMWUP, A ; (REMWUP ← A), “K” state output “J” state output 2. Be sure to follow the exact instruction sequence to append EOP when terminating Resume output. CLR1 REMWUP.
CHAPTER 8 USB FUNCTION 8.6 Interrupt Request from USB Function 8.6.1 Interrupt sources Interrupt request sources generated by the USB function fall into the following five categories. Table 8-4.
CHAPTER 8 USB FUNCTION (3) Data/handshake packet transmit interrupt (INTUSBST) Upon EOP detection during data/handshake packet transmission, an interrupt request signal is generated and an interrupt request flag (USBSTIF) is set. (4) USB timer overflow interrupt (INTUSBTM) If the USB timer overflows, an interrupt request signal is generated and an interrupt request flag (USBTMIF) is set. (5) USB reset/Resume detection interrupt (INTUSBRE) This is an interrupt to release the STOP mode.
CHAPTER 8 USB FUNCTION 8.6.2 Cautions when using interrupts Pay attention to the following when using an interrupt request generated by the USB function. (1) Because USBREIF is set by transition from the J state to the K state on the bus, it is also set during sync detection or packet reception. Thus, disable the generation of interrupt requests by setting the interrupt mask flag (USBREMK) during bus idle or control transfer.
CHAPTER 8 USB FUNCTION 8.7 USB Function Control 8.7.1 Relationship between packets and operation modes The relationship between packets and operation modes in the USB function is as follows.
CHAPTER 8 USB FUNCTION (2) Control transfer (OUT) (Transfer byte count: 9 bytes or more) Packet flow Packet from host controller Setup stage Packet from µ PD789800 Operation of host controller SETUP Request • ACK transmission • NAK transmission reservation OUT OUT packet • NAK transmission reservation clear • ACK transmission reservation DATA1 • ACK transmission • NAK transmission reservation ACK OUT OUT packet • NAK transmission reservation clear • ACK transmission reservation DATA0 • ACK tr
CHAPTER 8 USB FUNCTION (3) Control transfer (IN) (Transfer byte count: 8 bytes or less) Packet flow Packet from host controller Setup stage Packet from µ PD789800 Operation of host controller SETUP Request Operation of USB function of µ PD789800 ACK transmission reservation DATA0 • ACK transmission • DATA1 transmission reservation ACK Data stage IN reception IN IN packet • DATA1 transmission • NAK transmission reservation DATA1 ACK NAK transmission reservation clear OUT Status stage OUT rece
CHAPTER 8 USB FUNCTION (4) Control transfer (IN) (Transfer byte count: 9 bytes or more) Packet flow Packet from host controller Setup stage Packet from µPD789800 Operation of host controller SETUP Operation of USB function of µPD789800 ACK transmission reservation Request DATA0 • ACK transmission • DATA1 transmission reservation ACK Data stage IN reception IN IN packet • DATA1 transmission • NAK transmission reservation DATA1 NAK transmission reservation clear ACK IN IN packet • NAK transmis
CHAPTER 8 USB FUNCTION (5) No data control Packet flow Packet from host controller Setup stage Packet from µPD789800 Operation of host controller SETUP Request Operation of USB function of µPD789800 ACK transmission reservation DATA0 • ACK transmission • DATA1 transmission reservation ACK Status stage No data control IN IN packet DATA1 ACK DATA1 transmission ACK packet NAK transmission reservation 134 User’s Manual U12978EJ3V0UD
CHAPTER 8 USB FUNCTION (6) Interrupt transfer Packet flow Packet from host controller Packet from µPD789800 Operation of host controller Operation of USB function of µPD789800 ACK transmission reservation IN • NAK transmission • DATA1 transmission reservation NAK IN IN packet • DATA1 transmission • NAK transmission reservation DATA1 ACK NAK transmission reservation clear IN IN packet • NAK transmission • DATA0 transmission reservation NAK IN IN packet • DATA0 transmission • NAK transmissio
CHAPTER 8 USB FUNCTION 8.7.
CHAPTER 8 USB FUNCTION (2) Data/handshake packet reception interrupt servicing INTUSBRD occurrence Planned packet was received? Yes No USB_MODE is data stage OUT reception? No Yes Re-transmit data reception reservation processing Transition processing to status stage OUT reception No USB_MODE is SETUP? USB_MODE is waiting for communication request? Yes No ACK reception processing to ENDPOINT 1 Yes USB request processing DATA/ACK reception processing to ENDPOINT 0 RETI User’s Manual U12978
CHAPTER 8 USB FUNCTION (3) USB timer inadvertent program loop detection interrupt servicing INTUSBTM occurrence Processing for each operation mode when ACK is not received and for when DATA is not received after receiving OUT RETI 138 User’s Manual U12978EJ3V0UD
CHAPTER 8 USB FUNCTION (4) 1 ms timer interrupt servicing INTTM00 occurrence DURATION base timer processing 10 ms timer counting USB communication completion timer processing Waiting for resume signal completion? Yes No RESET received? Yes No USB reset processing No Resume signal completion wait processing Communication operating? Yes Standby detected? No Yes Standby processing REMOTE WAKEUP? No Yes RESUME output processing RETI User’s Manual U12978EJ3V0UD 139
CHAPTER 8 USB FUNCTION 8.8 USB Function Internal Circuit Operations 8.8.1 Operation of transmit/receive pointer Figure 8-25.
CHAPTER 8 USB FUNCTION Figure 8-25.
CHAPTER 8 USB FUNCTION Figure 8-25.
CHAPTER 8 USB FUNCTION Figure 8-25.
CHAPTER 8 USB FUNCTION Figure 8-25.
CHAPTER 8 USB FUNCTION Figure 8-25.
CHAPTER 8 USB FUNCTION Figure 8-25.
CHAPTER 8 USB FUNCTION 8.8.2 Receive bank switching ID detection buffer operation Figure 8-26.
CHAPTER 8 USB FUNCTION 8.8.3 Sync detection/USBCLK detector operation This circuit generates the USBCLK signal (1.5 MHz) upon detecting the sync part of the receive packet. In addition, it contains an NRZI decoder that decodes receive packets and detects the last bit of the sync part. When the last sync bit is detected, a signal that specifies start of storing in the ID detection buffer is output. Figure 8-27.
CHAPTER 8 USB FUNCTION Figure 8-29.
CHAPTER 8 USB FUNCTION 8.8.4 NRZI encoder operation This circuit performs NRZI encoding of data to be transmitted. Figure 8-30. Timing of NRZI Encoder Operation Data before encoding Sync pattern Data/handshake packet NRZI encoding Transmit packet USB clock generation Figure 8-31. Flow Chart of NRZI Encoder Operation Idle state Transmit start? N Y Sync.
CHAPTER 8 USB FUNCTION 8.8.5 Bit stuffing/strip controller operation This circuit counts the number of “logic 1” of transmit/receive packets. If six successive logic 1s are detected, it outputs an increment disable signal to the transmit/receive pointer (USBPOB). During packet transmission, it inserts “logic 0” simultaneously with the increment disable signal. Moreover, during bit stripping, if the bit that should be deleted was a “logic 1,” this is detected as a bit stuffing error. Figure 8-32.
CHAPTER 8 USB FUNCTION Figure 8-33.
CHAPTER 8 USB FUNCTION Figure 8-34.
CHAPTER 9 SERIAL INTERFACE 10 9.1 Functions of Serial Interface 10 Serial interface 10 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out. It enables a reduction in power consumption. (2) 3-wire serial I/O mode (MSB/LSB start bit switchable) In this mode, 8-bit data transfer is carried out with three lines: one for the serial clock (SCK10) and two for serial data (SI10 and SO10).
CHAPTER 9 SERIAL INTERFACE 10 9.2 Configuration of Serial Interface 10 Serial interface 10 consists of the following hardware. Table 9-1.
Figure 9-1.
CHAPTER 9 SERIAL INTERFACE 10 9.3 Register Controlling Serial Interface 10 The following register is used to control serial interface 10. • Serial operation mode register 10 (CSIM10) (1) Serial operation mode register 10 (CSIM10) This register is used to control serial interface 10 and set the serial clock and start bit. CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM10 to 00H. Figure 9-2.
CHAPTER 9 SERIAL INTERFACE 10 Table 9-2.
CHAPTER 9 SERIAL INTERFACE 10 9.4 Operation of Serial Interface 10 Serial interface 10 provides the following two modes. • Operation stop mode • 3-wire serial I/O mode 9.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. The P20/SCK10, P21/SO10, and P22/SI10 pins can be used as normal I/O ports. (1) Register setting Operation stop mode is set by serial operation mode register 10 (CSIM10).
CHAPTER 9 SERIAL INTERFACE 10 9.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10).
CHAPTER 9 SERIAL INTERFACE 10 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Transmit/receive shift register 10 (SIO10) shift operations are performed in synchronization with the fall of the serial clock (SCK10). Then transmit data is held in the SO10 latch and output from the SO10 pin.
CHAPTER 10 REGULATOR The µPD789800 incorporates a regulator that powers the USB driver/receiver. The features are as follows. • Generates VREG (3.3 ±0.3 V) from VDD0, VDD1 (4.0 to 5.5 V) and outputs it to the REGC pin. • Supports power-saving mode, reducing power consumption in mode. Figure 10-1. Block Diagram of Regulator and USB Driver/Receiver µPD789800 VDD0 Regulator VREG REGC 22 µF VSS0 1.
CHAPTER 11 INTERRUPT FUNCTIONS 11.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does no undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) Maskable interrupt These interrupts undergo mask control.
CHAPTER 11 INTERRUPT FUNCTIONS Table 11-1.
CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-1.
CHAPTER 11 INTERRUPT FUNCTIONS 11.3 Registers Controlling Interrupt Function The following five registers are used to control the interrupt functions. • Interrupt request flag registers 0 and 1 (IF0 and IF1) • Interrupt mask flag registers 0 and 1 (MK0 and MK1) • External interrupt mode register 0 (INTM0) • Program status word (PSW) • Key return mode register 00 (KRM00) Table 11-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. Table 11-2.
CHAPTER 11 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0 and IF1) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgement of an interrupt request or upon RESET input. IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets IF0 and IF1 to 00H. Figure 11-2.
CHAPTER 11 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 to FFH. Figure 11-3.
CHAPTER 11 INTERRUPT FUNCTIONS (4) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped here. Besides 8-bit unit read/write, this register can carry out operations with bit manipulation instructions and dedicated instructions (EI, DI).
CHAPTER 11 INTERRUPT FUNCTIONS (5) Key return mode register 00 (KRM00) This register sets the pin that detects a key return signal (rising edge of port 4). KRM00 is set with a 1-bit an 8-bit memory manipulation instruction. Bit 0 (KRM000) is set in 4-bit units for the KR00/P40 to KR03/P43 pins. Bits 4 to 7 (KRM004 to KRM007) are set in 1-bit units for the KR04/P44 to KR07/P47 pins, respectively. RESET input sets KRM00 to 00H.
CHAPTER 11 INTERRUPT FUNCTIONS 11.4 Interrupt Servicing Operation 11.4.1 Non-maskable interrupt acknowledgment operation The non-maskable interrupt is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts.
CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-8. Flowchart of Non-Maskable Interrupt Request Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) No Interval timer Yes No WDT overflows Yes WDTM3 = 0 No (non-maskable interrupt is selected) Reset processing Yes Interrupt request is generated Interrupt servicing is started WDTM: Watchdog timer mode register WDT: Watchdog timer Figure 11-9.
CHAPTER 11 INTERRUPT FUNCTIONS 11.4.2 Maskable interrupt acknowledgment operation A maskable interrupt can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE flag is set to 1). The time required to start the interrupt servicing after a maskable interrupt request has been generated is as follows. Table 11-3.
CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-12. Timing of Interrupt Request Acknowledgment (Example of MOV A,r) 8 clocks Clock Saving PSW and PC, and jump to interrupt handling MOV A,r CPU Interrupt servicing program Interrupt When an interrupt request flag (xxIF) is generated before clock n (n = 4 to 10) of the instruction being executed turns to n - 1, the interrupt is acknowledged after the instruction has been executed. Figure 11-12 shows an example for 8-bit data transfer instruction MOV A,r.
CHAPTER 11 INTERRUPT FUNCTIONS 11.4.3 Multiplexed interrupt servicing Servicing in which another interrupt is acknowledged while an interrupt is being processed is called multiplexed interrupt servicing. Multiplexed interrupt is not performed unless interrupt requests are enabled (IE = 1) (except the non-maskable interrupt request). Other interrupt requests are disabled (IE = 0) as soon as an interrupt request is acknowledged.
CHAPTER 11 INTERRUPT FUNCTIONS Figure 11-14. Example of Multiplexed Interrupt Servicing Example 1. Acknowledging multiplexed interrupts INTxx processing Main processing EI IE = 0 INTxx EI INTyy processing IE = 0 INTyy RETI RETI The interrupt request INTyy is acknowledged and multiplexed interrupt servicing is performed during the interrupt INTxx servicing. Before each interrupt is acknowledged, the IE instruction is issued and interrupt requests are enabled. Example 2.
CHAPTER 11 INTERRUPT FUNCTIONS 11.4.4 Interrupt request hold If an interrupt (such as a maskable, non-maskable, or external interrupt) is requested when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed.
CHAPTER 12 STANDBY FUNCTION 12.1 Standby Function and Configuration 12.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU. The system clock oscillator continues oscillating.
CHAPTER 12 STANDBY FUNCTION 12.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. 15 RESET input sets OSTS to 04H. However, it takes 2 /fX until oscillation stabilizes after RESET input. Figure 12-1.
CHAPTER 12 STANDBY FUNCTION 12.2 Standby Function Operation 12.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 12-1. HALT Mode Operation Status Item HALT Mode Operation Status Clock generator Oscillation enabled CPU Operation disabled Port (output latch) Remains in the state before the selection of HALT mode.
CHAPTER 12 STANDBY FUNCTION (2) Releasing HALT mode The HALT mode can be released by the following three sources. (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed. If interrupts are disabled, the instruction at the next address is executed. Figure 12-2.
CHAPTER 12 STANDBY FUNCTION (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 12-3. Releasing HALT Mode by RESET Input Wait (215/f X : 5.46 ms) HALT instruction RESET signal Operation mode Clock HALT mode Reset period Oscillation stabilization wait status Oscillation Oscillation stops Oscillation Operation mode Remarks 1.
CHAPTER 12 STANDBY FUNCTION 12.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 pin is internally pulled up to VDD to suppress the current leakage of the crystal oscillator block. Therefore, do not use the STOP mode in a system where an external clock is used as the system clock. 2.
CHAPTER 12 STANDBY FUNCTION (2) Releasing STOP mode The STOP mode can be released by the following two sources. (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed. If interrupt acknowledgement is disabled, the instruction at the next address is executed. Figure 12-4.
CHAPTER 12 STANDBY FUNCTION (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 12-5. Releasing STOP Mode by RESET Input Wait (215/f X : 5.46 ms) STOP instruction RESET signal Operation mode STOP mode Oscillation stops Oscillation Clock Oscillation stabilization wait status Reset period Operation mode Oscillation Remarks 1. fX: System clock oscillation frequency 2.
CHAPTER 13 RESET FUNCTION The following two operations are available to generate reset signals. (1) External reset input via RESET pin (2) Internal reset by inadvertent program loop time detected by watchdog timer External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
CHAPTER 13 RESET FUNCTION Figure 13-2. Reset Timing by RESET Input X1 Oscillation stabilization time wait Reset period (oscillation stops) During normal operation Normal operation (reset processing) RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 13-3.
CHAPTER 13 RESET FUNCTION Table 13-1. Hardware Status After Reset (1/2) Hardware Note 1 Status After Reset Program counter (PC) The contents of reset vector tables (0000H and 0001H) are set.
CHAPTER 13 RESET FUNCTION Table 13-1.
CHAPTER 14 µPD78F9801 The µPD78F9801 is a product that substitutes flash memory for the internal ROM of the mask ROM version. The differences between the µPD78F9801 and the mask ROM versions are shown in Table 14-1. Table 14-1.
CHAPTER 14 µPD78F9801 14.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FLPR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the µPD78F9801 mounted on the target system (on-board). A flash memory program adapter (FA adapter), which is a target board used exclusively for programming, is also provided.
CHAPTER 14 µPD78F9801 14.1.2 Communication mode Use the communication mode shown in Table 14-2 to perform communication between the dedicated flash programmer and µPD78F9801. Table 14-2. Communication Mode List Communication Mode TYPE SettingNote 1 COMM PORT SIO Clock 3-wire serial I/O SIO ch-0 100 Hz to (3-wire, sync.) 1.25 MHzNote 2 Pseudo-3-wire Port A (pseudo3-wire) 100 Hz to 1 kHz CPU Clock Pins Used Flash Clock Note 2 Multiple Rate Optional 1 to 5 MHz 1.0 Optional 1 to 5 MHzNote 2 1.
CHAPTER 14 µPD78F9801 Figure 14-3. Example of Connection with Dedicated Flash Programmer (a) 3-wire serial I/O µ PD78F9801 Dedicated flash programmer VPP1 VPP VDD VDD0, VDD1 RESET RESET SCK SCK10 SO SI10 SI SO10 CLKNote X1 GND VSS0, VSS1 (b) Pseudo-3-wire µ PD78F9801 Dedicated flash programmer VPP1 VDD RESET VPP VDD0, VDD1 RESET SCK P10 SO P12 SI P11 CLKNote GND X1 VSS0, VSS1 Note Connect this pin when the system clock is supplied from the dedicated flash programmer.
CHAPTER 14 µPD78F9801 If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the µPD78F9801. For details, refer to the manual of Flashpro III/Flashpro IV. Table 14-3.
CHAPTER 14 µPD78F9801 14.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 10.0 V (TYP.
CHAPTER 14 (1) µPD78F9801 Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status. Figure 14-5.
CHAPTER 14 µPD78F9801 If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash programmer. Figure 14-7.
CHAPTER 14 µPD78F9801 14.1.4 Connection of adapter for flash writing The following figure shows an example of recommended connection when the adapter for flash writing is used. Figure 14-8. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O VDD (4.0 to 5.
CHAPTER 14 µPD78F9801 Figure 14-9. Wiring Example for Flash Writing Adapter with Pseudo-3-Wire Method VDD (4.0 to 5.
CHAPTER 15 INSTRUCTION SET This chapter lists the instruction set of the µPD789800 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instruction User’s Manual (U11047E). 15.1 Operation 15.1.1 Operand identifiers and description methods Operands are described in the “Operands” column of each instruction in accordance with the description method of the instruction operand identifier (see the assembler specifications for details).
CHAPTER 15 INSTRUCTION SET 15.1.
CHAPTER 15 INSTRUCTION SET 15.
CHAPTER 15 Mnemonic Operands Bytes INSTRUCTION SET Clocks Operation Flag Z AC CY MOVW rp,#word 3 6 rp ← word AX,saddrp 2 6 AX ← (saddrp) saddrp,AX 2 8 (saddrp) ← AX Note 1 4 AX ← rp Note 1 4 rp ← AX Note AX,rp rp,AX XCHW AX,rp 1 8 AX ↔ rp ADD A,#byte 2 4 A,CY ← A+byte × × × saddr,#byte 3 6 (saddr),CY ← (saddr) + byte × × × A,r 2 4 A,CY ← A+r × × × A,saddr 2 4 A,CY ← A+(saddr) × × × A,!addr16 3 8 A,CY ← A+(addr16) × × × A,[HL] 1 6 A,CY
CHAPTER 15 Mnemonic Operands Bytes INSTRUCTION SET Clocks Operation Flag Z AC CY SUBC AND OR XOR Remark A,#byte 2 4 A,CY ← A−byte−CY × × × saddr,#byte 3 6 (saddr),CY ← (saddr)−byte−CY × × × A,r 2 4 A,CY ← A−r−CY × × × A,saddr 2 4 A,CY ← A−(saddr)−CY × × × A,!addr16 3 8 A,CY ← A−(addr16)−CY × × × A,[HL] 1 6 A,CY ← A−(HL)−CY × × × A,[HL+byte] 2 6 A,CY ← A−(HL+byte)−CY × × × A,#byte 2 4 A ← A∧byte × saddr,#byte 3 6 (saddr) ← (saddr)∧byte ×
CHAPTER 15 Mnemonic Operands Bytes INSTRUCTION SET Clocks Operation Flag Z AC CY A,#byte 2 4 A−byte × × × saddr,#byte 3 6 (saddr)−byte × × × A,r 2 4 A−r × × × A,saddr 2 4 A−(saddr) × × × A,!addr16 3 8 A−(addr16) × × × A,[HL] 1 6 A−(HL) × × × A,[HL+byte] 2 6 A−(HL+byte) × × × ADDW AX,#word 3 6 AX,CY ← AX+word × × × SUBW AX,#word 3 6 AX,CY ← AX−word × × × CMPW AX,#word 3 6 AX−word × × × INC r 2 4 r ← r+1 × × saddr 2 4 (
CHAPTER 15 Mnemonic Operands Bytes INSTRUCTION SET Clocks Operation Flag Z AC CY CALL !addr16 3 6 (SP−1) ← (PC+3)H, (SP−2) ← (PC+3)L, PC ← addr16, SP ← SP−2 CALLT [addr5] 1 8 (SP−1) ← (PC+1)H, (SP−2) ← (PC+1)L, PCH ← (00000000, addr5+1), PCL ← (00000000, addr5), SP ← SP−2 RET 1 6 PCH ← (SP+1), PCL ← (SP), SP ← SP+2 RETI 1 8 PCH ← (SP+1), PCL ← (SP), PSW ← (SP+2), SP ← SP+3, NMIS ← 0 PSW 1 2 (SP−1) ← PSW, SP ← SP−1 rp 1 4 (SP−1) ← rpH, (SP−2) ← rpL, SP ← SP−2 PSW 1 4 PSW
CHAPTER 15 INSTRUCTION SET 15.
CHAPTER 15 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word rpNote AX saddrp SP None 1st Operand AX ADDW SUBW CMPW rp MOVW MOVW XCHW MOVW MOVWNote saddrp MOVW SP MOVW INCW DECW PUSH POP Note Only when rp = BC, DE, or HL . (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand $addr16 None 1st Operand 208 MOVW A.bit BT BF SET1 CLR1 sfr.bit BT BF SET1 CLR1 saddr.bit BT BF SET1 CLR1 PSW.
CHAPTER 15 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand AX !addr16 [addr5] $addr16 1st Operand Basic Instructions BR CALL BR Compound Instructions CALLT BR BC BNC BZ BNZ DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U12978EJ3V0UD 209
CHAPTER 16 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C) Parameter Symbol Supply voltage Conditions VDD µPD78F9801 only VPP Note 1 Rating Unit −0.3 to +6.5 V −0.3 to +10.5 V VI −0.3 to VDD + 0.3Note 2 V Output voltage VO −0.3 to VDD + 0.
CHAPTER 16 ELECTRICAL SPECIFICATIONS System Clock Oscillation Circuit Characteristics (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V) Resonator Recommended Circuit Crystal VPP X1 C1 External clock X1 X2 C2 Parameter Conditions Note 1 Oscillator frequency (fX) MIN. TYP. MAX. Unit 6.0 6.0 6.0 MHz 10 ms 6.0 MHz 83 ns Oscillation stabilization timeNote 2 X2 X1 input frequency (fX)Note 1 6.0 X1 input high-low-level width (tXH, tXL) 71 OPEN 6.0 Notes 1.
CHAPTER 16 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V) (1/2) Parameter Output current, high Output current, low Input voltage, high Symbol IOH IOL Conditions MAX. Unit Per pin −1 mA Total for all pins −15 mA Per pin 10 mA Total for all pins 80 mA VDD V VIH1 P00 to P07, P10 to P17 VIH2 RESET, P20 to P26, P40 to P47 VIH3 X1 VIH4 USBDM, USBDP TA = 0 to +70°C VIL1 MIN. TYP. 0.7VDD 0.8VDD VDD V VDD − 0.1 VDD V 2.0 3.
CHAPTER 16 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V) (2/2) Parameter Note 1 Supply current (Mask ROM Version) Supply currentNote 1 (µPD78F9801) Symbol Conditions MIN. TYP. MAX. Unit IDD1 6.0 MHz crystal oscillation (operating mode)Note 2 1.5 3.0 mA IDD2 6.0 MHz crystal oscillation (HALT mode)Note 2 0.5 1.
CHAPTER 16 ELECTRICAL SPECIFICATIONS AC Characteristics (1) Basic operations (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V) Parameter Symbol Cycle time (minimum instruction execution time) TCY TI01 input frequency fTI TI01 input high-/low-level width tTIH, tTIL Interrupt input high-/low-level width tINTH, tINTL RESET input low-level width tRSL Conditions MIN. TYP. MAX. Unit When PCC = 00H (fX = 6.0 MHz) 0.333 0.333 0.333 µs When PCC = 02H (fX = 6.0 MHz) 1.333 1.333 1.333 µs 4.
CHAPTER 16 ELECTRICAL SPECIFICATIONS (b) 3-wire serial I/O mode (TA = −40 to +85°°C, VDD = 4.0 to 5.5 V) (i) SCK10 ...Internal clock output (when fX = 6.0 MHz) Parameter SCK10 cycle time Symbol tKCY1 Conditions Note 1 Note 1 Note 1 Note 1 When TPS100 When TPS100 SCK10 high-/low-level width SI10 setup time SI10 hold time tKH1, tKL1 When TPS100 tSIK1 To SCK10 ↑ tKSI1 From SCK10 ↑ When TPS100 MIN. TYP. MAX.
CHAPTER 16 ELECTRICAL SPECIFICATIONS AC Timing Measurement Points (Except X1 Input and USB Function) 0.8VDD 0.8VDD Measurement points 0.2VDD 0.2VDD Clock timing 1/fX tXH tXL VIH3 (MIN.) X1 input VIL3 (MAX.
CHAPTER 16 ELECTRICAL SPECIFICATIONS Serial Transfer Timing USB function: USBDM and USBDP rise/fall time 0.9VDD USBDM, USBDP 0.1VDD tR tF Transmission differential signal jitter 1,333 ns 667 ns Bit following the next bit Next bit USBDM, USBDP tUDJ2 tUDJ1 Differential output signal cross-over point, transmission EOP width, reception EOP width, and reception USB reset width USBDM, USBDP VCRS tEOPT1, tEOPRm, tURESm m = 1, 2 3-wire serial I/O mode: tKCYm tKLm tKHm 0.8VDD SCK10 0.
CHAPTER 16 ELECTRICAL SPECIFICATIONS Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°°C) Item Symbol Conditions MIN. Data hold supply voltage VDDDR 4.0 Release signal set time tSREL 0 Oscillation stabilization timeNote 1 Notes 1. tWAIT TYP. MAX. Unit 5.
CHAPTER 17 PACKAGE DRAWINGS 44 PIN PLASTIC LQFP (10x10) A B detail of lead end 23 22 33 34 S P C T D R 12 11 44 1 L U Q F J G H I M K M N S S ITEM MILLIMETERS NOTE A 12.0±0.2 Each lead centerline is located within 0.20 mm of its true position (T.P.) at maximum material condition. B 10.0±0.2 C 10.0±0.2 D 12.0±0.2 F 1.0 G 1.0 H 0.37 +0.08 −0.07 User’s Manual U12978EJ3V0UD I 0.20 J 0.8 (T.P.) K 1.0±0.2 L 0.5 M 0.17 +0.03 −0.06 N 0.10 P Q 1.4±0.05 0.1±0.
CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS The µPD789800 Subseries should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 18-1.
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the µPD789800 Subseries. Figure A-1 shows the development tools. • Support of the PC98-NX series Unless otherwise stated, the µPD789800 Subseries, which is supported by IBM PC/AT™ and compatibles, can be used for the PC98-NX series. When using the PC98-NX series, refer to the descriptions of IBM PC/AT and compatibles. • Windows Unless otherwise stated, “Windows” indicates the following OSs.
APPENDIX A DEVELOPMENT TOOLS Figure A-1.
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S Software tools for development of the 78K/0S Series are combined in this package. The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files Software package Part number: µS××××SP78K0S ×××× in the part number differs depending on the OS used. Remark µS××××SP78K0S ×××× AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Japanese Windows Supply Medium CD-ROM English Windows A.
APPENDIX A Remark DEVELOPMENT TOOLS ×××× in the part number differs depending on the host machine and operating system to be used. µS××××RA78K0S µS××××CC78K0S ×××× AB13 BB13 Host Machine PC-9800 series, IBM PC/AT compatibles AB17 OS Japanese Windows 3.5" 2HD FD English Windows Japanese Windows BB17 Supply Medium CD-ROM English Windows TM 3P17 HP9000 series 700 HP-UXTM (Rel. 10.10) 3K17 SPARCstationTM SunOSTM (Rel. 4.1.4), SolarisTM (Rel. 2.5.
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator In-circuit emulator for debugging hardware and software of an application system using the 78K/0S Series. Supports a integrated debugger (ID78K0S-NS). Used in combination with an AC adapter, emulation probe, and interface adapter for connecting the host machine.
APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS Integrated debugger This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the 78K/0S Series. The ID78K0S-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result.
APPENDIX A DEVELOPMENT TOOLS A.7 Notes on Target System Design Figures A-2 and A-3 show the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Figure A-2.
APPENDIX A DEVELOPMENT TOOLS Figure A-3. Connection Condition of Target System (NP-H44GB-TQ) Emulation board IE-789801-NS-EM1 Emulation probe NP-H44GB-TQ 23 mm 11 mm 10 mm Conversion adapter TGB-044SAP 40 mm 34 mm Target system Remarks 1. NP-H44GB-TQ is a product of Naito Densei Machida Mfg. Co., Ltd. 2. TGB-044SAP is a product of TOKYO ELETECH CORPORATION.
APPENDIX B REGISTER INDEX B.1 Register Index (Alphabetic Order of Register Name) 8-bit compare register 00 (CR00) .......................................................................................................................... 81 8-bit compare register 01 (CR01) .......................................................................................................................... 81 8-bit timer mode control register 00 (TMC00) .................................................................
APPENDIX B REGISTER INDEX Port mode register 2 (PM2) .................................................................................................................................... 69 Port mode register 4 (PM4) .................................................................................................................................... 69 Port output mode register 0 (POM0) ......................................................................................................................
APPENDIX B REGISTER INDEX B.2 Register Index (Alphabetic Order of Register Symbol) [A] ADRCMP: Token address compare register ...................................................................................... 107 [C] CR00: 8-bit compare register 00................................................................................................... 81 CR01: 8-bit compare register 01...................................................................................................
APPENDIX B PU0: REGISTER INDEX Pull-up resistor option register 0 ........................................................................................ 70 [R] REMWUP: Remote wake-up control register ..................................................................................... 121 RXSTAT: Packet receive status register .......................................................................................... 111 [S] SIO10: Transmit/receive shift register 10 ...............................
APPENDIX C REVISION HISTORY The revision history is described below. The “Applied to” column indicates the chapters in each edition.
APPENDIX C REVISION HISTORY (2/2) Edition 3rd Major Revisions from Previous Edition Correction of address values in Figure 3-1 Memory Map (µPD789800) and Figure 3-2 Memory Map (µPD78F9801) CHAPTER 3 CPU ARCHITECTURE Modification of Figure 5-3 External Circuit of System Clock Oscillator (b) External clock CHAPTER 5 CLOCK GENERATOR • Modification of chapter composition • Standardization of buffer name indications as receive token bank, receive data bank, and transmit data banks 0 and 1 • Addition of im
