Electronics America Computer Hardware User Manual

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Contents
8-1 Modes Generating the INTAD......................................................................................................225
8-2 A/D Conversion Time ....................................................................................................................232
8-3 Conditions to Generate Interrupt Requests in Each A/D Converter Operating Mode .........239
9-1 Causes of Reception Errors ..........................................................................................................250
9-2 Baud Rate Setting ..........................................................................................................................254
9-3 Example of Setting the BRGC Register When the Baud Rate Generator for UART Is Used ....... 255
9-4 Example of Setting the Baud Rate When 8-Bit Timer/Counter 3 Is Used
(Asynchronous Serial Interface) ..................................................................................................257
9-5 Examples of Setting the BRGC When an External Baud Rate Input (ASCK) Is Used ..........258
10-1 Reading/Writing the Contents of the SBIC Register .................................................................263
10-2 Signals in SBI Mode ......................................................................................................................284
10-3 Conditions Governing Release of BUSY ....................................................................................287
11-1 Pins P20 to P26 and Use of Detected Edge ...............................................................................293
12-1 Interrupt Request Handling Modes .............................................................................................301
12-2 Interrupt Request Sources ...........................................................................................................302
12-3 Flags for Interrupt Request Sources ...........................................................................................305
12-4 Multiple-Interrupt Handling .........................................................................................................313
12-5 Interrupt Request Acceptance Processing Time .......................................................................317
12-6 Macro Service Processing Time ..................................................................................................318
12-7 Interrupts That Can Use a Macro Service ..................................................................................320
12-8 Interrupt Requests That Can Specify Macro Service and Related SFRs (Type A) ................324
12-9 Illegal Write Access Conditions and Corresponding Operations ...........................................324
12-10 Interrupt Requests That Can Specify Macro Service and SFRs (Type C) ..............................331
12-11 Illegal Write Access Conditions and Corresponding Operations ...........................................331
12-12 Illegal Write Access Conditions and Corresponding Operations ...........................................344
13-1 Conditions and Operations for Illegal Write Access .................................................................350
13-2 System Clock Frequency and Refresh Pulse Output Cycle
When Pseudo Static RAM Is Used ..............................................................................................368
13-3 Conditions and Operations for Illegal Write Access .................................................................373
14-1 Operation States in HALT Mode .................................................................................................379
14-2 Sources for Releasing HALT Mode and Operations Performed After Release .....................380
14-3 Release of HALT Mode by a Maskable Interrupt Request .......................................................381
14-4 Operation States in STOP Mode .................................................................................................382
15-1 Pin States during Reset and After Reset State Is Released .....................................................390
15-2 Hardware States after Reset ........................................................................................................391
17-1 Operating Modes for PROM Programming ...............................................................................399
18-1 8-Bit Instructions for Each Addressing Type .............................................................................416
18-2 16-Bit Instructions for Each Addressing Type ...........................................................................417
18-3 Bit Manipulation Instructions for Each Addressing Type ........................................................418
18-4 Call Instructions and Branch Instructions for Each Addressing Type....................................419
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