USER'S MANUAL µPD78214 SUB-SERIES 8-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE µPD78212 µPD78213 µPD78214 µPD78P214 µPD78212 (A) µPD78213 (A) µPD78214 (A) µPD78P214 (A) NEC Corporation 1989 Document No. IEU-1236H (O. D. No.
GENERAL 1 PIN FUNCTIONS 2 CPU FUNCTION 3 CLOCK GENERATOR 4 PORT FUNCTIONS 5 REAL-TIME OUTPUT FUNCTION 6 TIMER/COUNTER UNITS 7 A/D CONVERTER 8 ASYNCHRONOUS SERIAL INTERFACE 9 CLOCK SYNCHRONOUS SERIAL INTERFACE 10 EDGE DETECTION FUNCTION 11 INTERRUPT FUNCTIONS 12 LOCAL BUS INTERFACE FUNCTION 13 STANDBY FUNCTION 14 RESET FUNCTION 15 APPLICATION EXAMPLES 16 PROGRAMMING FOR THE µPD78214 17 INSTRUCTION OPERATIONS 18 78K/II SERIES PRODUCT LIST A DEVELOPMENT TOOLS B SOFTWARE
Cautions on CMOS Devices 1 Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling.
The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
Main Revisions in This Edition Page Description P.55 VSS and "Caution" have been added in (a) of Fig. 4-2. P.329 "Caution" has been added in (2) of Section 12.4.6. P.383 "Caution" has been added in (b) of Section 14.4.2. P.429 Appendix B has been modified as follows: • "IBM PC series" has been changed to "IBM PC/AT." • Upgraded versions of MS-DOS are now supported by some development tools designed for the PC-9800 series. • 3.5" 2HC has been added to as a PC DOS distribution media.
PREFACE Users: This manual is aimed at engineers who need to be familiar with the capabilities of the µPD78214 sub-series for application program development purposes. Purpose: The purpose of this manual is to help users understand the hardware capabilities of the µPD78214 sub-series. Organization: Two manuals are available for the µPD78214 sub-series: The hardware manual (this manual) and instruction manual (common to all 78K/II series products).
µ PD78P214 µ PD78P214(A) PROM 16K RAM 512 µ PD78214 µ PD78214(A) µ PD78213 µ PD78213(A) ROM 16K RAM 512 ROM-less RAM 512 µ PD78212 µ PD78212(A) ROM 8K RAM 384 To check the details of a register when you know the name of the register: See Appendix D. To check the differences between the µPD78214 sub-series and other models of the 78K/II series: First see Appendix A to determine the differences between the models then see Appendix E for details.
Register representation EDC 7 6 5 4 3 2 1 0 B 1 0 × A 1 0 × The encircled bit number indicates that the bit name is used as reserved word by the NEC assembler and defined by the header file, sfrbit.h, by C compiler. Write operation Either 0 or 1 can be written to this bit without affecting the register operation. Register name Read operation 0 or 1 is read from these bits. Write 0 to this bit. Write 1 to this bit.
• Documents related to development tools Document name Document No.
• Other documents Document name Document No. Package Manual IEI-1213 SMD Surface Mount Technology Manual IEI-1207 Quality Grades on NEC Semiconductor Devices IEI-1209 NEC Semiconductor Device Reliability/Quality Control System IEI-1203 Guide to Quality Assurance for Semiconductor Devices MEI-1202 Caution The above documents may be revised without notice. Use the latest versions when you designing an application system.
Contents CONTENTS CHAPTER 1 GENERAL ........................................................................................................................................1 1.1 1.2 FEATURES ............................................................................................................................3 ORDERING INFORMATION AND QUALITY GRADE ........................................................4 1.2.1 Ordering Information ...................................................................
Contents 3.3 CHAPTER 4 CLOCK GENERATOR .....................................................................................................................55 4.1 4.2 CHAPTER 5 NOTES ...................................................................................................................................53 CONFIGURATION AND FUNCTION ...................................................................................55 NOTES .......................................................................
Contents Preface 5.9 CHAPTER 6 REAL-TIME OUTPUT FUNCTION .................................................................................................95 6.1 6.2 6.3 6.4 6.5 6.6 CHAPTER 7 5.8.4 Built-In Pull-Up Resistor ..........................................................................................93 5.8.5 Notes .........................................................................................................................93 NOTES ..................................................
Contents 7.5 ★ CHAPTER 8 A/D CONVERTER ...........................................................................................................................225 8.1 8.2 8.3 8.4 8.5 8.6 CHAPTER 9 CONFIGURATION ................................................................................................................225 A/D CONVERTER MODE REGISTER (ADM) ......................................................................228 OPERATION ...........................................................
Contents 10.4 OPERATIONS IN THE THREE-WIRE SERIAL I/O MODE ..................................................265 10.4.1 Basic Operation Timing ..........................................................................................265 10.4.2 Operation When Only Transmission Is Permitted ...............................................267 10.4.3 Operation When Only Reception Is Permitted .....................................................267 10.4.
Contents 12.3.4 Multiplexed-Interrupt Handling ..............................................................................313 12.3.5 Interrupt Request and Macro Service Pending ....................................................316 12.3.6 Interrupt and Macro Service Operation Timing ..................................................317 12.4 MACRO SERVICE FUNCTION .............................................................................................319 12.4.1 Macro Service Outline ...............
Contents CHAPTER 16 APPLICATION EXAMPLES ............................................................................................................395 16.1 OPEN-LOOP CONTROL OF STEPPER MOTORS ..............................................................395 16.2 SERIAL COMMUNICATION WITH MULTIPLE DEVICES ..................................................397 CHAPTER 17 PROGRAMMING FOR THE µPD78P214 .......................................................................................399 17.1 17.2 17.
Contents LIST OF FIGURES Fig. No. Title, Page 2-1 I/O Circuits Provided for Pins .......................................................................................................34 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 Memory Map of µPD78212 (EA Pin Driven High) .....................................................................38 Memory Map of µPD78212 (EA Pin Driven Low) ......................................................................
Contents Fig. No. Title, Page 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 Connection of Pull-Up Resistors (Port 4) ...................................................................................79 Example of Driving an LED Directly ...........................................................................................79 Block Diagram of Port 5 ..................................................................................................
Contents Fig. No. 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44 7-45 7-46 7-47 7-48 7-49 7-50 7-51 7-52 7-53 7-54 7-55 7-56 7-57 7-58 7-59 7-60 7-61 Title, Page Example of Rewriting Compare Register CR00 .........................................................................124 Example of PWM Output Signal with a 100% Duty Factor ......................................................
Contents Fig. No. 7-62 7-63 7-64 7-65 7-66 7-67 7-68 7-69 7-70 7-71 7-72 7-73 7-74 7-75 7-76 7-77 7-78 7-79 7-80 7-81 7-82 7-83 7-84 7-85 7-86 7-87 7-88 7-89 7-90 7-91 7-92 7-93 7-94 7-95 7-96 7-97 7-98 7-99 7-100 7-101 7-102 7-103 7-104 7-105 Title, Page Timing of Pulse Width Measurement .........................................................................................156 Setting of Control Registers for Pulse Width Measurement ...................................................
Contents Fig. No. 7-106 7-107 7-108 7-109 7-110 7-111 7-112 7-113 7-114 7-115 7-116 7-117 7-118 7-119 7-120 7-121 7-122 7-123 7-124 7-125 7-126 7-127 7-128 7-129 7-130 7-131 7-132 7-133 7-134 7-135 7-136 7-137 7-138 7-139 Title, Page 7-141 Interrupt Request Handling for Pulse Width Calculation .........................................................197 Example of PWM Signal Output by 8-Bit Timer/Counter 2 .....................................................
Contents Fig. No. Title, Page 8-9 8-10 8-11 8-12 8-13 8-14 Software-Started Scan-Mode A/D Conversion ..........................................................................235 Example of Malfunction in a Hardware-Started A/D Conversion ...........................................236 Select-Mode A/D Conversion Started by Hardware .................................................................237 Scan-Mode A/D Conversion Started by Hardware .............................................................
Contents Fig. No. Title, Page 11-1 11-2 11-3 11-4 11-5 11-6 Format of External Interrupt Mode Register 0 (INTM0) ...........................................................294 Format of External Interrupt Mode Register 1 (INTM1) ...........................................................295 Edge Detection on Pin P20 ...........................................................................................................296 Edge Detection on Pins P21 to P26 .............................................
Contents Fig. No. Title, Page 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 13-24 13-25 13-26 13-27 Format of the Memory Expansion Mode Register (MM) .........................................................346 Format of Programmable Wait Control Register (PW) .............................................................347 Read Timing .......................................................................................
Contents Fig. No. 17-1 17-2 17-3 Title, Page Timing Chart for PROM Write and Verify .................................................................................. 400 Write Operation Flowchart ...........................................................................................................401 PROM Read Timing Chart ............................................................................................................
Contents LIST OF TABLES Table No. Title, Page 2-1 2-2 2-3 2-4 Port 2 Port 3 Port 6 Types Functions .............................................................................................................................27 Operating Mode .................................................................................................................29 Operating Mode .................................................................................................................
Contents Table No. Title, Page 8-1 8-2 8-3 Modes Generating the INTAD......................................................................................................225 A/D Conversion Time ....................................................................................................................232 Conditions to Generate Interrupt Requests in Each A/D Converter Operating Mode .........239 9-1 9-2 9-3 9-4 9-5 Causes of Reception Errors ....................................................
CHAPTER 1 GENERAL The µPD78214 sub-series is part of the 78K/II series of eight-bit single-chip microcomputers capable of accessing an expanded memory space of 1 megabyte. This sub-series consists of the following products. The µPD78214 offers a 16-KB masked ROM, 512-byte RAM, highly functional timers/counters, a high-precision A/ D converter, and two independent serial interfaces. The µPD78212 is the same as the µPD78214 except that it offers an 8-KB ROM and 384-byte RAM.
2 µPD78224 sub-series The A /D converter is contained. The timer/counter and baud rated generator function are enhanced. The comparator is deleted. The following are contained: A/D converter D/A converter The PWM output function is added. The macro service and timer/ counter are enhanced. The comparator is deleted. µPD78P214 µ PD78P214(A) µ PD78214 µ PD78214(A) µ PD78213 µPD78213(A) µ PD78212 µ PD78212(A) µPD78214 sub-series The D/A converter is contained. The PWM output function is added.
Chapter 1 General 1.
µPD78214 Sub-Series 1.2 ORDERING INFORMATION AND QUALITY GRADE 1.2.
Chapter 1 General 1.2.
µPD78214 Sub-Series 1.3 PIN CONFIGURATION (TOP VIEW) 1.3.
Chapter 1 General VDD VDD P25/INTP4/ASCK AV SS P26/INTP5 AV REF 5 4 3 2 1 68 67 66 65 64 63 62 61 P30/RXD P75/AN5 6 P27/SI P74/AN4 7 P31/TXD P73/AN3 8 P32/SCK P72/AN2 9 EA P71/AN1 P33/SO/SB0 (2) 68-pin plastic QFJ 1 P70/AN0 10 60 P24/INTP3 P34/TO0 11 59 P23/INTP2/CI P35/TO1 12 58 P22/INTP1 P36/TO2 13 57 P21/INTP0 P37/TO3 14 56 P20/NMI P00 15 55 ASTB P01 16 54 P40/AD0 P02 17 53 P41/AD1 P03 18 P04 19 P05 P06 µ PD78213L µ PD78214L-××× µ PD78214L
µPD78214 Sub-Series P70/AN0 P34/TO0 P35/TO1 P36/TO2 P37/TO3 P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/AN7 P66/WAIT/AN6 P65/WR (3) 64-pin plastic QFP (14 × 14 mm) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 P71/AN1 P63/A19 2 47 P72/AN2 P62/A18 3 46 P73/AN3 P61/A17 4 45 P74/AN4 P60/A16 5 44 P75/AN5 RESET 6 43 AV REF X2 7 42 AV SS X1 8 41 VDD VSS 9 40 EA 39 P33/SO/SB0 38 P32/SCK 37 P31/TXD µ PD78212GC-×××-AB8 µ PD78212GC(A)-×××-AB8 µ PD78213GC
Chapter 1 General P64/RD P63/A19 P62/A18 P61/A17 P60/A16 NC RESET X2 X1 VSS VSS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 (4) 74-pin plastic QFP (20 × 20 mm) 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 P65/WR 1 55 P66/WAIT/AN6 P47/AD7 2 54 P67/REFRQ/AN7 P46/AD6 3 53 P07 P45/AD5 4 52 NC P44/AD4 5 51 P06 P43/AD3 6 50 P05 P42/AD2 7 49 P04 VSS 8 48 P03 VSS 9 47 NC 46 P02 45 P01 44 P00 43 P37/TO3 P41/AD1 10 P40/AD0 11 A
µPD78214 Sub-Series P00-P07 : Port 0 P20-P27 : Port 2 P30-P37 : Port 3 P40-P47 : Port 4 P50-P57 : Port 5 P60-P67 : Port 6 P70-P75 : Port 7 TO0-TO3 : Timer output CI : Clock input RxD : Receive data TxD : Transmit data SCK : Serial clock ASCK : Asynchronous serial clock SBO : Serial bus SI : Serial input SO : Serial output NMI : Non-maskable interrupt INTP0-INTP5 : Interrupt from peripherals AD0-AD7 : Address/data bus A8-A19 : Address bus RD : Read strobe WR : Write
Chapter 1 General 1.3.2 PROM Programming Mode (P20/NMI = 12.
µPD78214 Sub-Series 8 7 6 5 4 3 (G) (Open) (L) 2 1 68 67 66 65 64 63 62 61 VPP VDD 9 VDD (L) (2) 68-pin plastic QFJ 10 60 11 59 12 58 13 57 A9 14 56 P20/NMI A0 15 55 (Open) A1 16 54 D0 A2 17 53 D1 A3 18 52 VSS A4 19 51 VSS A5 20 50 D2 A6 21 49 D3 A7 22 48 D4 NC 23 47 D5 24 46 D6 25 45 D7 26 44 A8 (L) (Open) (L) CE µ PD78P214L µ PD78P214L-××× (G) ★ (L) A10 A11 A12 A13 A14 VSS A15 (G) VSS (Open) RESET (L) OE 27 28 2
Chapter 1 General 1 (L) A0 A1 A2 A3 A4 A5 A6 A7 CE (L) (Open) (3) 64-pin plastic QFP (14 × 14 mm) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 RESET 6 43 (Open) 7 (G) 8 (L) µ PD78P214GC-AB8 µ PD78P214GC-×××-AB8 µ PD78P214GC(A)-AB8 1 OE (L) 42 41 VDD 40 VPP VSS 9 A15 10 A14 11 A13 12 A12 13 36 A11 14 35 A10 15 34 (L) 16 33 39 38 37 (L) (Open) (G) (G) A9 P20/NMI D0 (Open) D1 VSS D2 D3 D4 D5 D6 A8 D7 17 18 19
µPD78214 Sub-Series OE (L) NC RESET (Open) (G) VSS VSS (G) A14 A13 A12 A11 A10 (L) (4) 74-pin plastic QFP (20 × 20 mm) 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 CE 1 55 D7 2 54 D6 3 53 A7 D5 4 52 (Open) D4 5 51 A6 D3 6 50 A5 D2 7 49 A4 VSS 8 48 A3 IC 9 47 NC D1 10 46 A2 D0 11 45 A1 (Open) 12 44 A0 NC 13 43 P20/NMI 14 42 A9 15 41 16 40 NC 17 39 (Open) 18 38 (L) (G) µ PD78P214GJ-5BJ µ PD78P214GJ-×××-5BJ A8 (L)
Chapter 1 General VPP : Programming power supply RESET : Reset D0-D7 : Data bus 1 A0-A14 : Address bus VSS : Ground OE : Output enable VDD : Power supply CE : Chip enable P20/NMI : Port 2/non-maskable interrupt NC : Non-connection 15
16 SCK SO Shift register RESET AN2-AN7 AN1 Motor supply voltage SW input for each mode AN0 AVSS AVREF Ports Temperature sensor RS-232C driver TO Print head driver TXD RXD P04-P07 P00-P03 X1 X2 VSS VDD A8-A15 ASTB AD0-AD7 REFRQ WR RD A16-A19 µ PD78214 M Paper feed motor M Carriage motor Stepping motor Latch Decoder PROM µ PD27C256A Gate array I/O expansion Centronics interface, etc.
Clocked serial interface Timer/counter (16 bits) Timer/counter channel-1(PS+8 bits) Timer/counter channel-2 (PS+8 bits) SCK SO/SB0 SI INTP3 TO0 TO1 INTP0 INTP1 INTP2 TO2 TO3 A/D converter Real-time output port (4 bits×2) Bus interface P2 SFR address/data bus P4 P5 P6 P7 Note 4 Note 4 Note 4 P30 P40 P50 P60 P64 P70 -P37 -P47 -P57 -P63 -P67 -P75 P3 Data bus (8) P00 P20 -P07 -P27 P0 Port Data bus • RAM (256 bytes)Note 2 • GR • Macro service channel Boolean processpr SP PSW Temporary
µPD78214 Sub-Series 1.
Chapter 1 General Item µPD78212 µPD78214 µPD78P214 µPD78213 A/D converter Eight channels, each having a resolution of eight bits Interrupt • 19 interrupts (seven external and 12 internal) plus those caused by BRK instructions 1 • Two programmable priority levels • Two types of interrupt handling, vectored interrupt and macro service Instruction set • 16-bit calculation • Multiplication (8 bits by 8 bits) and division (16 bits by 8 bits) • Bit manipulation • BCD conversion • Others Package • 64
µPD78214 Sub-Series 1.7 DIFFERENCES BETWEEN THE µPD78210Note AND µPD78213 Note For maintenance purposes only.
Chapter 1 General 1.8 DIFFERENCES BETWEEN THE µPD78214 SUB-SERIES AND µPD78218A SUB-SERIES µPD78214 Sub-Series Series name Minimum instruction cycle (when operating at 12 MHz) 333 ns 500 ns 333 ns Operating voltage range ROM RAM Number of I/O pins Execution time (number of clocks) required for PUSH PSW instruction 500 ns 333 ns VDD = +5 V ±0.
µPD78214 Sub-Series 1.9 DIFFERENCES BETWEEN THE µPD78212 AND µPD78212(A) Product µPD78212 Item µPD78212(A) Quality grade Standard Special Package • 64-pin plastoc shrink DIP • 64-pin plastoc shrink DIP • 64-pin plastic QFP • 64-pin plastic QFP • 74-pin plastic QFP 1.
Chapter 1 General 1.12 DIFFERENCES BETWEEN THE µPD78212, µPD78213, µPD78214, AND µPD78P214 1.12.
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CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTION LIST 2.1.1 Normal Operating mode 2 (1) Ports Pin P00-P07 Input/Output Pin name for secondary function Function Output — Port 0 (P0): Can be used as two four-bit, real-time output ports. Can drive transistors directly.
µPD78214 Sub-Series (2) Pins other than those which function as ports Pin TO0-TO3 Function Input/output Output P34-P37 Timer output CI Input Count clock supplied to eight-bit timer/counter unit 2 RxD Input Serial data input (UART) P30 TxD Output Serial data output (UART) P31 ASCK SB0 P23/INTP2 Input Baud rate clock input (UART) P25/INTP4 Input/output Serial data input/output (SB2) P33/SO SI Input SO Output SCK Input/output Serial data input (three-wire serial I/O) Serial data
Chapter 2 Pin Functions 2.1.2 PROM Programming Mode (only for the µPD78P214, P20/NMI = 12.5 V, RESET = L) Pin Input/output Function P20/NMI Setting PROM programming mode RESET 2 Input A0-A14 Address bus Input/output D0-D7 CE Data bus PROM enable input Input OE Read strobe to PROM VPP Power for programming VDD Main power — VSS Ground — NC 2.2 PIN FUNCTIONS 2.2.
µPD78214 Sub-Series (a) When functioning as a port Signals applied to these pins can be read and these pins can be tested, regardless of whether these pins are acting as secondary function pins. (b) When functioning as control-signal input pins (i) NMI (non-maskable interrupt) Apply an external non-maskable interrupt request signal to this pin. The external interrupt mode register (IMTM0) specifies whether an interrupt is detected at its rising or falling edge.
Chapter 2 Pin Functions Table 2-2 Port 3 Operating Mode (n = 0 to 7) Mode Port mode Control signal I/O mode PMC3 setting PMC3n = 0 PMC3n = 1 P30 RxD input P31 TxD output P32 SCK input/output P33 2 SO output/SB0 input/output I/O port P34 TO0 output P35 TO1 output P36 TO2 output P37 TO3 output (a) Port mode Pins for which port mode is specified by the PMC3 can be used independently as input or output pins by specifying the port-3 mode register (PM3).
µPD78214 Sub-Series (6) P60 to P67 (port 6): Output (P60 to P63) and tristate inputs/outputs (P64 to P67) Port 6 is an eight-bit I/O port with output latches. Pins P64 to P67 are provided with software-programmable pull-up resistors. The pins of port 6 also function as control signal input pins, as listed in Table 2-3. To use these pins as control signal input pins, set up is required. In the case of the µPD78213, P64 and P65 act as an RD output and WR output, respectively.
Chapter 2 Pin Functions (8) ASTB (address strobe): Output Timing signal output used for latching addresses externally to enable access to external memory. (9) EA (external access): Input Control signal input used for switching the program memory from the internal ROM to the external memory. When this signal is high, the internal ROM is accessed. When low, the external memory is accessed in ROMless mode. In the case of the µPD78212, µPD78214, and µPD78P214, always apply a high-level signal to this pin.
µPD78214 Sub-Series (9) VSS Ground. (10) NC (non-connection) Not connected inside the chip.
Chapter 2 Pin Functions 2.3 I/O CIRCUITS AND UNUSED-PIN HANDLING Table 2-4 lists the types of I/O circuits provided for each pin and describes how pins are handled when not used. Fig. 2-1 illustrates the I/O circuit types. Table 2-4 Types of I/O Circuits and Unused-Pin Handling Pin P00-P07 P20/NMI Type of I/O circuit Input/output 4 Output 2 2 Recommended unused-pin handling Leave open. Connect to VDD or V SS. P21/INTP0 P22/INTP1 P23/INTP2/CI Input P24/INTP3 2-A Connect to VDD.
µPD78214 Sub-Series Fig. 2-1 I/O Circuits Provided for Pins Type 1 Type 2-A VDD VDD P IN Pull-up enable P N IN Type 2 IN Schmitt trigger input with hysteresis characteristics Type 5-A VDD Schmitt trigger input with hysteresis characteristics Type 4 Pull-up enable VDD Data P VDD P Data OUT Output disable P IN/OUT Output disable N N Input enable Push-pull output which can output high impedance (both the positive and negative channels are off.
Chapter 2 Pin Functions 2.4 NOTES (1) While the RESET signal is being applied, pins P60 to P63 are high impedance. When the RESET signal is released, the output of these pins is low level. Design the peripheral circuit so that it operates satisfactorily when pins P60 to P63 initially output the low level. (2) When an I/O pin is used as both an input and output pin, connect the pin to the VDD pin through a resistor of less than 100 kilohms.
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CHAPTER 3 CPU FUNCTION 3.1 MEMORY SPACE The µPD78214 can access a memory space of up to 1M byte. Figs. 3-1 to 3-4 show the corresponding memory maps. The mapping of program memory depends on the status of the EA pin. The EA pin of the µPD78213 must be tied low. (1) µPD78212 Program memory is mapped to the internal ROM (8K bytes: 00000H to 01FFFH) and external memory (56704 bytes: 02000H to 0FD7FH). External memory is accessed in external memory expansion mode.
µPD78214 Sub-Series Fig. 3-1 Memory Map of µPD78212 (EA Pin Driven High) Data memory Expansion address FFFFFH External memoryNote 1 (960K bytes) Data memory General registers (32 bytes) Macro service control words (30 bytes) 0FEC2H Data area (512 bytes) 0FD80H Program memory/ data memory 01FFFH External memory (56704 bytes) Program area (4K bytes) 01000H 00FFFH CALLF entry area (2K bytes) 00800H 007FFH 02000H 01FFFH Internal ROM (8K bytes) 00000H Notes 1. Accessed in 1M-byte expansion mode. 2.
Chapter 3 CPU Function Fig.
µPD78214 Sub-Series Fig. 3-3 Memory Map of µPD78213, µPD78214, or µPD78P214 (EA Pin Driven Low) Data memory Expansion address FFFFFH External memoryNote 1 (960K bytes) Data memory 0FEFFH 0FEE0H 0FEDFH 0FD00H 0FCFFH Macro service control words (30 bytes) Data area (512 bytes) 0FD00H External memory (64768 bytes) 00FFFH CALLF entry area (2K bytes) 00800H 007FFH 00080H 0007FH 00040H 0003FH 00000H Notes 1. Accessed in 1M-byte expansion mode. 2.
Chapter 3 CPU Function Fig.
µPD78214 Sub-Series 3.1.1 Internal Program Memory Area In the area from 00000H to 03FFFH (00000H to 01FFFH for the µPD78212), a 16K × 8 bit ROM (8K × 8 bit ROM for the µPD78212) is incorporated. Programs and table data are stored in this area. Usually, the program counter (PC) is used for addressing. If the µPD78213 is used or if the EA pin is driven low, this area becomes external memory (ROM-less operation). (1) Vector table area The 64-byte area from 00000H to 0003FH is reserved as a vector table area.
Chapter 3 CPU Function 3.1.2 Internal RAM Area A 512-byte (384-byte for the µPD78212) general-purpose static RAM is incorporated into the area from 0FD00H to 0FEFFH. This area consists of the following two RAMs: Peripheral RAM (PRAM) : 0FD00H to 0FDFFH (0FD80H to 0FDFFH for the µPD78212) ° Internal RAM (IRAM): 0FE00H to 0FEFFH °The internaldual-port dual-port RAM (IRAM) can be accessed at high speed. 3 Short direct addressing mode for high-speed access can be used for the area from 0FE20H to 0FEFFH.
µPD78214 Sub-Series To access the space, specify the bank to be used (high-order four bits of address, A16 to A19) in the bank register (P60 to P63 of register P6, or PM60 to PM63 of register PM6). Then, execute an instruction which allows extended addressing. The high-order four bits of address output from pins P60 to P63 are valid only while an instruction that allows extended addressing is being executed. Because two bank registers are provided, two data banks can always be used.
Chapter 3 CPU Function 3.2 REGISTERS 3.2.1 Program Counter (PC) This 16-bit binary counter holds the address of the program to be executed next (see Fig. 3-6). Usually, the address is automatically incremented according to the number of bytes of the instruction to be fetched. If an instruction causing a branch is executed, the contents of the register or immediate data are set.
µPD78214 Sub-Series (3) Register bank selection flags (RBS0, RBS1) These two flags are used to select one of four register banks (see Table 3-2). The flags hold two-bit information indicating the register bank selected by the SEL RBn instruction.
Chapter 3 CPU Function Fig. 3-9 Data Saved to the Stack Area PUSH rp instruction Stack SP ← SP – 2 SP – 2 ↑ SP – 1 ↑ SP ⇒ Register pair, low Register pair, high CALL, CALLF, and CALLT instructions Stack SP ← SP – 2 SP ← SP – 3 SP – 2 ↑ SP – 1 ↑ SP ⇒ PC7-PC0 PC15-PC8 SP – 3 ↑ SP – 2 ↑ SP – 1 ↑ SP ⇒ Interrupt Stack PC7-PC0 PC15-PC8 3 PSW Fig.
µPD78214 Sub-Series Fig.
Chapter 3 CPU Function (2) Function General-purpose registers can be operated in units of eight bits. They can also be operated in units of 16 bits, that is, a pair of eight-bit registers can be operated as a single unit (AX, BC, DE, HL). Each register can temporarily hold operation results or can be used as an operand of an arithmetic/logical instruction between registers. General-purpose registers are grouped into four register banks.
µPD78214 Sub-Series 3.2.5 Special Function Registers (SFR) A mode register, control register, and other registers with special functions, which are built-in hardware peripherals, are mapped into the 256-byte space from 0FF00H to 0FFFFH. Caution Never access an address to which no SFR is mapped in this area. If this is attempted, the µPD78214 may enter a deadlock. To clear the deadlock, a reset signal must be input to the device. Table 3-4 lists the special function registers (SFR).
Chapter 3 CPU Function Table 3-4 Special Function Registers (SFR) (1/2) Bit unit Address Name of special function register (SFR) Symbol R/W At reset 1 bit 0FF00H Port 0 P0 R/W 0FF02H Port 2 P2 R 0FF03H Port 3 P3 0FF04H Port 4 P4 0FF05H Port 5 P5 0FF06H Port 6 P6 0FF07H Port 7 P7 0FF0AH Port 0 buffer register Port 0 buffer register 0FF0CH Real-time output port control register RTPC 0FF10H 16-bit compare register 0 (16-bit timer/counter) CR00 16-bit compare register 1 (16-
µPD78214 Sub-Series Table 3-4 Special Function Registers (SFR) (2/2) Bit unit Address Name of special function register (SFR) Symbol R/W At reset 1 bit 8 bits 16 bits 0FF50H 16-bit timer register 0 0FF51H — — — — ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° 0FF52H 8-bit timer register 1 TM1 0FF54H 8-bit timer register 2 TM2 — 0FF56H 8-bit timer register 3 TM3 — 0FF5CH Prescaler mode register 0 PRM0 W — 0FF5DH Timer control
Chapter 3 CPU Function 3.3 NOTES (1) A program fetch from the internal RAM area is prohibited. (2) Operation of the stack pointer In stack addressing, the entire 64K bytes can be accessed. No stack area can be mapped into the SFR area or internal ROM area. (3) Special function register (SFR) 3 Never access an address to which no SFR is mapped in the area from 0FF00H to 0FFFFH. If this is attempted, the µPD78214 may enter a deadlock. To clear the deadlock, a reset signal must be input to the device.
54
CHAPTER 4 CLOCK GENERATOR 4.1 CONFIGURATION AND FUNCTION A clock generator generates and controls the internal system clock (CLK) sent to the CPU. Fig. 4-1 shows the configuration of the clock generator. Fig.
µPD78214 Sub-Series Remark Different uses of the crystal and ceramic resonator Generally, a crystal’s oscillation frequency is quite stable. Crystals are ideal for high-precision time management (for example, clock or frequency measurement). In comparison with crystals, ceramic resonators are less stable but offer three advantages: a shorter oscillation start time, smaller dimensions, and lower price.
Chapter 4 Clock Generator Fig. 4-4 Notes on Connection of the Oscillator µ PD78214 X2 X1 VSS 4 Cautions 1. Place the oscillator as close as possible to pins X1 and X2. 2. Do not let other signal lines cross the circuit enclosed in a dashed line. Fig. 4-5 Incorrect Oscillator Connections (a) The wiring length of the external circuit is too long. (b) A signal line is allowed to cross the oscillator.
µPD78214 Sub-Series (c) A varying high current flows too close to the signal line. (d) A current flows through the ground line of the oscillator. (The potentials vary at points A, B, and C.) VDD µ PD78214 µ PD78214 X2 X1 VSS Pnm X2 X1 VSS High current A B C High current (e) A signal is being drawn from the oscillator. µ PD78214 X2 X1 VSS (2) At power-on or return from STOP mode, some time is required for the oscillation to settle.
CHAPTER 5 PORT FUNCTIONS 5.1 DIGITAL I/O PORTS The µPD78214 has the ports shown in Fig. 5-1. These ports can be used for various types of control. Table 5-1 lists the function of each port. For ports 2 through 6, software can specify whether to use a built-in pull-up resistor for inputs. Fig.
µPD78214 Sub-Series Table 5-1 Port Functions Name Port 0 Pin name P00-P07 Function Software-specified pull-up resistor Can be specified for either output in 8-bit units or high impedance. Can also function as 4-bit real-time output port (P00-P03 and P04-P07). Can drive transistors directly. — Port 2 P20-P27 Input port In 6-bit units (P22-P27) Port 3 P30-P37 Can be specified for either input or output in bit units.
Chapter 5 Port Functions 5.2.1 Hardware Configuration Fig. 5-2 shows the hardware configuration of port 0. Fig. 5-2 Configuration of Port 0 WRRTPC Real-time output port control register P0LM (P0HM) RDRTPC WRPM0 5 Port 0 mode register Internal bus PM0n (PM0m) WRP0L Trigger Buffer register P0Ln (P0Hm) RDP0L Output latch Selector P0n (P0m) WROUT P0n (P0m) n = 0, 1, 2, 3 m = 4, 5, 6, 7 RDIN 5.2.
µPD78214 Sub-Series 5.2.3 Operation Port 0 is an output-only port. Once port 0 is put in the output mode, the output latch becomes operable, enabling data transfer between the output latch and accumulator according to a transfer instruction. The output latch can be loaded with any data by a logical operation instruction. Once the output latch is loaded with some data, it retains the data until it is loaded with other data.
Chapter 5 Port Functions 5.3 PORT 2 Port 2 is an 8-bit input-only port. P22 through P27 have a software-programmable built-in pull-up resistor. In addition to functioning as an input port, port 2 functions as a control signal input pin such as for external interrupts (see Table 5-3). All the 8 input pins of port 2 are configured as Schmitt trigger circuits in order to prevent malfunction due to noise.
µPD78214 Sub-Series 5.3.1 Hardware Configuration Fig. 5-6 shows the configuration of port 2 Fig. 5-6 Block Diagram of Port 2 VDD WRPUO Pull-up resistor option register PUO2 RDPUO Noise eliminator Interrupt and control signals P2n n = 0, 1, 2, ···, 6 Edge detector RDP27 Noise eliminator Internal bus RDP2n P27 SI input 3-wire serial I/O mode Note P20 or P21 does not have a circuit enclosed in a dotted box. 5.3.2 Setting the Input Mode and Control Mode Port 2 is an input-only port.
Chapter 5 Port Functions Fig. 5-7 Port Specified as an Input Port Noise eliminator Internal bus RDIN P2n n = 0 to 7 5 Caution For the in-circuit emulator, the level of each port 2 pin from which noise has not been removed can be read and tested. 5.3.4 Built-In Pull-Up Resistor P22 through P27 have built-in pull-up resistors. When they must be pulled up, the built-in pull-up resistors should be used.
µPD78214 Sub-Series Fig. 5-9 Connection of Pull-Up Resistors (Port 2) VDD P22 Input buffer Internal bus P23 P24 P25 P26 P27 PUO2 Pull-up resistor option register (PUO) Caution P22 through P26 are not pulled up immediately after a reset. In this case, INTP1 through INTP5 (one of the multiple functions assigned to P22 to P26) may set interrupt request flags. To avoid this problem, specify use of the pull-up resistors in the initialization routine, before clearing the interrupt flags. 5.
Chapter 5 Port Functions Table 5-4 Port 3 Operating Modes (n = 0 through 7) Mode Condition Port mode Control signal I/O mode PMC3n = 0 PMC3n = 1 P30 RxD input P31 TxD output P32 SCK I/O P33 I/O port SO output or SB0 I/O P34 TO0 output P35 TO1 output P36 TO2 output P37 TO3 output 5 (a) Port mode If a port is put in a port mode by the PMC3 register, the port mode register (PM3) can put each bit of the port in either the input or output mode independently of the other bits.
µPD78214 Sub-Series 5.4.1 Hardware Configuration Fig. 5-10 through 5-13 show the configuration of port 3. Fig.
Chapter 5 Port Functions Fig.
µPD78214 Sub-Series ★ Fig.
Chapter 5 Port Functions ★ Fig. 5-13 Block Diagram of P33 (Port 3) WRPUO Pull-up resistor option register PUO3 RDPUO WRPM33 Port 3 mode register 5 PM33 WRPMC33 Output disable PMC33 RDPMC33 VDD SB0 output WRP33 Output latch SO output Selector Internal bus PMC33 P33 P33 SBI mode Output disable RDOUT SB0 input PMC33 RDIN 5.4.
µPD78214 Sub-Series Fig. 5-14 Port 3 Mode Register Format 7 PM3 6 5 4 3 2 1 0 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM3n (FFH when RESET is input) Specifies I/O mode of pin PM3n (n = 0 to 7) 0 Output mode (output buffer ON) 1 Input mode (output buffer OFF) Fig.
Chapter 5 Port Functions 5.4.3 Operation Port 3 is an I/O port. Its pins also function as control signal pins. (1) Output port When port 3 is in the output mode, its output latch is operable. Once the output latch becomes operable, data can be transferred between the output latch and the accumulator using a transfer instruction. The output latch can be loaded with any data by a logical operation instruction.
µPD78214 Sub-Series (3) Control signal input or output Regardless of setting of the port mode 3 register (PM3), each bit of port 3 can be used to input or output a control signal, independently of the other bits, by setting the corresponding bit of the port mode control register (PMC3) to 1. When a pin is used for a control signal, executing a read instruction for the port can detect the state of the control signal. Fig.
Chapter 5 Port Functions Fig. 5-20 Connection of Pull-Up Resistors (Port 3) VDD P30 Input buffer 5 P32 ••• ••• ••• Internal bus P31 P36 P37 ••• (PUO) PUO3 Port 3 mode register (PM3) 5.5 PORT 4 Port 4 is an 8-bit I/O port with an output latch. The memory expansion mode register (MM) can put all 8 bits of this port in either the input or output mode at one time. Each pin has a software-programmable built-in pull-up resistor, and can drive an LED directly.
µPD78214 Sub-Series 5.5.1 Hardware Configuration Fig. 5-21 shows the hardware configuration of port 4. Fig. 5-21 Block Diagram of Port 4 WRPUO Pull-up resistor option register PUO4 RDPUO WRP4n VDD Output latch P4n I/O control circuit RDP4n Internal address bus Internal data bus MM0-MM2 EA P4n n = 0 to 7 5.5.2 Setting the I/O Mode and Control Mode The memory expansion mode register (MM, see Fig 13-1) specifies the operating mode of port 4, as listed in Table 5-5.
Chapter 5 Port Functions 5.5.3 Operation Port 4 is an I/O port. It functions also as an address/data bus (AD0 through AD7). (1) Output port When port 4 is in the output mode, its output latch is operable. Once the output latch becomes operable, data can be transferred between the output latch and the accumulator using a transfer instruction. The output latch can be loaded with any data by a logical operation instruction.
µPD78214 Sub-Series (3) Address/data bus (AD0 through AD7) Port 4 is used as the address/data automatically for external access. Do not execute I/O instructions for port 4. 5.5.4 Built-In Pull-Up Resistor Port 4 has built-in pull-up resistors. When port 4 must be pulled up, the built-in pull-up resistors should be used. Use of the built-in pull-up resistors can reduce the number of the required components and the required installation space.
Chapter 5 Port Functions Fig. 5-25 Connection of Pull-Up Resistors (Port 4) VDD P40 Input buffer 5 P42 ••• ••• ••• ••• Internal bus P41 P46 P47 PUO4 Pull-up resistor option register (PUO) 5.5.5 Driving LEDs Directly For port 4, the low level side of the output buffer has an enhanced driving capacity so that it can drive an LED directly on an active-low signal. Fig. 5-26 is an example of such an output buffer. Fig.
µPD78214 Sub-Series 5.6 PORT 5 Port 5 is an 8-bit I/O port with an output latch. The port 5 mode register (PM5) can put each bit of this port in either the input or output mode, independently of the other bits. Each pin has a software-programmable built-in pullup resistor, and can drive an LED directly. When an external memory or I/O device is expanded, P50 through P57 function as an address bus (AD8 through AD15). For the µPD78213, P50 through P57 function only as an address bus (AD8 through AD15).
Chapter 5 Port Functions Fig.
µPD78214 Sub-Series Fig. 5-30 Port Specified as an Input Port WRPORT Internal bus Output Iatch P5n n = 0 to 7 RDIN Caution Although its ultimate purpose is to manipulate only 1 bit, a bit manipulation instruction accesses a port in 8-bit units.
Chapter 5 Port Functions Fig. 5-32 Connection of Pull-Up Resistors (Port 5) VDD P50 Input buffer 5 P52 ••• ••• ••• Internal bus P51 P56 P57 ••• (PUO) PUO5 Port 5 mode register (PM5) 5.6.5 Driving LEDs Directly For port 5, the low level side of the output buffer has an enhanced driving capacity so that it can drive an LED directly on an active-low signal. Fig. 5-33 is an example of such an output buffer. Fig.
µPD78214 Sub-Series 5.7 PORT 6 Port 6 is an 8-bit I/O port with an output latch. P64 through P67 have a software-programmable built-in pull-up resistor. In addition to the port functions, port 5 works as I/O pins for various control signals as listed in Table 5-7. Each control pin is operated by the corresponding function. For the µPD78213, P64 and P65 function only as RD and WR output pins, respectively.
Chapter 5 Port Functions (vi) AN6 and AN7 (analog input) These pins receive analog signals for the A/D converter. 5.7.1 Hardware Configuration Fig. 5-34 through 5-37 show the hardware configuration of port 6. Fig.
µPD78214 Sub-Series Fig.
Chapter 5 Port Functions Fig.
µPD78214 Sub-Series Fig. 5-37 Block Diagram of P67 (Port 6) WRPUO Pull-up resistor option register PUO6 RDPUO VDD WRPM67 Port 6 mode register PM67 Refresh signal WRP67 Selector Internal bus Refresh mode Output latch P67 P67 RDOUT RDIN A/D converter 5.7.2 Setting the I/O Mode and Control Mode The port 6 mode register (PM6) can put port 6 in either the input or output mode as shown in Fig. 5-38. Table 58 lists the operations needed to make port 6 function as control pins.
Chapter 5 Port Functions Cautions 1. To use P60 through P63 as an output port, it is necessary to reset the PM60 through PM63 bits to 0. If they are not 0, the incircuit emulator may not work. 2. To use the P66/WAIT pin as the WAIT pin, it is necessary to put P66 in the input mode using the PM6 register. Fig.
µPD78214 Sub-Series 5.7.3 Operation Port 6 is an I/O port. Its pins also function as control signal pins. (1) Output port When port 6 is in the output mode, the contents of its output latch are output, and data can be transferred between the output latch and the accumulator using a transfer instruction. The output latch can be loaded with any data by a logical operation instruction. Once the output latch is loaded with some data, it retains the data until it is loadedNote with other data.
Chapter 5 Port Functions (3) Control pins When port 6 function as control pins, they cannot be manipulated or tested by software. (4) Analog inputs (P66 and P67 only) When port 6 is used as analog input pins (AN6 and AN7), the level of each pin can be read and tested. 5.7.4 Built-In Pull-Up Resistor P64 through P67 have built-in pull-up resistors. When they must be pulled up, the built-in pull-up resistors should be used.
µPD78214 Sub-Series 5.7.5 Note When P66 and P67 are used as analog input pins AN6 and AN7 respectively or when A/D conversion is not performed, do not apply a voltage out of the range AVSS through AVREF to these pins, if AN6 and AN7 are selected for ANI0 through ANI2 of the A/D converter mode register (ADM). See Chapter 8 for details. 5.8 PORT 7 Port 7 is a 6-bit input-only port. It functions as A/D converter analog input pins (AN0 through AN5) as well as input port pins.
Chapter 5 Port Functions 5.8.3 Operation Port 7 is an input-only port, and the level of its pins can be read and tested. Internal bus Fig. 5-44 Port Specified as an Input Port RDIN 5 P7n n = 0 to 5 5.8.4 Built-In Pull-Up Resistor Port 0 has no built-in pull-up resistor. 5.8.
µPD78214 Sub-Series (4) P22 through P26 are not pulled up immediately after a reset, and the interrupt request flag may be set depending on the function of a dual-function pin (INTP1 through INTP5). Therefore, specify connection of a pull-up resistor in the initialization routine, before clearing the interrupt request flag. (5) With an in-circuit emulator, the level of each pin of port 2 can be read and tested before noise is removed.
CHAPTER 6 REAL-TIME OUTPUT FUNCTION 6.1 CONFIGURATION AND FUNCTION The real-time output function is implemented by the hardware centering around port 0 and the buffer register (P0H and P0L) as shown in Fig. 6-1. The term real-time output function refers to a function that transfers data in the buffer register to the output latch by hardware for output to the outside simultaneously when a timer interrupt or external interrupt occurs.
96 RTPC INTP0 INTC10 INTC11 Selector EXTR BYTE P0MH EXTR P0ML P0ML P0MH BYTE Selector 4 4 P03 P02 P01 P00 Output latch P0 4 P0L Buffer register P0H 4 P07 P06 P05 P04 8-bit real-time output (P0) 4-bit real-time output (P0L) 4-bit real-time output (P0H) Internal bus Fig.
Chapter 6 Real-Time Output Function 6.2 REAL-TIME OUTPUT CONTROL REGISTER (RTPC) The real-time output control register (RTPC) is an 8-bit register to specify the functions of port 0. An 8-bit manipulation instruction and a bit manipulation instruction can be used to read data from and write data to the RTPC register. Fig. 6-2 shows the format of this register. When the RESET signal is input, the RTPC is reset to 00H. Fig.
µPD78214 Sub-Series Table 6-1 Port 0 Operating Modes and Operations Needed for the Port 0 Buffer Registers Read operation Operating mode 8-bit port mode High-order 4 bits P0 4-bit separate real-time output port mode Low-order 4 bits High-order 4 bits Output latch Low-order 4 bits Output latch Buffer registerNote — Buffer register P0H Buffer registerNote Buffer register — P0 Output latch P0L 8-bit real-time output port mode Write operation Register — Buffer registerNote Buffer regi
Chapter 6 Real-Time Output Function 6.4 OPERATION When port 0 is in the real-time output port mode, the contents of the buffer registers (P0H and P0L) are sent to the output latches for output to the pins of port 0 in synchronization with the occurrence of a trigger condition listed in Table 6-2. For example, let’s select, as an output trigger source, a signal (INTC10 or INTC11) indicating that timer 1 (TM1) of 8-bit timer/counter 1 coincides with the compare register (CR10 or CR11).
µPD78214 Sub-Series Fig. 6-4 Real-Time Output Port Operation Timing FFH CR11 8-bit timer/ counter 1 CR11 CR11 CR11 0H Timer starts INTC11 interrupt request CPU operation Buffer register (P0H) D01 Output latches (P07-P04) D00 D02 D01 D03 D02 D04 D03 The contents of the buffer register and compare register are rewritten by software processing or macro service (see Section 12.4).
Chapter 6 Real-Time Output Function Fig.
µPD78214 Sub-Series 6.5 APPLICATION EXAMPLE This section describes an example of application in which P00 through P03 are used as a 4-bit real-time output port. Each time TM1 for 8-bit timer/counter 1 coincides with the contents of CR10, the contents of the P0L are output to P00 through P03. At this point, an interrupt occurs, and the interrupt handling routine for this interrupt sets the next data to be output and determines the timing at which the output is to change (see Fig 6-6). See Section 7.
Chapter 6 Real-Time Output Function Fig. 6-7 Contents of the Control Register for the Real-Time Output Function RTPC 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 Uses pins P00 to P03 as real-time output ports Disables data transfer by INTP0 from the buffer register to the output latch Uses pins P04 to P07 as ordinary output ports 6 Selects a 4-bit separate real-time output port Fig.
µPD78214 Sub-Series Fig. 6-9 Interrupt Request Handling When the Real-Time Output Function Is Used Timer interrupt Set the interval Set the value to be output next in the P0L buffer register Return 6.6 NOTES (1) When the P0ML or P0MH is set to 1, the output buffer for the corresponding output port is turned on to output the contents of the port 0 output latch, regardless of the contents of the port 0 mode register (PM0).
Chapter 6 Real-Time Output Function (4) With an in-circuit emulator, digital noise cannot be eliminated normally from the INTP0 pin. When it is specified that data transfer from the buffer register to the output latch be performed according to a signal from the INTP0 pin, data transfer may occur according to an erroneously detected edge. Keep in mind this characteristic when using the in-circuit emulator. See the notes in Chapter 11 for details of erroneous detection of edges.
106
CHAPTER 7 TIMER/COUNTER UNITS The µPD78214 contains one 16-bit timer/counter unit (channel) and three 8-bit timer/counter units (channels).
µPD78214 Sub-Series Fig.
Chapter 7 Timer/Counter Units 7.1 16-BIT TIMER/COUNTER 7.1.1 Functions The 16-bit timer/counter can function as an interval timer and can also be used for programmable square wave output and pulse width measurement. In addition to these basic functions, the 16-bit timer/counter can be used for the following: • PWM output • Period measurement (1) Interval timer When operating as an interval timer, the 16-bit timer/counter generates an internal interrupt at specified intervals.
110 P24/INTP3 Mode register (INTM1) ES30 Edge detector ES31 1/8 16 16 16 16 Clear MOD0 8 Internal bus CE0 8 CLR01 ENTO1 OVF0 RESET Capture/compare control register (CRC0) Timer control register (TMC0) PWM/PPG output control MOD1 Overflow Coincidence 16-bit timer 0 (TM0) 16 16 Compare register (CR01) Coincidence Capture register (CR02) Capture trigger fCLK/8 INTP3 16 Compare register (CR00) 16 Internal bus Fig.
Chapter 7 Timer/Counter Units (1) 16-bit timer 0 (TM0) TM0 is a count-up timer using a count clock of fCLK/8. The count operation of TM0 can be enabled or disabled by timer control register 0 (TMC0). TM0 allows only read operation using a 16-bit manipulation instruction. When the RESET signal is applied, TM0 is cleared to 0000H, and count operation stops. (2) Compare registers (CR00, CR01) The CR00 and CR01 registers are 16-bit registers for holding a value that determines the period of the interval timer.
µPD78214 Sub-Series Fig. 7-3 Format of Timer Control Register 0 (TMC0) TMC0 7 6 5 4 3 2 1 0 CE3 0 0 0 CE0 OVF0 0 0 OVF0 TM0 overflow flag 0 Overflow does not occur 1 Overflow occurs (countiing up from FFFFH to 0000H) CE0 TM0 counting control 0 Clears and stops counting 1 Enables counting These bits control counting for 8-bit timer/ counter 3 (see Fig. 7-123). Remark The OVF0 bit can be reset only by software.
Chapter 7 Timer/Counter Units (3) Timer output control register (TOC) The TOC register is an 8-bit register for specifying the active level of timer output and for enabling/disabling timer output. The lower 4 bits control the timer output operation (on the TO0 and TO1 pins) of the 16-bit timer/counter. (The higher 4 bits control the timer output operation (on the TO2 and TO3 pins) of 8-bit timer/counter 2.) The TOC register allows only write operation using an 8-bit manipulation instruction. Fig.
µPD78214 Sub-Series 7.1.4 Operation of 16-Bit Timer 0 (TM0) (1) Basic operation The 16-bit timer/counter performs count operation by counting up with a count clock of fCLK/8. When the RESET signal is applied, TM0 is cleared to 0000H, and count operation stops. Bit 3 (CE0) of timer control register 0 (TMC0) is used to enable/disable count operation. When the CE0 bit is reset to 1 by software, TM0 is cleared to 0000H by the first count clock pulse, then count-up operation starts.
Chapter 7 Timer/Counter Units (c) When the value of TM0 is FFFFH Count clock fCLK/8 TM0 FFFEH FFFFH 0H 1H OVF0 Cleared by software OVF0←0 7 (2) Clear operation After a coincidence with the CR01 compare register, 16-bit timer 0 (TM0) can be automatically cleared. If a TM0 clear cause occurs, TM0 is cleared to 0000H by the next count clock pulse. This means that even if a TM0 clear cause occurs, TM0 holds the value existing at that time until the next count clock pulse is applied. Fig.
µPD78214 Sub-Series Fig. 7-8 Clear Operation When the CE0 Bit Is Reset to 0 (a) Basic operation Count clock TM0 n-1 n 0 CE0 (b) Restart after 0 is set in TM0 cleared Count clock TM0 n-1 n 0 0 1 CE0 When the CE0 bit is set to 1 after this count clock, counting starts from 0 on the count clock input after the CE0 bit has been set.
Chapter 7 Timer/Counter Units 7.1.5 Compare Register and Capture Register Operations (1) Compare operation The 16-bit timer/counter performs an operation to compare the values set in the compare registers with timer count values. When the values set in the compare registers (CR00, CR01) coincide with count values of 16-bit timer 0 (TM0), the coincidence signal is sent to the output control circuit. At the same time, the interrupt requests (INTC00, INTC01) are generated.
µPD78214 Sub-Series Fig. 7-10 TM0 Cleared After a Coincidence Is Detected CR01 CR00 CR00 TM0 count value CR01 0H Count starts CE0←1 Cleared Cleared INTC00 interrupt request INTC01 interrupt request Remark CLR01 = 1 (2) Capture operation The 16-bit timer/counter performs a capture operation to load the count value of the timer into the capture register in synchronism with an external trigger.
Chapter 7 Timer/Counter Units Fig. 7-11 Capture Operation FFFFH TM0 count value D1 D0 D2 0H 7 Count starts CE0←1 INTP3 pin input INTP3 interrupt request Capture register (CR02) D0 D1 D2 OVF0 Remark Dn: TM0 count value (n = 0, 1, 2, ...) CLR01 = 0 Caution With an in-circuit emulator, digital noise on the INTP3 pin cannot be removed correctly. When the capture function is used, the operation described below is performed if an edge is detected erroneously.
120 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 0 ENTO0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 ALV0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 × × 0 MOD0 MOD1 CRC0 Toggle output (low/high active) Toggle output (low/high active) × 1 Tied high/low PWM output (high/low active) PWM output (high/low active) Tied high/low Toggle output (low/high active
Chapter 7 Timer/Counter Units (1) Basic operation By setting ENTOn (n = 0, 1) of the timer output control register (TOC) to 1, the timer outputs (TO1, TO0) can be changed with the timing determined by MOD0, MOD1, and CLR01 of capture/compare control register 0 (CRC0). In addition, by clearing ENTOn (n = 0, 1) to 0, the levels of the timer outputs (TO1, TO0) can be tied. The level where an output is tied is determined by ALVn (n = 0, 1) of the timer output control register (TOC).
µPD78214 Sub-Series 7.1.7 PWM Output The PWM output function outputs a PWM signal whose period coincides with the full-count period of 16-bit timer 0 (TM0). The pulse width of TO0 is determined by the value of CR00, and the pulse width of TO1 is determined by the value of CR01. Before this function can be used, the CLR01 bit of capture/compare control register 0 (CRC0) must be set to 0.
Chapter 7 Timer/Counter Units Fig. 7-14 Example of PWM Output Using TM0 FFFFH FFFFH FFFFH CR01 CR01 CR00 CR00 TM0 count value CR00 0H INTC00 INTC01 7 TO0 TO1 Remark ALV0 = 0, ALV1 = 0 Fig. 7-15 PWM Output When CR00 = FFFFH FFFFH FFFFH FFFFH FFFFH FFFFH Count clock period T 2 2 TM0 count value 1 1 0 0 0 INTO00 OVF flag TO0 Pulse width Pulse period = 65536T T Duty factor = 65535 × 100 = 99.
µPD78214 Sub-Series Even if the value of a compare register (CR00, CR01) coincides with the value of 16-bit timer 0 (TM0) more than once during one period of PWM output, the output levels on the timer outputs (TO0, TO1) do not change. Fig. 7-16 Example of Rewriting Compare Register CR00 FFFFH FFFFH T2 T2 TM0 count value T1 T1 T1 0H CR00 T1 T2 TO0 Rewriting CR00 TO0 does not change though CR00 coincides with TM0 Cautions 1.
Chapter 7 Timer/Counter Units 2. If timer output is disabled (ENTOn = 0: n = 0, 1), the output level on the TOn (n = 0, 1) pin is the inverted value of the value set in ALVn (n = 0, 1). Accordingly, note that if timer output is disabled when the PWM output function is selected, the active level is output. 7.1.8 PPG Output The PPG output function outputs a square wave that has a period determined by the CR01 compare register, and has a pulse width determined by the CR00 compare register.
µPD78214 Sub-Series Fig. 7-19 PPG Output When CR00 = CR01 n n n n-1 n-1 Count period T TM0 count value 2 2 1 1 0 0 0 INTC00 INTC01 TO0 Pulse width = nT Pulse period = (n + 1)T Fig.
Chapter 7 Timer/Counter Units Even if the value of the CR00 compare register coincides with the value of 16-bit timer 0 (TM0) more than once during one period of PPG output, the output levels on the timer outputs (TO0, TO1) are not inverted. Fig. 7-21 Example of Rewriting Compare Register CR00 CR01 CR01 T2 T2 TM0 count value T1 T1 0H CR00 T1 7 T2 TO0 Rewriting CR00 TO0 does not change though CR00 coincides with TM0 Remark ALV0 = 1 Cautions 1.
µPD78214 Sub-Series 2. If the current value of the CR01 compare register is decreased below the value of 16-bit timer 0 (TM0), the PPG period becomes as long as the full-count time of TM0. At this time, if CR01 is rewritten after the value of the CR00 compare register coincides with the value of TM0, the inactive level is output until TM0 overflows to 0, then normal PPG output is resumed.
Chapter 7 Timer/Counter Units 7.1.9 Sample Applications (1) Interval timer operation (1) By free running 16-bit timer 0 (TM0), and adding a value to a compare register (CR00, CR01) in an interrupt handling routine, the 16-bit timer/counter can be used as an interval timer whose period is as long as the added value. (See Fig. 7-24.) This interval timer has a resolution of 1.3 µs, and can count up to 87.4 ms (at internal system clock fCLK = 6 MHz).
µPD78214 Sub-Series Fig. 7-25 Setting of Control Registers for Interval Timer Operation (1) ★ (a) Timer control register 0 (TMC0) TMC0 7 6 5 4 3 2 1 0 × 0 0 0 1 0 0 0 Overflow flag Enables counting TM0 (b) Capture/compare control register 0 (CRC0) CRC0 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 Disables clearing TM0 Both TO0 and TO1 are used for toggle output Fig.
Chapter 7 Timer/Counter Units Fig. 7-27 Interrupt Request Handling for Interval Timer Operation (1) INTC00 interrupt Calculation of timer value at which next interrupt is to occur CR00←CR00 + n Other interrupt program RETI 7 (2) Interval timer operation (2) The 16-bit timer/counter can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand. (See Fig. 7-28.) This interval timer has a resolution of 1.3 µs, and can count up from 1.3 µs to 87.
µPD78214 Sub-Series Fig. 7-29 Setting of Control Registers for Interval Timer Operation (2) ★ (a) Timer control register 0 (TMC0) TMC0 7 6 5 4 3 2 1 0 × 0 0 0 1 0 0 0 Overflow flag Enables counting TM0 (b) Capture/compare control register 0 (CRC0) CRC0 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 0 Clears TM0 when CR01 coincides with TM0 Both TO0 and TO1 are used for toggle output Fig.
Chapter 7 Timer/Counter Units Fig. 7-31 Timing of Pulse Width Measurement FFFFH FFFFH TM0 count value D1 D3 D2 D0 0H Captured Captured Captured 7 Captured Count starts CE0¨ 1 INTP3 external input signal (10000H – D1 + D2) × 8/fCLK (D1 – D0) × 8/fCLK (D3 – D2) × 8/fCLK INTP3 interrupt request CR02 D0 D1 D2 D3 OVF0 Cleared by software Remark Dn: TM0 count value (n = 0, 1, 2, ...) Fig.
µPD78214 Sub-Series (c) External interrupt mode register 1 (INTM1) INTM1 7 6 5 4 3 2 1 0 0 0 × × × × 1 1 Specifies valid edge of INTP3 input to be rising and falling edges × : Don't care Fig.
Chapter 7 Timer/Counter Units (4) PWM output operation In PWM output operation, a pulse signal with a duty factor determined by the value set in a compare register is output. (See Fig. 7-35.) The duty factor of a PWM output signal can be changed in steps of 1/65536 from 1/65536 to 65535/65536. In addition, 16-bit timer 0 (TM0) has two compare registers, so that two types of PWM signals can be output. Fig. 7-36 shows the setting of control registers. Fig. 7-37 shows the setting procedure. Fig.
µPD78214 Sub-Series Fig. 7-37 Setting Procedure for PWM Output PWM output Set CRC0 register CRC0←90H Set TOC register Set P34 pin in control mode PMC3.4←1 Set initial value in compare register Start counting CE0←1 ; Sets bit 3 of TMC0 Fig.
Chapter 7 Timer/Counter Units (5) PPG output operation In PPG output operation, a pulse signal with a period and duty factor determined by the values set in the compare registers is output. (See Fig. 7-39.) Fig. 7-40 shows the setting of control registers. Fig. 7-41 shows the setting procedure. Fig. 7-42 shows the procedure for changing the duty factor of PPG output. Fig.
µPD78214 Sub-Series Fig. 7-41 Setting Procedure for PPG Output PPG output Set CRC0 register CRC0←D8H Set TOC register Set P34 pin in control mode PMC3.4←1 Set period in compare register CR01 Set duty factor in compare register CR00 Start counting CE0←1 ; Sets bit 3 of TMC0 Fig.
Chapter 7 Timer/Counter Units 7.2 8-BIT TIMER/COUNTER 1 7.2.1 Functions Eight-bit timer/counter 1 can function as an interval timer and can also be used for pulse width measurement. In addition to these basic functions, 8-bit timer/counter 1 can be used as a timer for generating an output trigger on a real-time output port. (1) Interval timer When operating as an interval timer, 8-bit timer/counter 1 generates an internal interrupt at specified intervals.
µPD78214 Sub-Series 7.2.2 Configuration Eight-bit timer/counter 1 consists of one 8-bit timer 1 (TM1), one 8-bit compare register (CR10), and one 8-bit capture/compare register (CR11). Fig. 7-43 shows the block diagram of 8-bit timer/counter 1.
Prescaler mode register (PRM1) 1/8 ES00 8 PRS11 PRS10 Caapture trigger MPX Edge detector ES01 PRS12 fCLK/128 fCLK/64 fCLK/32 fCLK/16 fCLK/512 fCLK/256 INTP0 (INTM0) External interrupt mode register 0 8 8 8 8 Clear Internal bus Timer control register 0 (TMC1) Capture/compare register (CR11) RESET 8 8 8 (CRC1) CE1 8 OVF1 Overflow CLR11 Capture/compare control register RESET Compare register (CR10) 8-bit timer 1 (TM1) 8 Internal bus Fig.
µPD78214 Sub-Series (1) 8-bit timer 1 (TM1) TM1 is a timer for counting up with the count clock specified by the lower 4 bits of prescaler mode register 1 (PRM1). The count operation of TM1 can be enabled or disabled by timer control register 1 (TMC1). TM1 allows only read operation using an 8-bit manipulation instruction. When the RESET signal is applied, TM1 is cleared to 00H, and count operation stops.
Chapter 7 Timer/Counter Units 7.2.3 8-Bit Timer/Counter 1 Control Registers (1) Timer control register 1 (TMC1) The TMC1 register is an 8-bit register for controlling the count operations of 8-bit timer 1 (TM1) and 8-bit timer 2 (TM2). The lower 4 bits control the count operation of TM1 of 8-bit timer/counter 1. (The higher 4 bits control the count operation of TM2 of 8-bit timer/counter 2.) The TMC1 register allows both read and write operations using an 8-bit manipulation instruction. Fig.
µPD78214 Sub-Series Fig. 7-45 Format of Prescaler Mode Register 1 (PRM1) 7 6 5 4 PRM1 PRS23 PRS22 PRS21 PRS20 3 2 1 0 PRS12 PRS11 PRS10 0 fCLK = 6 MHz PRS12 PRS11 PRS10 0 0 0 0 0 1 0 1 0 0 1 1 Specification of count clock [Hz] Resolution fCLK/16 2.6 µ s 1 fCLK/32 5.3 µ s 0 0 fCLK/64 10.7 µ s 1 0 1 fCLK/128 21.3 µ s 1 1 0 fCLK/256 42.7 µ s 1 1 1 fCLK/512 85.3 µ s These bits specify the count clock supplied to 8-bit timer/counter 2 (TM2) (see Fig. 7-68).
Chapter 7 Timer/Counter Units 7.2.4 Operation of 8-Bit Timer 1 (TM1) (1) Basic operation Eight-bit timer/counter 1 performs count operation by counting up with the count clock specified by the lower 4 bits of prescaler mode register 1 (PRM1). When the RESET signal is applied, TM1 is cleared to 00H, and count operation stops. Bit 3 (CE1) of timer control register 1 (TMC1) is used to enable/disable count operation.
µPD78214 Sub-Series (c) When the value of TM1 is FFH Count clock TM1 FEH FFH 0H 1H OVF1 Cleared by software OVF1←0 (2) Clear operation After a coincidence with a compare register (CR1m: m = 0, 1) or capture operation, 8-bit timer 1 (TM1) can be automatically cleared. If a TM1 clear cause occurs, TM1 is cleared to 00H by the next count clock pulse. This means that even if a TM1 clear cause occurs, TM1 holds the value existing at that time until the next count clock pulse is applied. Fig.
Chapter 7 Timer/Counter Units Fig. 7-49 TM1 Cleared after Capture Operation Count clock TM1 n n-1 1 0 2 INTP0 TM1 is captured to CR11 here 7 Cleared here TM1 can also be cleared by software when the CE1 bit of the timer control register (TMC1) is reset to 0. Similarly, clear operation is performed by the count clock pulse following the resetting of CE1 bit to 0.
µPD78214 Sub-Series (b) Restart after 0 is set in TM1 cleared Count clock TM1 n-1 n 0 0 1 1 2 CE1 When the CE1 bit is set to 1 aftr this count clock, counting starts from 0 on the count clock input after the CE1 bit has been set. (c) Restart before 0 is set in TM1 cleared Count clock TM1 n-1 n 0 CE1 When the CE1 bit is set to 1 before this count clock, Clearing TM1 by CE1←0 and counting by CE1←1 are performed simultaneously. 7.2.
Chapter 7 Timer/Counter Units Fig. 7-51 Compare Operation FFH TM1 count value Value of CR10 Value of CR11 0H INTC10 interrupt request Count starts CE1←1 Coincidence Coincidence INTC11 interrupt request 7 OVF1 Remark CLR10 = 0, CLR11 = 0, CM = 0 Caution When using an in-circuit emulator, see the notes described in Section 7.5.4. Fig.
µPD78214 Sub-Series Fig. 7-53 Capture Operation FFH TM1 count value D1 D0 D2 0H Count starts INTP0 pin input INTP0 interrupt request Capture/compare register(CR11) D0 OVF1 Remark Dn: TM1 count value (n = 0, 1, 2, ...
Chapter 7 Timer/Counter Units Fig. 7-54 TM1 Cleared after Capture Operations N1 N4 N2 N5 N3 TM1 count value 0H Captured Captured Captured Captured Captured 7 INTP0 pin input INTP0 interrupt request Capture/compare register (CR11) N1 Remark N2 N3 N4 Dn: TM1 count value (n = 0, 1, 2, ...) CLR10 = 0, CLR11 = 0, CM = 1 7.2.
µPD78214 Sub-Series Fig. 7-55 Timing of Interval Timer Operation (1) FFH FFH MOD(3n) n TM1 count value MOD(2n) 0H Timer starts Compare register (CR10) n MOD(2n) MOD(3n) Rewriting by interrupt program INTC10 interrupt request Rewriting by interrupt program Rewriting by interrupt program Interval Interval Interval MOD(4n) Remark Interval = n × x/fCLK, 1 ≤ n ≤ FFH x = 16, 32, 64, 128, 256, 512 Fig.
Chapter 7 Timer/Counter Units Fig. 7-57 Setting Procedure for Interval Timer Operation (1) Interval timer (1) Set PRM1 register Set count value in CR10 register CR10←n Set CRC1 register CRC1←00H 7 Start counting CE1←1 ; Sets bit 3 of TMC1 to 1 INTC10 interrupt Fig.
µPD78214 Sub-Series Fig. 7-59 Timing of Interval Timer Operation (2) (When CR11 Is Used As a Compare Register) n n Cleared Cleared TM1 count value 0H Count starts Compare register (CR11) n Coincidence Coincidence INTC11 interrupt request Interrupt accepted Interval time Interrupt accepted Interval time Remark Interval = (n + 1) × x/fCLK, 0 ≤ n ≤ FFH x = 16, 32, 64, 128, 256, 512 Fig.
Chapter 7 Timer/Counter Units Fig. 7-61 Setting Procedure for Interval Timer Operation (2) Interval timer (2) Set PRM1 register Set count value in CR11 register CR11←n Set CRC1 register CRC1←08H Start counting CE1←1 7 ; Sets bit 3 of TMC1 to 1 INTC11 interrupt (3) Pulse width measurement operation In pulse width measurement, the width of the high level or low level of an external pulse signal applied to the external interrupt request (INTP0) input pin is measured.
µPD78214 Sub-Series Fig. 7-62 Timing of Pulse Width Measurement (When CR11 Is Used As a Capture Register) FFH FFH TM1 count value D3 D1 D2 D0 0H Captured Captured Captured Captured Count starts CE1←1 INTP0 external input signal (D1 – D0) × X/fCLK (100H – D1 + D2) × X/fCLK (D3 – D2) × X/fCLK INTP0 interrupt request Capture/compare register (CR11) D0 D1 D2 OVF1 ↑ Cleared by software Remark Dn: TM1 count value (n = 0, 1, 2, ...
Chapter 7 Timer/Counter Units Fig.
µPD78214 Sub-Series Fig. 7-64 Setting Procedure for Pulse Width Measurement Pulse width measurement Set PRM1 register Set CRC1 register CRC1←04H ; Specifies valid edge of INTP0 input to be both edges and unmasks interrupt Set INTM0 register and MK0L register Initialize buffer memory for capture value X0←0 Start counting CE1←1 ; Sets bit 3 of TMC1 to 1 Enable interrupt INTP0 interrupt Fig.
Chapter 7 Timer/Counter Units 7.3 8-BIT TIMER/COUNTER 2 7.3.
µPD78214 Sub-Series (2) Programmable square wave output Eight-bit timer/counter 2 outputs a square wave separately on the TO2 and TO3 timer output pins. Table 7-12 Programmable Square Wave Output Setting Range of 8-Bit Timer/Counter 2 Minimum pulse width Maximum pulse width 16/fCLK (2.6 µs) 28 × 16/fCLK (683 µs) 32/fCLK (5.3 µs) 28 × 32/fCLK (1.37 ms) 64/fCLK (10.7 µs) 28 × 64/fCLK (2.73 ms) 128/fCLK (21.3 µs) 28 × 128/fCLK (5.46 ms) 256/fCLK (42.7 µs) 28 × 256/fCLK (10.
Chapter 7 Timer/Counter Units (4) External event counter Eight-bit timer/counter 2 counts clock pulses (CI pin input pulses) applied to the external interrupt input pin (INTP2). Table 7-14 indicates the clock signals that can be applied to 8-bit timer/counter 2.
162 Edge detector Edge detector INTP1 INTP2/CI MPX INTP2 INTP1 8 Prescaler mode PRS23 PRS22 PRS21 PRS20 register (PRM1) fCLK/512 fCLK/256 fCLK/128 fCLK/64 fCLK/32 fCLK/16 ES21 ES20 ES11 ES10 1/8 (INTM0) External interrupt mode register 8 RESET 8 8 8 Timer control register (TMC1) CE2 8 8 OVF2 CMD2 Overflow RESET 8 INTC21 Output control circuit INTC20 Output control circuit P37/TO3 P36/TO2 ENT03 ALV3 ENT02 ALV2 Timer output control register (TOC) CLR22 CLR21 PWM/PPG outpu
Chapter 7 Timer/Counter Units (5) Output control circuit When the value of CR20 or CR21 coincides with the value of TM2, timer output can be inverted. By setting the higher 4 bits of the timer output control register (TOC), a square wave can be output on a timer output pin (TO2, TO3). At this time, PWM/PPG output is possible, depending on the setting of capture/ compare control register 2 (CRC2). Timer output can be disabled or enabled by the TOC register.
µPD78214 Sub-Series (2) Prescaler mode register 1 (PRM1) The PRM1 register is an 8-bit register used to specify a count clock for 8-bit timer 1 (TM1) and 8-bit timer 2 (TM2). The higher 4 bits are used to specify a count clock for TM2 of 8-bit timer/counter 2. (The lower 4 bits are used to specify a count clock for TM1 of 8-bit timer/counter 1.) The PRM1 register allows only write operation using an 8-bit manipulation instruction. Fig. 7-68 shows the format of the PRM1 register.
Chapter 7 Timer/Counter Units (3) Capture/compare control register 2 (CRC2) The CRC2 register is used to specify the condition for enabling the clear operation of 8-bit timer 2 (TM2) with the CR21 compare register or CR22 capture register, and also specify a timer output (TO2, TO3) mode. The CRC2 register allows only write operation using an 8-bit manipulation instruction. Fig. 7-69 shows the format of the CRC2 register. When the RESET signal is applied, the CRC2 register is cleared to 10H. Fig.
µPD78214 Sub-Series (4) Timer output control register (TOC) The TOC register is an 8-bit register for controlling the active level of timer output and for enabling/disabling timer output. The higher 4 bits control the timer output operation (on the TO2 and TO3 pins) of 8-bit timer/counter 2. (The lower 4 bits control the timer output operation (on the TO0 and TO1 pins) of the 16-bit timer/counter.) The TOC register allows only write operation using an 8-bit measurement instruction. Fig.
Chapter 7 Timer/Counter Units 7.3.4 Operation of 8-Bit Timer 2 (TM2) (1) Basic operation Eight-bit timer/counter 2 performs count operation by counting up with the count clock specified by the higher 4 bits of prescaler mode register 1 (PRM1). Bit 7 (CE2) of timer control register 1 (TMC1) is used to enable/disable count operation. (The higher 4 bits of the TMC1 register are used to control the operation of 8-bit timer/counter 2.
µPD78214 Sub-Series (c) When the value of TM2 is FFH Count clock fCLK/8 TM2 FEH FFH 0H 1H OVF2 Cleared by software OVF2←0 (2) Clear operation After a coincidence with the CR21 compare register or capture operation, 8-bit timer 2 (TM2) can be automatically cleared. If a TM2 clear cause occurs, TM2 is cleared to 00H by the next count clock pulse. This means that even if a TM2 clear cause occurs, TM2 holds the value existing at that time until the next count clock pulse is applied. Fig.
Chapter 7 Timer/Counter Units TM2 can also be cleared by software when the CE2 bit of the timer control register (TMC1) is reset to 0. Similarly, clear operation is performed by the count clock pulse following the resetting of CE2 bit to 0.
µPD78214 Sub-Series (c) Restart before 0 is set in TM2 cleared Count clock TM2 n-1 n 0 1 2 CE2 When the CE2 bit is set to 1 before this count clock, Clearing TM2 by CE2←0 and counting by CE2←1 are performed simultaneously. 7.3.5 External Event Counter Function Eight-bit timer/counter 2 can count clock pulses externally applied to the CI pin. The external event counter operation mode requires no particular selection method.
Chapter 7 Timer/Counter Units Fig. 7-75 External Event Count Timing of 8-Bit Timer/Counter 2 (1) When occurrences of one edge are counted (maximum frequency = fCLK/24) 12/fCLK(Min.) 12/fCLK(Min.) 24/fCLK(Min.) CI 8-12/fCLK ICI 16/fCLK (constant) 7 Countable timing of TM2 Count clock of TM2 TM2 Dn + 1 Dn Dn + 2 Dn + 3 Remark ICI: CI input signal after passing through the edge detector (2) When occurrences of both edges are counted (maximum frequency = fCLK/32) 16/fCLK(Min.) 16/fCLK(Min.
µPD78214 Sub-Series The count operation of TM2 is controlled by the CE2 bit of the TMC1 register as in the case of basic operation. When the CE2 bit is set to 1 by software, TM2 is cleared to 00H by the first count clock pulse, then count-up operation starts. When the CE2 bit is set to 0 by software during TM2 count operation, TM2 is cleared to 00H by the next count clock pulse, and count operation stops.
Chapter 7 Timer/Counter Units Fig. 7-77 Example Where Input of No Valid Edge Cannot Be Distinguished from Input of Only One Valid Edge with External Event Counter CI TM2 0 2 1 0 Cannot be distinguished Count starts 7 Fig. 7-78 How to Distinguish Input of No Valid Edge from Input of Only One Valid Edge with External Event Counter (a) Count start processing Count starts Clear INTP2 interrupt request flag IF0L.2←0 Start counting TMC1.
µPD78214 Sub-Series (b) Count value read processing Reads count value Read contents of TM2 A←TM2 A = 0? Yes ; Check TM2 value. If 0, check interrupt request flag. No Yes IF0L.2 = 1? No ; Check contents of PIF2. If 1, valid edge has been input. A←A + 1 End ; The number of valid edges input to register A is set. 3. With an in-circuit emulator, digital noise on the CI/INTP2 pin cannot be removed correctly.
Chapter 7 Timer/Counter Units 7.3.6 One-Shot Timer Function Eight-bit timer/counter 2 has an operation mode in which the full-count (FFH) is reached as the result of count operation. Fig. 7-79 One-Shot Timer Operation FFH TM2 count value Value of CR21 7 0H Count starts CE2←1 Cleared OVF2←0 INTC21 OVF2 As shown in Fig. 7-79, a one-shot interrupt is generated when the value (00H-FFH) set in the CR20 or CR21 register coincides with the value of TM2.
µPD78214 Sub-Series 7.3.7 Compare Register and Capture Register Operations (1) Compare operation Eight-bit timer/counter 2 performs an operation to compare the values set in the compare registers with timer count values. When the values set in the compare registers (CR20, CR21) coincide with count values of 8-bit timer 2 (TM2), the coincidence signal is sent to the output control circuit. At the same time, the interrupt requests (INTC20, INTC21) are generated.
Chapter 7 Timer/Counter Units Fig. 7-81 TM2 Cleared After a Coincidence Is Detected FFH CR20 TM2 count value CR21 CR21 CR21 0H ( Count starts CE2←1 CLR21←0 ( Count stops Count starts CE2←0 CE2←1 CLR21←1 ( Cleared Cleared ( 7 INTC20 INTC21 TO2 pin output ENTO2←1 ALV2←1 ( ( Inactive level TO3 pin output ENTO3←1 ALV3←1 ( ( Inactive level OVF2 Cleared by software Remark CLR22 = 0 Caution When using an in-circuit emulator, see the notes described in Section 7.5.4.
µPD78214 Sub-Series Fig. 7-82 Capture Operation FFH TM2 count value D1 D0 D2 0H Count starts CE←1 INTP1 pin input INTP1 interrupt request Interrupt accepted Capture register (CR22) D0 (undefined) Interrupt accepted D1 (undefined) OVF2 CPU operation Reads CR22 Remark Dn: TM2 count value (n = 0, 1, 2, ...
Chapter 7 Timer/Counter Units Fig. 7-83 TM2 Cleared after Capture Operation N1 N4 N2 N3 TM2 count value N5 0H Captured Captured Captured Captured Captured 7 INTP1 pin output INTP1 interrupt request Capture/compare register (CR22) N1 N2 N3 N4 Remark CLR21 = 0, CLR22 = 1 7.3.8 Basic Operation of Output Control Circuit The output control circuit controls the levels of the timer outputs (TO2, TO3) according to the coincidence signal from the compare registers.
180 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 0 ENTO2 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 ALV2 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 × × × 0 × × Note 0 × × Note × × × × CMD2 × CLR21 Note CLR22 TMC1 Toggle output (low/high active) Toggle output (low/high active) Tied high/low PWM output (
Chapter 7 Timer/Counter Units (1) Basic operation By setting ENTOn (n = 2, 3) of the timer output control register (TOC) to 1, the timer outputs (TO2, TO3) can be changed with the timing determined by MOD0, MOD1, and CLR21 of capture/compare control register 2 (CRC2). In addition, by clearing ENTOn (n = 2, 3) to 0, the levels of the timer outputs (TO2, TO3) can be tied. The level where an output is tied is determined by ALVn (n = 2, 3) of the timer output control register (TOC).
µPD78214 Sub-Series Table 7-16 TO2 and TO3 Toggle Output (fCLK = 6 MHz) Count clock Minimum pulse width Maximum pulse width fCLK/16 2.6 µs 28 × 16/fCLK (683 µs) fCLK/32 5.3 µs 28 × 32/fCLK (1.37 ms) fCLK/64 10.7 µs 28 × 64/fCLK (2.73 ms) fCLK/128 21.3 µs 28 × 128/fCLK (5.46 ms) fCLK/256 42.7 µs 28 × 256/fCLK (10.9 ms) fCLK/512 85.3 µs 28 × 512/fCLK (21.75 ms) Caution When using an in-circuit emulator, see the notes described in Section 7.5.4. 7.3.
Chapter 7 Timer/Counter Units Table 7-17 PWM Output on TO2 and TO3 (fCLK = 6 MHz) Count clock Minimum pulse width PWM period (ms) PWM frequency (Hz) fCLK/16 2.7 0.7 1465 fCLK/32 5.3 1.4 732 fCLK/64 10.7 2.7 366 fCLK/128 21.3 5.5 183 fCLK/256 42.7 10.9 92 fCLK/512 85.3 21.8 46 Fig. 7-86 shows an example of 2-channel PWM output. Fig. 7-87 shows PWM output when FFH is set in the CR20 compare register. 7 Fig.
µPD78214 Sub-Series Fig. 7-87 PWM Output When CR20 = FFH FFH FFH FFH FFH FFH Count clock period T 2 2 TM2 count value 1 1 0 0 0 INTO20 OVF flag TO2 Pulse width T Duty factor = 255 × 100 = 99.6 (%) 256 Pulse period = 256T Remark ALV2 = 0 Even if the value of a compare register (CR20, CR21) coincides with the value of 8-bit timer 2 (TM2) more than once during one period of PWM output, the output levels on the timer outputs (TO2, TO3) are not inverted. Fig.
Chapter 7 Timer/Counter Units Cautions 1. If a value less than the value of 8-bit timer 2 (TM2) is set in a compare register (CR20, CR21), a PWM signal with a 100% duty factor is output. Rewrite the CR20 or CR21 compare register, if required, by using an interrupt generated by a coincidence between TM2 and the compare register. Fig.
µPD78214 Sub-Series Fig. 7-90 shows an example of PPG output using 8-bit timer 2 (TM2). Fig. 7-91 shows an example of PPG output when CR20 = CR21. Fig. 7-92 shows an example of PPG output when CR20 = 00H. Fig.
Chapter 7 Timer/Counter Units Fig. 7-91 PPG Output When CR20 = CR21 n n n n-1 n-1 Count period T TM2 count value 2 2 1 1 0 0 0 INTC20 7 INTC21 TO2 Pulse width = nT Pulse period = (n + 1)T Remark ALV2 = 0 Fig.
µPD78214 Sub-Series Even if the value of the CR20 compare register coincides with the value of 8-bit timer 2 (TM2) more than once during one period of PPG output, the output level on the timer output (TO2) is not inverted. Fig. 7-93 Example of Rewriting Compare Register CR20 CR21 CR21 CR21 T2 T2 TM2 count value CR20 T1 T1 T1 T2 TO2 Rewriting CR20 TO2 does not change though CR20 coincides with TM2 Remark ALV2 = 1 Cautions 1.
Chapter 7 Timer/Counter Units 2. If the current value of the CR21 compare register is decreased below the value of 8-bit timer 2 (TM2), the PPG period becomes as long as the full-count time of TM2. At this time, if CR21 is rewritten after the value of the CR20 compare register coincides with the value of TM2, the inactive level is output until TM2 overflows to 0, then normal PPG output is resumed.
µPD78214 Sub-Series 7.3.11 Sample Applications (1) Interval timer operation (1) By free running 8-bit timer 2 (TM2), and adding a value to a compare register (CR20, CR21) in an interrupt handling routine, 8-bit timer/counter 2 can be used as an interval timer whose period is as long as the added value. (See Fig. 7-96.) In addition, 8-bit timer 2 (TM2) has two compare registers, so that interval timers with two types of periods can be produced. Fig. 7-97 shows the setting of control registers. Fig.
Chapter 7 Timer/Counter Units Fig.
µPD78214 Sub-Series Fig. 7-99 Interrupt Request Handling for Interval Timer Operation (1) INTC20 interrupt Calculation of timer value at which next interrupt is to occur CR20←CR20 + n Other interrupt program RETI (2) Interval timer operation (2) Eight-bit timer/counter 2 can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand. (See Fig. 7-100.) Fig. 7-101 shows the setting of control registers, and Fig. 7-102 shows the setting procedure. Fig.
Chapter 7 Timer/Counter Units Fig.
µPD78214 Sub-Series Fig. 7-102 Setting Procedure for Interval Timer Operation (2) Interval timer Set PRM1 register Set count value in CR21 register CR21←n Set CRC2 register CRC2←18H Set TMC1 register CE2←1 CMD2←0 ; Sets bit 7 of TMC1 to 1 Sets normal mode (CMD2 = 0) INTC21 interrupt (3) Pulse width measurement operation In pulse width measurement, the width of the high level or low level of an external pulse signal applied to the INTP1 pin is measured.
Chapter 7 Timer/Counter Units Fig. 7-103 Timing of Pulse Width Measurement FFH FFH TM2 count value D3 D1 D2 D0 0H Captured Captured Captured 7 Captured Count starts INTP1 external input signal (100H – D1+ D2) × X/fCLK (D1 – D0) × X/fCLK (D3 – D2) × X/fCLK INTP1 interrupt request Capture register (CR22) D0 D1 D2 D3 OVF2 ↑ Cleared by software Remark Dn: TM2 count value (n = 0, 1, 2, ...) Fig.
µPD78214 Sub-Series (c) Timer control register 1 (TMC1) TMC1 7 6 5 4 3 2 1 0 1 0 0 0 × × 0 0 Normal mode Overflow flag Enables counting (d) External interrupt mode register 0 (INTM0) INTM0 7 6 5 4 3 2 1 0 × × 1 1 × × 0 × Specifies valid edge of INTP1 input to be rising and falling edges Fig.
Chapter 7 Timer/Counter Units Fig. 7-106 Interrupt Request Handling for Pulse Width Calculation INTP1 interrupt Store captured value in memory Xn+1←CR22 Calculation of pulse width Yn=Xn+1 – Xn RETI 7 (4) PWM output operation In PWM output operation, a pulse signal with a duty factor determined by the value set in a compare register is output. (See Fig. 7-107.) The duty factor of a PWM output signal can be changed in steps of 1/256 from 1/256 to 255/256.
µPD78214 Sub-Series Fig.
Chapter 7 Timer/Counter Units Fig. 7-109 Setting Procedure for PWM Output Fig. 7-110 Changing Duty Factor of PWM Output Preprocessing for changing duty factor PWM output Clear INTC21 interrupt request flag CIF21←0 Set CRC2 register CRC2←90H Enable INTC21 interrupt CMK21←0 ; Clears bit 0 of IF0H ; Clears bit 0 of MK0H Set TOC register INTC21 interrupt 7 Set P34 pin in control mode PMC3.
µPD78214 Sub-Series Fig.
Chapter 7 Timer/Counter Units Fig. 7-113 Setting Procedure for PPG Output Fig. 7-114 Changing Duty Factor of PPG Output Preprocessing for changing duty factor PPG output Clear INTC20 interrupt request flag CIF20←0 Set CRC2 register CRC2←D8H Enable INTC20 interrupt CMK20←0 ; Clears bit 3 of IF0H ; Clears bit 3 of MK0H Set TOC register INTC20 interrupt 7 Set P34 pin in control mode PMC3.
µPD78214 Sub-Series Fig.
Chapter 7 Timer/Counter Units (7) One-shot timer operation When functioning as a one-shot timer, 8-bit timer/counter 2 generates only one interrupt when a specified count time has elapsed after the start of 8-bit timer 2 (TM2). (See Fig. 7-118.) An additional one-shot timer operation can be started by clearing the OVF2 bit of timer control register 1 (TMC1). Fig. 7-119 shows the setting of control registers. Fig. 7-120 shows the setting procedure. Fig.
µPD78214 Sub-Series Fig. 7-120 Setting Procedure for One-Shot Timer Operation One-shot timer Set one-shot timer mode ; Sets bit 5 of TMC1 to 1 CMD2←1 Set PRM1 register Set count value in CR21 register CR21←n Set CRC2 register CRC2←10H Start counting CE2←1 ; Sets bit 7 of TMC1 to 1 INTC21 interrupt Fig.
Chapter 7 Timer/Counter Units 7.4 8-BIT TIMER/COUNTER 3 7.4.1 Functions Eight-bit timer/counter 3 can be used as an interval timer, and also as a counter for generating a clock signal used with the baud rate generator. When operating as an interval timer, 8-bit timer/counter 3 generates an internal interrupt at specified intervals. Table 7-19 indicates the interval setting range. Table 7-19 Intervals of 8-Bit Timer/Counter 3 Resolution Minimum interval Maximum interval 8/fCLK (1.3 µs) 8/fCLK (1.
µPD78214 Sub-Series Fig.
Chapter 7 Timer/Counter Units 7.4.3 8-Bit Timer/Counter 3 Control Registers (1) Timer control register 0 (TMC0) The TMC0 register is an 8-bit register for controlling the count operation of 8-bit timer 3 (TM3). The higher 4 bits control the count operation of TM3 of 8-bit timer/counter 3. (The lower 4 bits control the count operation of TM0 of the 16-bit timer/counter.) The TMC0 register allows both read and write operations using an 8-bit manipulation instruction. Fig.
µPD78214 Sub-Series 7.4.4 Operation of 8-Bit Timer 3 (TM3) (1) Basic operation Eight-bit timer/counter 3 performs count operation by counting up with the count clock specified by the higher 4 bits of prescaler mode register 0 (PRM0). When the RESET signal is applied, TM3 is cleared to 00H, and count operation stops. Bit 7 (CE3) of timer control register 0 (TMC0) is used to enable/disable count operation. (The higher 4 bits of the TMC0 register are used to control the operation of 8-bit timer/counter 3.
Chapter 7 Timer/Counter Units (2) Clear operation After a coincidence with the CR30 compare register, 8-bit timer 3 (TM3) can be automatically cleared. If a TM3 clear cause occurs, TM3 is cleared to 00H by the next count clock pulse. This means that even if a TM3 clear cause occurs, TM3 holds the value existing at that time until the next count clock pulse is applied. Fig.
µPD78214 Sub-Series (b) Restart after 0 is set in TM3 cleared Count clock TM3 n-1 n 0 0 1 CE3 When the CE3 bit is set to 1 after this count clock, counting starts from 0 on the count clock input after the CE3 bit has been set. (c) Restart before 0 is set in TM3 cleared Count clock TM3 n-1 n 0 1 2 CE3 When the CE3 bit is set to 1 before this count clock, Clearing TM3 by CE3←0 and counting by CE3←1 are performed simultaneously. 7.4.
Chapter 7 Timer/Counter Units Fig. 7-128 Compare Operation CR30 CR30 TM3 count value 0H Cleared (coincidence) Count starts CE←1 Cleared (coincidence) INTC30 interrupt request 7 7.4.6 Sample Applications (1) Interval timer operation Eight-bit timer/counter 3 can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand. Eight-bit timer/counter 3 can also be used for baud rate generation. This interval timer has a resolution from 1.3 µs to 85.
µPD78214 Sub-Series Fig. 7-130 Setting of Control Registers for Interval Timer Operation ★ (a) Timer control register 0 (TMC0) TMC0 7 6 5 4 3 2 1 0 × 0 0 0 1 0 0 0 Overflow flag Enables counting TM0 (b) Prescaler mode register 0 (PRM0) PRM0 7 6 PRS3 PRS2 5 4 PRS1 PRS0 3 2 1 0 0 0 0 0 Specifies count clock (x/fCLK; where x = 16, 32, 64, 128, 256, or 512) Fig.
Chapter 7 Timer/Counter Units (2) The OVFm flag for holding an overflow from a timer/counter is contained in register TMCn used to control the operation of the timer/counter. When a read/modify/write instruction (such as AND TMCn,#7FH) is executed, for example, the OVFm flag may be cleared. (Even if the OVFm flag is 0 when the OVFm flag is read by the CPU, the OVFm flag may already be set to 1 by a timer/counter overflow when the OVFm flag is rewritten to by the CPU.
µPD78214 Sub-Series Fig. 7-132 Count Start Operation Count clock TMn (n = 0 to 3) 0 0 1 2 3 CEn Actual counting starts Count start instruction by software (CEn←1) (5) Even when an instruction is executed to stop a timer (CEn ← 0), the value of TMn is not cleared to 0 immediately. Instead, the value of TMn is cleared to 0 by the count clock pulse occurring after an instruction is executed (CEn ← 0) to stop the timer.
Chapter 7 Timer/Counter Units (6) When a register associated with a timer/counter is accessed, wait states as many as the maximum number of clock pulsesNote indicated below are automatically inserted.
µPD78214 Sub-Series (9) When PWM is used, a PWM signal with a 100% duty factor is output if a value less than the value of TMn (n = 0, 2) is set in compare register CRnm (n = 0, 2, m = 0, 1). CRnm rewrite operation must be performed using an interrupt generated by a coincidence between TMn and CRnm to be rewritten. Fig.
Chapter 7 Timer/Counter Units (10)Notes on compare register rewrite operation when PPG output is used (a) If a value less than the value of TMn is written into compare register CRn0 (n = 0, 2) before the value of the CRn0 register coincides with the value of TMn (n = 0, 2), a PPG signal with a 100% duty factor is output in that period. CRn0 rewrite operation must be performed using an interrupt generated by a coincidence between TMn and CRn0. Fig.
µPD78214 Sub-Series Fig. 7-137 Example of PPG Output Period Made Longer Full count value n1 n1 n1 n3 n3 n5 n2 n2 TMn n4 0H CRn0 n3 CRn1 n1 n4 n2 TOp (p = 0,2) The PPG period is extended when a value, n2 less than TMn value, n5 is written to CRn1 here. TOp becomes inactive when CRn0 coincides with TM0; otherwise, TOp remains active. Remark ALVp = 1 (c) If the PPG period is too short for interrupt acceptance, the measures described in (a) and (b) above do not lead to solution.
Chapter 7 Timer/Counter Units (14) With an in-circuit emulator, digital noise cannot be removed correctly. When a timer/counter is used together with edge detection function, note the point below. (a) When IE-78210-R is used Operations are performed on an erroneously detected edge. (b) When other in-circuit emulators are used • Timer/counter capture operation and clear operation An erroneously detected edge has no effect.
µPD78214 Sub-Series Fig. 7-138 Interrupt Request Generation Using External Event Counter CI 8 to 12 clocks ICI 16 clocks (Max.) Countable timing of TM2 Count clock of TM2 n-1 TM2 n Coincidence between INTP2 and ICI n+1 ICI: Signal that has gone through the edge detector of CI input TM2 counts up here or is compared with compare register.
Chapter 7 Timer/Counter Units Fig. 7-140 How to Distinguish Input of No Valid Edge from Input of Only One Valid Edge with External Event Counter (a) Count start processing Count starts Clear INTP2 interrupt request flag IF0L.2←0 ; Clears PIF2 (0) Start counting TMC1.7←1 7 ; Sets CE2 (1) End (b) Count value read processing Reads count value Read contents of TM2 A←TM2 A = 0? No Yes ; Check TM2 value. If 0, check interrupt request flag. Yes IF0L.2 = 1? No ; Check contents of PIF2.
µPD78214 Sub-Series (3) With an in-circuit emulator, digital noise cannot be removed correctly. When the timer/counter is used together with edge detection function, note the point below. • When IE-78210-R is used All functions are performed on an erroneously detected edge. • When other in-circuit emulators are used When 8-bit timer/counter 2 is used as an external event counter, an erroneously detected edge changes the timing of coincidence-based interrupt generation.
Chapter 7 Timer/Counter Units Fig.
µPD78214 Sub-Series (c) Event counter function (with only 8-bit timer/counter 2) An erroneously detected edge causes no change in the value of the timer/counter. However, the timing for generating an interrupt by a coincidence between the value of the timer/counter and the value of a compare register becomes faster by the number of edges detected erroneously. The timer output function is not affected by an erroneously detected edge, but operates with the correct timing.
CHAPTER 8 A/D CONVERTER The µPD78214 contains an analog-to-digital (A/D) converter with eight multiplexed analog input pins (AN0 through AN7). This A/D converter uses successive approximation The conversion result is stored in an 8-bit A/D conversion result register (ADCR). Conversion can be performed at high speed (with conversion time of 30 µs and at fCLK = 6 MHz) and with high accuracy.
226 INTP5 AN6 AN7 AN4 AN5 AN3 AN2 AN1 AN0 Input selector Edge detector 8 A/D converter mode register (ADM) Trigger enable 8 INTAD 8 A/D conversion result register (ADCR) Internal bus INTP5 Voltage comparator Successive approximation register (SAR) Control circuit RESET Conversion trigger Sample and hold circuit Selector Interrupt request R/2 R R/2 Series resistor string Tap selector Fig.
Chapter 8 A/D Converter Cautions 1. To prevent malfunction due to noise, insert a capacitor between each analog input pins (AN0 through AN7) and the AVSS pin and between the reference voltage input pin (AVREF) and the AVSS pin. Fig. 8-2 Example of Capacitors Connected to the A/D Converter Pins µPD78214 Analog input AN0-AN7 100500pF Reference voltage input AVREF AVSS 8 2. Do not apply a voltage out of the rated voltage range (AVSS through AVREF) to the A/D converter input pins. See Section 8.
µPD78214 Sub-Series (7) Edge detector The edge detector detects the valid edge of an input at the interrupt request input pin (INTP5) and generates an external interrupt request signal (INTP5) and an external trigger for A/D conversion. The valid edge of an input at the INTP5 pin is specified by external interrupt mode register 1 (INTM1) (see Fig. 11-2). The external trigger is enabled or disabled by the ADM register (see Section 8.2). 8.
Chapter 8 A/D Converter Fig.
µPD78214 Sub-Series 8.3 OPERATION 8.3.1 Basic A/D Converter Operation (1) A/D conversion sequence The A/D converter operates as follows: (a) The input selector selects one of the analog input pins (AN0 through AN7) according to the mode of operation specified in the A/D converter mode register (ADM). (b) The sample and hold circuit samples the voltage at the analog input pin selected by the input selector.
Chapter 8 A/D Converter A/D conversion continues until the CS bit is reset by software. If data is written to the ADM register during conversion, conversion is initialized. If the CS bit is 1, conversion is started from the beginning. When the RESET signal is input, the ADCR register contents become undefined.
µPD78214 Sub-Series (3) A/D conversion time The time required for A/D conversion is determined by the system clock frequency (fCLK) and the FR bit of the ADM register. To maintain A/D conversion accuracy above a certain level, it is necessary to set the FR bit as listed in Table 8-2 according to the system clock frequency. This A/D conversion time includes all the time required for one A/D conversion sequence and the sampling time. Table 8-2 shows the conversion time and sampling time.
Chapter 8 A/D Converter 8.3.3 Scan Mode In the scan mode, signals input from the analog input pins, specified by bits 1 through 3 (ANI0 through ANI2) of the A/D converter mode register (ADM), are selected successively for conversion. For example, when the ANI2 through ANI0 bits of the ADM register are 001, the AN0 and AN1 pins are scanned repeatedly, starting at the ANI0 pin in the sequence: AN0 → AN1 → AN0 → AN1 →...
µPD78214 Sub-Series 2. If the ADM register is set after registers related to interrupts have been set during the scan mode, an unwanted interrupt may occur, thus causing the storage location of the conversion result to appear to have shifted. To prevent this, take the actions listed below in the stated order. • Write to the ADM register. • Reset the interrupt request flag (PIF5) to 0. • Set the interrupt mask flag or interrupt service mode flag. 8.3.
Chapter 8 A/D Converter (2) Scan-mode A/D conversion When triggered, conversion begins with the signal input to the AN0 pin. When the conversion sequence for the AN0 pin is completed, the signal at the next analog input pin is converted. Each time a conversion sequence is completed, an interrupt request (INTAD) is generated. Fig.
µPD78214 Sub-Series Fig. 8-10 Example of Malfunction in a Hardware-Started A/D Conversion INTP5 Note 2 Conversion trigger A/D converter operatioon ADCR Conversion 1 Conversion 2 Conversion result 1 7FHNote 1 INTAD Conversion completion and conversion trigger occur simultaneously Notes 1. When the operation is normal, the result of conversion 2 is stored. If a malfunction occurs, however, value 7FH is stored. 2. Time from when an input to the INT5 pin changes to when its edge is asserted.
Chapter 8 A/D Converter Fig. 8-11 Select-Mode A/D Conversion Started by Hardware INTP5 pin input (rising edge valid) A/D conversion Standby state ANn ANn ANn ANn ANm ANm ADM writing CS←1, TRG←1 ADM writing CS←1, TRG←1 ANn ADCR ANn Standby state ANn ANn ANm INTAD 8 INTAD accepted Remark n = 0, 1, ..., 7 m = 0, 1, ..., 7 (2) Scan-mode A/D conversion When A/D conversion is started, the analog signal input to the AN0 pin is converted.
238 INTAD ADCR A/D conversion (scans AN0 to AN2) INTP5 pin input (rising edge valid) ADM writing CS←1, TRG←1 Standby state AN0 AN1 INTAD accepted AN0 AN1 AN2 AN2 AN0 AN0 AN1 AN0 AN0 AN0 AN1 Standby state AN1 ADM rewriting CS←1, TRG←1 AN2 Fig.
Chapter 8 A/D Converter 8.4 INTERRUPT REQUEST FROM THE A/D CONVERTER The A/D converter generates an A/D conversion end interrupt request (INTAD), each time a conversion sequence is completed, except for the select mode. The interrupt control flags are shared by the INTAD interrupt and the INTP5 external interrupt. Therefore, the timing at which an interrupt request occurs varies depending on the mode of A/D conversion specified in the ADM register, as listed in Table 8-3.
µPD78214 Sub-Series (2) About hardware-started A/D conversion (a) Eight to twelve system clocks are required from when a valid edge appears at the INTP5 pin until A/D conversion is actually started. Take this delay into consideration when designing your application. See Chapter 11 for details of the edge detection function. (b) Digital noise at the INTP6 pin cannot be eliminated normally with an in-circuit emulator.
Chapter 8 A/D Converter Fig. 8-14 Example of Malfunction in a Hardware-Started A/D Conversion INTP5 Note 2 Conversion trigger A/D converter operatioon Conversion 1 ADCR Conversion 2 Conversion result 1 7FHNote 1 8 INTAD Conversion completion and conversion trigger occur simultaneously Notes 1. When the operation is normal, the result of conversion 2 is stored. If a malfunction occurs, however, value 7FH is stored. 2. Time from when an input to the INT5 pin changes to when its edge is asserted.
242
CHAPTER 9 ASYNCHRONOUS SERIAL INTERFACE The µPD78214 contains an asynchronous serial interface, UART (Universal Asynchronous Receiver Transmitter). This interface transmits 1-byte data following a start bit and is capable of full-duplex transmission. The µPD78214 also contains a baud rate generator for UART, which allows data to be transmitted at a wide baud rate range. In addition, a baud rate can also be specified by dividing the frequency of the clock input to the ASCK pin.
P31/TxD P30/RxD 1 16 Reception control parity check Shift register RXB Reception buffer 1/8 INTSR PE FE 1/8 OVE (ASIS) INTSER RESET 1 16 Transmission control parity generation Transmission shift register TXS Asynchronous serial interface status register PSI INTST RXE PS0 1/8 Selector 244 Internal bus Fig.
Chapter 9 Asynchronous Serial Interface (1) Reception buffer (RXB) The reception buffer holds the receive data. Each time the shift register receives 1 byte of data, it sends it to this reception buffer. If the data length is specified to be 7 bits, the receive data is sent to bits 0 through 6 of the RXB. The MSB of the RXB is always kept as 0. Only an 8-bit manipulation instruction can be used for the reception buffer, and its use is limited to read operations.
µPD78214 Sub-Series Fig.
Chapter 9 Asynchronous Serial Interface Fig.
µPD78214 Sub-Series • Odd parity In contrast to even parity, the parity bit for odd parity is controlled so that the number of 1 bits in the transmit data becomes odd. When data is received, the number of 1 bits in it is counted, and if the number of 1 bits is even, a parity error is detected. • 0 parity When data is transmitted, the parity bit is reset to 0, regardless of what the transmit data is like. During reception, the parity bit is not checked.
Chapter 9 Asynchronous Serial Interface 9.3.4 Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set to 1, reception is enabled, and the input to the RxD pin is sampled. Sampling at the RxD pin is performed using the serial clock specified in the ASIM register. When the input to the RxD pin becomes low, the 1/16 frequency division counter starts counting. When the counter reaches eight counts, it outputs the start timing signal for data sampling.
µPD78214 Sub-Series Table 9-1 Causes of Reception Errors Cause Reception error ★ Parity error The parity of the receive data does not match the type of parity specified at transmission. Framing error No stop bit is detectedNote. Overrun error Before the receive data is read out from the reception buffer, the next data is received. Note Reception assumes that only one stop bit is used.
Chapter 9 Asynchronous Serial Interface 9.4 BAUD RATE GENERATOR 9.4.1 Configuration of the Baud Rate Generator for UART Fig. 9-8 shows the configuration of the baud rate generator. Fig.
µPD78214 Sub-Series Fig.
Chapter 9 Asynchronous Serial Interface 9.4.3 Operation of the Baud Rate Generator for UART The baud rate generator for UART starts operating, when the CE bit of the baud rate generator control register (BRGC) is set to 1. The baud rate clock to be generated is a signal obtained by dividing either the internal system clock (fCLK) or the clock input from the external baud rate input (ASCK) pin. Resetting the CE bit to 0 stops the operation of the baud rate generator.
µPD78214 Sub-Series 9.5 BAUD RATE SETTING The baud rate can be set by three methods listed in Table 9-2. The table indicates the ranges of baud rates that can be generated by each method, the baud rate calculation formulas, and the selection methods.
6 MHz Internal system clock (fCLK) 2.44 2.34 2.34 2.34 2.34 — FCH F9H E9H D9H C9H B9H A9H 99H 89H 92H 84H 75 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2.34 0.00 2.34 2.34 2.34 2.34 — BRGC value Baud rate [bps] Baud rate error (%) 12 MHz Oscillation frequency (fxx) or external clock input (fx) — — 88H 98H A8H B8H C8H D8H E8H F8H FBH — BRGC value — — 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.27 — Baud rate error (%) 5.5296 MHz 11.
µPD78214 Sub-Series 9.5.2 Example of Setting the Baud Rate When 8-bit Timer/Counter 3 Is Used Table 9-4 lists examples of setting the baud rate when 8-bit timer/counter 3 is used. When using 8-bit timer/ counter 3, reset the SCK bit of the asynchronous serial interface mode register (ASIM) to 0. See Section 7.4 for how to use 8-bit timer/counter 3.
212 155 77 38 fCLK/8 fCLK/8 fCLK/8 fCLK/8 fCLK/8 fCLK/8 fCLK/8 — — 110 150 300 600 1200 2400 4800 9600 19200 — — 4 9 19 155 fCLK/16 75 Baud rate [bps] m — — 2.34 2.34 2.34 0.16 0.16 0.16 0.03 0.16 Baud rate error (%) 6 MHz Internal system clock (fCLK) MHz Count clock 12 MHz Oscillation frequency fosc (MHz) — — — fCLK/8 fCLK/8 fCLK/8 fCLK/8 fCLK/8 fCLK/8 fCLK/16 Count clock — — — 8 17 35 71 143 195 143 m — — — 0.00 0.00 0.00 0.00 0.
µPD78214 Sub-Series 9.5.3 Example of Setting the BRGC When the External Baud Rate Input (ASCK) Is Used Table 9-5 lists examples of setting the BRGC register when an external baud rate input (ASCK) is used. To use the ASCK input, set the SCK bit of the asynchronous serial interface mode register (ASIM) to 1. Table 9-5 Examples of Setting the BRGC When an External Baud Rate Input (ASCK) Is Used fASCK (ASCK input frequency) 153.
CHAPTER 10 CLOCK SYNCHRONOUS SERIAL INTERFACE 10.1 FUNCTION The clock synchronous serial interface of the µPD78214 is configured as shown in Fig. 10-1. The clock synchronous serial interface supports the following two operation modes: (1) Three-wire serial I/O mode (MSB first) Three lines, serial clock (SCK) and serial bus lines (SO, SI), are used to transfer 8-bit data.
260 P32/SCK P33/SO/SB0 P27/SI RESET CRXE WUP N-ch open-drain output enabled CTXE MOD1 CSIM 1/8 CLS1 Selector Serial clock control circuit Serial clock counter Bus release/command/ acknowledge detector circuit Shift register SIO CLS0 8 D Q SET CLEAR RELT Interrupt signal generator circuit SO latch Internal bus RELD CLS1 CLS0 Serial clock selector INTCSI Busy/ acknowledge output circuit CMDT 1/2 CMDD ACKE ACKD 8-bit timer/counter 3 output fCLK/8 fCLK/32 ACKT SBIC 1/8 Fi
Chapter 10 Clock Synchronous Serial Interface (1) Shift register (SIO) Converts 8-bit serial data into 8-bit parallel data and vice versa. The SIO is used for both transmission and reception. Data is shifted in (received) or shifted out (transmitted) from the MSB. The actual transmission/reception is controlled by writing or reading the contents of the SIO. The 8-bit manipulation instruction can read or write the contents of this register. The contents become undefined when RESET is input.
µPD78214 Sub-Series 10.3 CONTROL REGISTERS 10.3.1 Clock Synchronous Serial Interface Mode Register (CSIM) This 8-bit register specifies a serial interface operation mode, serial clock and wake-up function. The 8-bit manipulation instruction and bit manipulation instruction can read and write the contents of the CSIM register. Fig. 10-2 shows the format. The register is set to 00H when RESET is input. Fig.
Chapter 10 Clock Synchronous Serial Interface 10.3.2 Serial Bus Interface Control Register (SBIC) The SBIC register consists of bits that control the status of the serial bus, as well as bits that indicate the status of the data input from the serial bus. This 8-bit register can be used only in SBI mode, not in three-wire serial I/O mode. The 8-bit manipulation instruction and bit manipulation instruction manipulate the contents of the register.
µPD78214 Sub-Series Fig.
Chapter 10 Clock Synchronous Serial Interface 10.4 OPERATIONS IN THE THREE-WIRE SERIAL I/O MODE In three-wire serial I/O mode, the device can communicate with a device having a conventional clock synchronous serial interface. Basically, communication is performed over three lines of serial clock (SCK), serial data output (SO) and serial data input (SI). A handshaking line is required to connect the device to two or more devices. Fig.
µPD78214 Sub-Series Fig. 10-5 Timing in Three-Wire Serial I/O Mode SCKNote 1 2 DI7 SI (input) 3 DI6 4 DI5 5 DI4 6 DI3 7 DI2 8 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SO (output) INTCSI Transfer end interrupt occurs Transfer starts in synchronization with SCK falling edge Executing instruction to write data to SIO Notes Master CPU : Output Slave CPU : Input In three-wire serial I/O mode, the SO pin sends a CMOS push-pull output.
Chapter 10 Clock Synchronous Serial Interface 10.4.2 Operation When Only Transmission Is Permitted Transmission is enabled when the CTXE bit of the clock synchronous serial interface mode register (CSIM) is set (1). If the CTXE bit is set, writing the contents of the shift register (SIO) invokes the start of transmission. If the CTXE bit is reset (0), the output from the SO pin goes to the high-impedance state.
µPD78214 Sub-Series (1) Selecting the internal clock as the serial clock When transmission and reception are started, the serial clock is output from the SCK pin. In synchronization with the falling edge of the serial clock, data is sequentially output from the SIO to the SO pin. In synchronization with the rising edge of the serial clock, data is sequentially shifted in from the SI pin to the SIO.
Chapter 10 Clock Synchronous Serial Interface (2) Function to select a chip by its address The master sends an address to select a slave chip. (3) Wake-up function Using the wake-up function (which can be set or released by software), a slave device can easily detect whether it receives the address (chip select). If the wake-up function is set, a serial reception interrupt (INTCSI) occurs only when the address is received.
µPD78214 Sub-Series 10.5.2 Configuration of the Serial Interface Fig. 10-9 is a block diagram of the µPD78214. The serial clock pin (SCK) and serial data bus pin SB0 are configured as shown in Fig. 10-8.
P32/SCK P33/SO/SB0 P27/SI RESET CRXE WUP N-ch open-drain output enabled CTXE CLS1 CLS0 CLS1 MOD1 CSIM 1/8 Serial clock control circuit Serial clock counter Bus release/command/ acknowledge detector circuit Shift register SIO CLS0 8 D Q SET CLEAR RELT Interrupt signal generator circuit SO latch Internal bus RELD CLS1 CLS0 MPX INTCSI Busy/ acknowledge output circuit CMDT CMDD fCLK/8 fCLK/32 1/2 ACKT SBIC 1/8 Fig.
µPD78214 Sub-Series 10.5.3 Detecting an Address Match SBI communication is started when a slave device is selected according to the address sent by the master device. The software detects whether the address of a slave device matches the sent address. In the wake-up state (WUP set to 1), the slave device generates a serial transfer completion interrupt request only when it receives the address.
Chapter 10 Clock Synchronous Serial Interface Fig.
µPD78214 Sub-Series (2) Serial bus interface control register (SBIC) This 8-bit register consists of bits controlling the serial bus statuses and flags indicating the statuses of data input from the serial bus. The 8-bit manipulation instruction and bit manipulation instruction can read and write the contents of the register. The bits have different read/write attributes. Fig. 10-11 shows the format. The value of the SBIC register is set to 00H when RESET is input. Fig.
Chapter 10 Clock Synchronous Serial Interface Fig. 10-11 Format of SBIC Register (2/2) Acknowledge trigger bit (W) When this bit is set after transfer, ACK is output in synchronization with the next SCK. After the ACK signal is output, this bit is automatically cleared to 0. ACKT Cautions: 1 Do not set this bit to 1 before serial transfer is completed. 2 ACKT cannot be cleared by software. 3 Set ACKT when ACKE = 0.
µPD78214 Sub-Series (3) Shift register (SIO) This 8-bit shift register is used for parallel-serial conversion. The data written into the SIO is output to the serial data bus. The data on the serial data bus is read into the SIO. Fig. 10-12 shows the configuration of the shift register and related components. Fig.
Chapter 10 Clock Synchronous Serial Interface 10.6 SBI COMMUNICATION AND SIGNALS This section describes the format of the SBI serial data and signals to be used. Serial data transferred via SBI can be divided into three groups: address, command, and data. Each frame of serial data is formed as shown below: (bus release signal) + (command signal) + 8-bit data + ACK + (BUSY) Fig. 10-13 shows the transfer timing of the address, command, and data. Fig.
µPD78214 Sub-Series 10.6.2 Command Signal (CMD) The command signal is the SB0 line going from high to low while the SCK line is high (the serial clock is not output). The master device outputs this signal. Fig. 10-15 Command Signal SCK "H" SB0 The slave device contains the hardware to detect the command signal. 10.6.3 Address The master device outputs an address, which is 8-bit data, to select one of the slave devices connected to the bus line. Fig.
Chapter 10 Clock Synchronous Serial Interface 10.6.4 Command and Data The master device sends commands to, and sends or receives data to or from, the slave device selected according to the specified address. Fig. 10-18 Command SCK 1 2 C7 SB0 3 C6 4 C5 5 C4 6 C3 7 C2 8 C1 C0 Command Command signal Fig. 10-19 Data SCK SB0 1 2 D7 3 D6 D5 4 5 D4 6 D3 7 D2 D1 8 D0 Data 10 The 8-bit data following the command signal is defined as a command.
µPD78214 Sub-Series 10.6.6 Busy Signal (BUSY) and Ready Signal (READY) The busy signal informs the master device that the slave device is preparing for data transmission or reception. The ready signal informs the master device that the slave device is ready for data transmission or reception. Fig. 10-21 Busy Signal and Ready Signal SCK SB0 8 9 ACK BUSY READY In SBI mode, the slave device drives the SB0 line low to inform the master device that the slave is busy.
Chapter 10 Clock Synchronous Serial Interface Fig. 10-23 ACKT Operation SCK 6 SB0 7 D2 8 D1 9 D0 ACK signal is output during first clock cycle immediately after ACKT is set. ACK ACKT When set during this period Caution Do not set ACKT before transfer has been completed. Fig.
µPD78214 Sub-Series (d) When ACKE is set to 1 for a short period of time SCK SB0 D1 D2 The ACK signal is not output D0 ACKE When ACKE is set or cleared during this period, and ACKE = 0 at the falling edge of SCK Fig.
Chapter 10 Clock Synchronous Serial Interface Fig. 10-26 BSYE Operation SCK SB0 6 7 D2 8 D1 9 D0 ACK BUSY BSYE When BSYE = 1 at this point When reset operation is executed during this period and BSYE = 0 at the falling edge of SCK.
284 Master Master Command signal (CMD) Output device Bus release signal (REL) Signal name Falling edge of SB0 while SCK is set to 1 Rising edge of SB0 while SCK is set to 1 Definition SB0 SCK SB0 SCK “H” “H” Timing chart • CMDT is set. • RELT is set. Output condition Table 10-2 Signals in SBI Mode (1/3) • CMDD is set. • RELD is set. • CMDD is cleared. Influence on flag (1) If this signal is output after the REL signal, the transmission data is an address.
Slave Slave Ready signal (READY) Master/ slave Output device Busy signal (BUSY) Acknowledge signal (ACK) Signal name High signal output to SB0 before serial transfer is started and after serial transfer is completed Low sgnal output to SB0, following the acknowledge signal Low signal output to SB0 within a single cycle of the SCK clock after serial reception has been completed Definition 9 D0 ACK D0 SCK SB0 SB0 ACK BUSY BUSY Timing chart READY READY 1 BSYE is set to 0.
286 Master Master Master/ slave Address (A7 to A0) Command (C7 to C0) Data (D7 to D0) 8-bit data transferred in synchronization with SCK when neither the REL signal nor CMD signal is output 8-bit data transferred in synchronization with SCK after the CMD signal is output without the REL signal 8-bit data transferred in synchronization with SCK after the REL and CMD signals are output Synchronization clock for output address, command, or data, ACK signal, and synchronous BUSY signal.
Chapter 10 Clock Synchronous Serial Interface 10.6.8 Communication In SBI communication, the master device outputs an address on the serial bus and, usually, one target slave device is selected out of two or more devices according to the address. Once the target device has been determined, commands and data are transferred between the master device and slave device to implement serial communication. Figs. 10-27 to 10-30 show the timing charts for data communication. 10.6.
288 SB0 pin SCK pin Hardware operation Program processing Slave device processing (receiver) Transfer line Hardware operation Program processing Master device processing (transmitter) Set Set RELT CMDT Write to SIO Set RELD Set Clear Set CMDD CMDD CMDD Set CMDT 1 A7 2 A6 3 Address A4 5 A3 Serial reception A5 4 Serial transmission 6 A2 7 A1 Generate INTCSI A0 Output Output ACK BUSY Read Compare Set SIO addresses ACKT ACK Set ACKD BUSY Clear BUSY Clear BUSY READY Stop
SB0 pin SCK pin Hardware operation Program processing Slave device processing (receiver) Transfer line Hardware operation Program processing Master device processing (transmitter) Write to SIO Set CMDD Set CMDT 1 C7 2 C6 3 C3 Command C4 5 Serial reception C5 4 6 Serial transmission C2 7 C1 Generate INTCSI C0 Read SIO Analyze command Clear BUSY Clear BUSY Output Output BUSY ACK BUSY Set ACKT ACK Set ACKD READY Stop SCK Remark This timing is valid only under the followi
290 SB0 pin SCK pin Hardware operation Program processing Slave device processing (receiver) Transfer line Hardware operation Program processing Master device processing (transmitter) Write to SIO 1 D7 2 D6 3 D5 Data D4 5 D3 Serial reception 4 6 Serial transmission D2 7 D1 Read SIO Generate INTCSI D0 Clear BUSY Clear BUSY Output Output BUSY ACK BUSY Set ACKT ACK Set ACKD READY Stop SCK Remark This timing is valid only under the following conditions: • The master is only
SB0 pin SCK pin BUSY Stop SCK Write to SIO Clear BUSY Hardware operation READY Program processing Slave device processing (transmitter) Transfer line Hardware operation Program processing Master device processing (receiver) Read SIO D7 1 2 D6 3 Data D4 5 D3 6 Serial transmission D5 4 Serial reception D2 7 D1 8 Output BUSY BUSY Clear BUSY Write to SIO READY 1 D7 2 D6 D5 3 Serial reception Receive data processing Set ACKD ACK Output ACK Set ACKT Remark This ti
µPD78214 Sub-Series 10.7 NOTES (1) Do not change CTXE from 0 to 1 and CRXE from 1 to 0, or vice versa, by means of a single instruction. If this is attempted, the serial clock counter will malfunction and the first communication after the change will be terminated before the eighth bit is sent.
CHAPTER 11 EDGE DETECTION FUNCTION Pins P20 to P26 support an edge detection function to program a rising or falling edge. The detected edge is sent to the internal hardware. Table 11-1 shows the relationship between pins P20 to P26, and the use of the detected edge.
µPD78214 Sub-Series Fig.
Chapter 11 Edge Detection Function Fig.
µPD78214 Sub-Series 11.2 EDGE DETECTION ON PIN P20 An edge on pin P20 is detected after noise elimination by means of analog delay. A pulse width of at least 10 µs is required to detect the edge. Fig. 11-3 Edge Detection on Pin P20 10 µ s (Min.) P20 input 10 µ s (Max.) 10 µ s (Max.
Chapter 11 Edge Detection Function 11.3 EDGE DETECTION ON PINS P21 TO P26 An edge on pins P21 to P26 is detected after digital noise elimination by means of clock sampling. The digital noise elimination is performed by means of sampling with the fCLK/4 clock. The input signal is eliminated as noise if an identical level is not obtained three or more times in a row (even if an identical level is consecutively obtained twice).
µPD78214 Sub-Series (b) Erroneously detected edge during input of a high signal Noise INTPn input (n = 0 to 6) fCLK/4 After noise rejection "L" Falling edge detection Rising edge detection Erroneously detected edge If the IE-78210-R is used, the real-time output port, timer/counter, and A/D converter operate according to the erroneously detected edge.
Chapter 11 Edge Detection Function (5) If noise input to pins P21 to P26 is synchronized with the fCLK/4 clock of the µPD78214, it may not be judged as being noise. If the input of such noise is possible, add a filter to the input pin so that the noise can be eliminated. (6) An in-circuit emulator cannot successfully eliminate digital noise. It may erroneously detect a falling edge due to noise during the input of a low signal and a rising edge due to the noise during the input of a high signal (see Fig.
µPD78214 Sub-Series • Compare operation of the timer/counter : If the mode for carrying out a clear operation after a capture operation is selected, or if timer/counter 2 is used as an external event counter, the erroneously detected edge causes the timing of match interrupt generation to be changed. As a result, the timing of match interrupt generation will disagree with that when the values of the timer/counter and compare register match.
CHAPTER 12 INTERRUPT FUNCTIONS The µPD78214 has the following two interrupt handling modes. Either mode can be selected by the program. Interrupt handling by a macro service is limited to the interrupt request sources provided with a macro service handling mode listed in Table 12-1.
µPD78214 Sub-Series 12.1 INTERRUPT REQUEST SOURCES The µPD78214 has 19 interrupt request sources shown in Table 12-2. Each of these sources is assigned an interrupt vector table.
Chapter 12 Interrupt Functions 12.1.2 Nonmaskable Interrupt Request A nonmaskable interrupt request is input to the NMI pin. When a valid edge, specified by bit 0 (ESNMI) of external interrupt mode register 0 (INTM0), is input to the NMI pin, an interrupt request is generated. A nonmaskable interrupt request is accepted unconditionally, even in an interrupt disabled state. In this case, interrupt priority control is not applied; the nonmaskable interrupt request takes precedence over all other interrupts.
µPD78214 Sub-Series (2) Selecting INTP5 or INTAD Interrupt INTP5 or INTAD is selected by the A/D converter mode register (ADM). (Either of these interrupts is selected automatically, according to the mode of operation specified for the A/D converter.) Both 8-bit manipulation instruction and bit manipulation instruction can be used to read data from and write data to the ADM register. The format of this register is shown in Fig. 12-2. See Chapter 8 for control of the A/D converter.
Chapter 12 Interrupt Functions Table 12-3 Flags for Interrupt Request Sources Interrupt request source Interrupt request flag Interrupt mask flag Interrupt service mode flag Priority specification flag INTP0 PIF0 PMK0 PISM0 PPR0 INTP1 PIF1 PMK1 PISM1 PPR1 INTP2 PIF2 PMK2 PISM2 PPR2 INTP3 PIF3 PMK3 PISM3 PPR3 INTC00 CIF00 CMK00 CISM00 CPR00 INTC01 CIF01 CMK01 CISM01 CPR01 INTC10 CIF10 CMK10 CISM10 CPR10 INTC11 CIF11 CMK11 CISM11 CPR11 INTC21 CIF21 CMK21 CISM21
µPD78214 Sub-Series 12.2.2 Interrupt Mask Register (MK0) The MK0 register is a 16-bit register consisting of interrupt mask flags. Each interrupt mask flag enables or disables the corresponding interrupt request. When the RESET signal is input, the register is set to FFFFH, thus disabling all maskable interrupts. If an interrupt mask flag is set to 1, it inhibits acceptance of the corresponding interrupt request.
Chapter 12 Interrupt Functions When a low-priority vectored interrupt is being handled, vectored interrupt requests with lower and higher priorities are accepted for multiple-interrupt handling provided that interrupts are enabled. When a high-priority interrupt is being handled, high-priority vectored interrupts are accepted for multiple-interrupt handling provided that interrupts are enabled. Moreover, any interrupt requests specifying a macro service are accepted regardless of their priority.
µPD78214 Sub-Series 12.2.6 Program Status Word (PSW) The PSW is a register that holds the result of instruction execution and the current status of interrupt requests. The register is mapped with the IE flag that specifies whether to enable maskable interrupts and the ISP flag to control multiple-interrupt handling. The PSW can be read and written to in 8-bit units. It can also be manipulated by a bit manipulation instruction and dedicated instructions (EI and DI).
Chapter 12 Interrupt Functions Resetting the NMIS bit to 0 during execution of a nonmaskable interrupt service program enables multipleinterrupt handling for nonmaskable interrupt requests. If the NMIS bit is 0, a new nonmaskable interrupt request is accepted even when a nonmaskable interrupt service program is running. Fig.
µPD78214 Sub-Series (c) If a new NMI request occurs during execution of an NMI service program (when the NMIS bit is reset to 0 by the current NMI service program after the NMI request occurs) Main routine (NMIS = 1) Pending NMI request is accepted when NMIS = 0.
Chapter 12 Interrupt Functions 3. Nonmaskable interrupts are always accepted except during execution of the nonmaskable interrupt handling program (except when multiple-interrupt handling for nonmaskable interrupts have been enabled by resetting the NMIS bit of the IST register to 0 during execution of the nonmaskable interrupt handling program) and except a period between a special instruction described in Section 12.3.5 and an instruction that follows that special instruction.
µPD78214 Sub-Series Fig.
Chapter 12 Interrupt Functions 12.3.4 Multiple-Interrupt Handling The µPD78214 performs multiple-interrupt handling in which another interrupt request is accepted during one interrupt is already being handled. Multiple-interrupt handling runs according to priority. Priority control is based on either default priority or programmable priority specified in the priority specification flag register (PR0).
µPD78214 Sub-Series Fig.
Chapter 12 Interrupt Functions Fig.
µPD78214 Sub-Series Fig. 12-12 Example of Handling Interrupts That Occur Simultaneously Main routine [Nesting 1] [Nesting 2] Processing b • Vectored interrupt request a (low priority) • Macro service request b (high priority) • Macro service request c (low priority) • Vectored interrupt request d (high priority) Default priority: a > b > c > d Processing d Processing c Processing a 12.3.
Chapter 12 Interrupt Functions Example of correct coding (2) • • • LOOP: BT IF0H.3, $NEXT Remark The BTCLR would be more convenient than the BT, because it clears the flags automatically. BR $LOOP ← NEXT: • • • Interrupts or macro services will not be kept pending long, because they are processed after the BR is executed. 2.
µPD78214 Sub-Series 3. “Peripheral RAM” corresponds to the internal RAM at addresses 0FC80H through 0FDFFH (for the µPD78212, 0FD80H through 0FDFFH). 4. 1 clock = 1/fCLK (167 ns at 12 MHz). (3) Macro service processing time The time required to process a macro service varies, depending on the type of the macro service, as listed in Table 12-6.
Chapter 12 Interrupt Functions 12.4 MACRO SERVICE FUNCTION 12.4.1 Macro Service Outline Macro service is one of the interrupt handling methods. When a vectored interrupt is processed, the contents of the program counter (PC) and the program status word (PSW) are saved in the stack and the PC is loaded with the vector address retrieved from the vector table. With the macro service function, a different type of processing (mainly data transfer) is performed.
µPD78214 Sub-Series 12.4.2 Macro Service Types The macro service can be used by the 17 types of interrupts listed in Table 12-7 (of which, 15 types can use macro services simultaneously). In addition, three modes of operation are available, and each should be selected according to the application.
Chapter 12 Interrupt Functions (3) Type C Transfers 1-byte data from memory to the real-time output port and the compare register for 8-bit timer/ counter 1 upon each interrupt request. When a specified number of data transfers are performed, a vectored interrupt request is generated. Type C macro service transfers data to two locations upon one interrupt request. In addition, it can be used together with output data ring control and automatic addition of the compare register contents to data.
µPD78214 Sub-Series 12.4.4 Macro Service Control Register (1) Macro service control word The macro service function of the µPD78214 is controlled using the macro service mode registers and macro service channel pointers. The macro service mode registers specify the mode of macro service processing, and the macro service channel pointer specifies the address of a macro service channel to be used.
Chapter 12 Interrupt Functions (2) Macro service mode register A macro service mode register is an 8-bit register that specifies the mode of macro service operation. It is mapped in internal RAM as part of macro service control word (see Fig 12-16). Fig. 12-17 shows the format of the macro service mode register. Fig.
µPD78214 Sub-Series Table 12-8 Interrupt Requests That Can Specify Macro Service and Related SFRs (Type A) Interrupt request specifying the type A macro service Transfer source/destination SFR INTC10 CR10 register INTC11 CR11 register INTC20 CR20 register INTC21 CR21 register INTC30 CR30 register INTSR RXB register INTST TXS register INTCSI SIO register INTAD ADCR register INTP0 CR11 register INTP1 CR22 register INTP2 TM2 register Caution When the external memory is expanded (or a
Chapter 12 Interrupt Functions Fig.
µPD78214 Sub-Series (2) Macro service channel configuration A channel pointer and a macro service counter (MSC) specify the addresses of transfer source and destination buffers in the internal RAM (at FE00H through FEFFH). (See Fig. 12-19.) The SFR to be accessed is predetermined for each interrupt request. (See Table 12-8.) Fig.
Chapter 12 Interrupt Functions (3) Example of using the type A macro service The following example shows how data received through an asynchronous serial interface is transferred to a buffer area in the internal RAM. Fig. 12-20 Asynchronous Serial Reception Internal RAM 0FEC0H 0FECFH MSC 0F Mode register Channel pointer 41 CF -1 Type A: SFR → memory Internal bus 12 Receive buffer (RXB) RXB/P30 Shift register INTSR macro service request 12.4.
µPD78214 Sub-Series Fig.
Chapter 12 Interrupt Functions (2) Macro service channel configuration The macro service pointer (MP) indicates a data buffer area in the 64K memory space as a transfer source or destination. The SFR pointer (SFRP) is set with the lower 8 bits of the address of an SFR used as a transfer source or destination. The macro service counter (MSC) specifies the number of data transfers to be performed.
µPD78214 Sub-Series (3) Example of using the type B macro service The following example shows how parallel data is input from port 3 in synchronization with an external signal. The external signal is input to the external interrupt pin (INTP4). Fig.
Chapter 12 Interrupt Functions 12.4.7 Macro Service Type C (1) Operation The type C macro service controls 8-bit timer/counter 1 and the real-time output port simultaneously. This macro service transfers data to both the compare register for 8-bit timer/counter 1 and the buffer register for the real-time output port upon one interrupt request. Only INTC10 and INTC11 can use the type C macro service. predetermined as listed in Table 12-8.
µPD78214 Sub-Series Fig.
Chapter 12 Interrupt Functions 1 No Ring control? Yes Decrement ring counter No Ring counter = 0? Yes Subtract modulo register contents from low-order 8-bits of macro service pointer for data (MPDL) and return pointer to the first address 12 Reload modulo register contents to ring counter MSC←MSC – 1 MSC = 0? No Yes Vectored interrupt request occurs Reset interrupt request flag End End 333
µPD78214 Sub-Series (2) Macro service channel configuration There are two types of type C macro service channels, as shown in Fig. 12-26. The timer macro service pointer (MPT) indicates a data buffer area in the 64K memory space from which data is transferred to, or added to the contents of, the compare register for 8-bit timer/counter 1. The data macro service pointer (MPD) indicates a data buffer area in the 64K memory space from which data is transferred to the real-time output port.
Chapter 12 Interrupt Functions (b) With ring control Lower address ↑ Macro service counter (MSC) Ring counter (RC) Modulo register (MR) Data macro service pointer, low (MPDL) Macro service channel Data macro service pointer, high (MPDH) Timer macro service pointer, low (MPTL) Timer macro service pointer, high (MPTH) Mode register Macro service control word ↓ Higher address Channel pointer 12 335
µPD78214 Sub-Series (3) Example of using the type C macro service The following example shows a pattern output to the real-time output port and how the output interval is controlled directly. Update data is transferred from two data areas previously set in the 64K-byte space to the buffer registers (P0H and P0L) and compare registers (CR10 and CR11) for the real-time output port. Fig.
Chapter 12 Interrupt Functions Fig.
µPD78214 Sub-Series Fig. 12-29 Four-Phase Stepping Motor with Phase 1 Excitation 1 2 3 4 1 2 3 Phase A Phase B Phase C Phase D 1 cycle (4 patterns) Fig.
Chapter 12 Interrupt Functions Fig.
µPD78214 Sub-Series Fig. 12-32 Timing Chart 1 for Automatic Addition Control Plus Ring Control (Constant-Speed Rotation with Phases 1 and 2 Excitation) FFH TM1 count value ∆t 0H Count starts INTC10 Compare register (CR10) T0 Buffer register P0L D0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T0+∆t T1+∆t T2+∆t T3+∆t T4+∆t T5+∆t T6+∆t T7+∆t T8+∆t T9+∆t D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 P00 P01 P02 P03 Remark Select a mode in which the MPT contents are retained.
Chapter 12 Interrupt Functions Fig.
µPD78214 Sub-Series Fig. 12-34 Timing Chart 2 for Automatic Addition Control Plus Ring Control (with the Output Timing Varied by Phase 2 Excitation) FFH ∆t7 ∆t5 ∆t6 ∆t4 ∆t3 TM1 count value ∆t2 ∆t1 T0 ∆t9 ∆t8 0H Count starts INTC10 Compare register (CR10) T0 T1 T2 T3 T0+∆t1 T1+∆t2 T2+∆t3 Buffer register P0L D1 D2 D3 D0 P00 P01 P02 P03 Remark Select a mode which increments the MPT.
Chapter 12 Interrupt Functions 12.5 NOTES (1) Do not use the RETI instruction to return from the software interrupt. (2) A macro service request is accepted and processed even when a nonmaskable interrupt service program is running. To disable macro service processing during execution of the nonmaskable interrupt service program, cause the nonmaskable interrupt service program to manipulate the mask register so that no macro service will not occur.
µPD78214 Sub-Series Example of correct coding (2) • • • LOOP: BT IF0H.3, $NEXT Remark The BTCLR would be more convenient than the BT, because it clears the flags automatically. BR $LOOP ← NEXT: • • • Interrupts or macro services will not be kept pending long, because they are processed after the BR is executed. (6) In addition, when you have to use a coding of the instructions listed in Section 12.3.
CHAPTER 13 LOCAL BUS INTERFACE FUNCTION The local bus interface function is provided to connect external memories (ROM and RAM) and I/Os. External memories (ROM and RAM) and I/Os are accessed by using the RD, WR, and ASTB signals, a multiplexed address/data bus consisting of lines AD0 to AD7, and an address bus consisting of lines A8 to A19. Figs. 13-3 and 13-4 show the basic bus interface timing diagrams.
µPD78214 Sub-Series 13.1 CONTROL REGISTERS 13.1.1 Memory Expansion Mode Register (MM) The MM register is an 8-bit register for controlling externally expanded memory, specifying the number of wait states (address space: 00000H to 0FFFFH), and controlling the internal fetch cycle. The MM register can be read and written with 8-bit manipulation instructions and bit manipulation instructions. Fig. 13-1 shows the format of the MM register. When the RESET signal is applied, the register is set to 20H. Fig.
Chapter 13 Local Bus Interface Function 13.1.2 Programmable Wait Control Register (PW) The PW register is an 8-bit register for specifying the number of wait states for external expansion data memory space 10000H to FFFFFH. The PW register can be read and written with both 8-bit manipulation instructions and bit manipulation instructions. Fig. 13-2 shows the format of the PW register. When the RESET signal is applied, the register is set to 80H. Fig.
µPD78214 Sub-Series Fig. 13-3 Read Timing A8-A15 (output) Higher address Hi-Z AD0-AD7 Hi-Z Lower address (output) Data (input) Hi-Z ASTB (output) RD (output) Fig.
Chapter 13 Local Bus Interface Function Fig.
µPD78214 Sub-Series 13.2.3 Memory Mapping with Expanded Memory Figs. 13-6 to 13-9 show the memory maps when the memory has been expanded. Even when the memory has been expanded, external devices at the same addresses as those of the internal ROM area, internal RAM area, or SFR area (excluding the external SFR area (0FFD0H to 0FFDFH)) cannot be accessed. When these addresses are accessed, the memory and SFRs of the µPD78214 take precedence and are accessed.
Chapter 13 Local Bus Interface Function Fig.
µPD78214 Sub-Series Fig.
Chapter 13 Local Bus Interface Function Fig.
µPD78214 Sub-Series Fig.
Chapter 13 Local Bus Interface Function 13.2.4 Example of Connecting Memories Fig. 13-10 shows an example of connecting memories to the µPD78214. In this example, a PROM, SRAM, and mask-programmable ROM are connected to the µPD78214.
µPD78214 Sub-Series Fig. 13-10 Example of Connecting Memories to µPD78214 µPD23C4000A OE CE WORD/BYTE A17 A16 A15 A14 O0-O7 A-1-A13 µPD43256AC-12 74HC32 CS WE OE 74HC04 µPD78214 I/O1-I/O8 74HC138 VDD 74HC375 A0-A14 G1 A19 A18 A17 A16 D4 Q4 D3 Q3 D2 Q2 D1 Q1 ST ST G2A C B A Y1 Y0 G2B µPD27C512D-15 CE WR RD OE A15 A8-A14 74HC573 ASTB LE Q0-Q7 AD0-AD7 D0-D7 OE Remark Pull-up resistors must be connected to the address and address/data bus lines.
Chapter 13 Local Bus Interface Function 13.3 INTERNAL ROM HIGH-SPEED FETCH FUNCTION The µPD78212, µPD78214, and µPD78P214 contain an internal ROM. The internal ROM can be accessed quickly without having to use the bus control circuit. Usually, internal ROM is fetched at the same speed as external ROM. When the IFCH bit of the memory expansion mode register (MM) is set to 1, the high-speed fetch function is enabled, which can speed up internal ROM fetching.
µPD78214 Sub-Series Fig.
Chapter 13 Local Bus Interface Function Fig.
µPD78214 Sub-Series Fig.
Chapter 13 Local Bus Interface Function Fig.
µPD78214 Sub-Series Fig.
Chapter 13 Local Bus Interface Function Fig.
µPD78214 Sub-Series Fig.
Chapter 13 Local Bus Interface Function Fig.
µPD78214 Sub-Series Fig.
Chapter 13 Local Bus Interface Function 13.5 PSEUDO STATIC RAM REFRESH FUNCTION 13.5.1 Function The µPD78214 provides the pseudo static RAM refresh function to enable pseudo static RAM to be connected directly. The pseudo static RAM refresh function outputs refresh pulses at arbitrary intervals. The refresh pulse output cycle period is specified in the refresh mode register (RFM), and the external access cycle is changed to the refresh bus cycle that matches the pseudo static RAM bus cycle.
µPD78214 Sub-Series 13.5.3 Operation (1) Pulse refresh operation To support the pulse refresh cycle of pseudo static RAM, the REFRQ pin outputs refresh pulses, synchronized with the bus cycle. Adjust the oscillator frequency and bits 1 and 0 (RFT1 and RFT0) of the refresh mode register (RFM) so that at least 512 refresh pulses are output in 8 ms.
Chapter 13 Local Bus Interface Function (b) Accessing External Memory The refresh bus cycle is generated at the intervals specified with the refresh mode register (RFM). Pseudo static RAM may malfunction if the access timing overlaps the refresh pulse output timing; therefore, the µPD78214 generates a refresh bus cycle of three clock pulses, synchronized with the bus cycle. Fig.
µPD78214 Sub-Series (2) Self-refresh Self-refresh is performed to retain the contents of pseudo static RAM when in standby mode. (a) Setting self-refresh mode When bit 4 (RFEN) of the RFM register is set to 1, and bit 7 (RFLV) is set to 0, pin REFRQ outputs a low-level signal, requesting pseudo static RAM to enter self-refresh mode. (b) Restoration from self-refresh Refresh pulse output to pseudo static RAM is disabled for approximately 200 nsNote after the output level of pin REFRQ goes high.
Chapter 13 Local Bus Interface Function Caution If the RFEN bit of the refresh mode register (RFM) is already set to 1 (or is simultaneously set to 1) when the RFLV bit is changed from 0 to 1, pin REFRQ may output a glitch, having a peak level of approximately 2.6 V, for approximately 10 ns. When setting the RFLV bit to 1, follow the steps shown in Fig. 13-22. The 200-ns delay after setting RFEN assures the access disabled time when pseudo static RAM returns from self-refresh mode. Fig.
µPD78214 Sub-Series 13.5.4 Example of Connecting Pseudo Static RAM Fig. 13-23 shows an example of connecting pseudo static RAM to the µPD78214. In this example, pseudo static RAM is assigned to addresses 20000H to 3FFFFH. Fig.
Chapter 13 Local Bus Interface Function (3) When macro service Type A or Type C is used in external memory expansion mode (the µPD78213 always uses external memory), an illegal write access may occur. This occurs when any of the following three conditions is satisfied: (a) Data is transferred from memory to an SFR using macro service Type A, and the transfer data is D0H to DFH.
µPD78214 Sub-Series Fig. 13-24 Return from Self-Refresh Self-refresh mode Clear RFEN bit to 0 Set RFLV bit to 1 No RFLV = 1 Yes Set RFEN bit to 1 Approximately 200 ns delay Pulse refresh mode (normal operation) (6) When using the in-circuit emulator, note the following points: • When the RD signal or WR signal is active, a glitch may occur on pins A16 to A19. Fig. 13-25 Glitch Observed on Pins A16 to A19 during Emulation An (n = 16 -19) Approx. 2 V Approx.
Chapter 13 Local Bus Interface Function Fig.
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CHAPTER 14 STANDBY FUNCTION 14.1 FUNCTION OVERVIEW The µPD78214 supports a standby function to reduce the system’s power consumption. With the standby function, two modes are available: • HALT mode: In this mode, only the CPU clock is stopped. Intermittent operation, when combined with normal operating mode, can reduce overall system power consumption. • STOP mode: In this mode, the oscillator is stopped to stop the entire system.
378 RESET NMI fx fxx or Oscillation stops System clock oscillator 1 2 fCLK Frequency divider Interrupt request Reset Oscillation settling time counter (16 bits) Interrupt control Overflow CLK Macro service request EI ××ISM Fig.
Chapter 14 Standby Function 14.2 STANDBY CONTROL REGISTER (STBC) The standby control register (STBC) is an 8-bit register which controls standby mode. The STBC register can be both read and written. Only a specified instruction (MOV STBC, #byte), however, can be used for writing to the register, to prevent the application system stopping unintentionally as a result of a program crash. Fig. 14-3 shows the format of the STBC register. When the RESET signal is input, the register is set to 0000×000B. Fig.
µPD78214 Sub-Series 14.3.2 Releasing HALT Mode HALT mode can be released by any of the following three sources: • Nonmaskable interrupt request (NMI) • Maskable interrupt request (vectored interrupt or macro service) • RESET input Table 14-2 lists the sources used for releasing HALT mode and the operations that are performed after HALT mode is released by each source.
Chapter 14 Standby Function (2) Release by a maskable interrupt request Only maskable interrupts with 0 in the interrupt mask flag can be used to release HALT mode. If the interrupt priority status flag (ISP) is set to 0 (only high-priority interrupts are enabled), only interrupts with 0 in the priority designation flag (high priority) can release HALT mode.
µPD78214 Sub-Series 14.4 STOP MODE 14.4.1 Specifying STOP Mode and Operation States in STOP Mode The system enters STOP mode when the STP bit of the STBC register is set to 1. The STBC register can be written only with a specified 8-bit data write instruction. To specify STOP mode, execute the “MOV STBC, #02H” instruction.
Chapter 14 Standby Function Fig. 14-4 Releasing STOP Mode with an NMI Signal STOP Oscillator fCLK STP flip-flop 1 STP flip-flop 2 NMI input (effective at rising edge) Oscillator stops Count time for oscillation settling time counter Caution If another effective edge of the NMI signal is detected during the oscillation settling time, the oscillation settling time counter is cleared and restarts counting, resulting in a longer wait time than usual.
µPD78214 Sub-Series 14.4.3 Notes on Using STOP Mode Check the following items to ensure that current consumption is appropriately reduced in STOP mode: (1) Is the output level of each output pin appropriate? The appropriate output level of each pin depends on the circuit of the next stage. Select an output level that minimizes current consumption.
Chapter 14 Standby Function Fig. 14-6 Example of Address Bus Arrangement Power supply backed up VDD Power supply not backed up VDD µ PD78214 CMOS IC, etc. An (n = 8 to 15) IN Diode with small VF VSS VSS The outputs of the address/data bus pins are high-impedance in STOP mode. The address/data bus pins are usually pulled up with pull-up resistors.
µPD78214 Sub-Series Fig. 14-8 Example Arrangement for Analog Input Pin Power supply backed up Power supply not backed up VDD AVREF Diode with small VF Signal source µ PD78214 ANn (n = 0 to 7) VSS The voltage input to the AN0 to AN7 pins must be maintained at a level between VSS and VDD. Any voltage falling outside this range increases the current consumption as well as adversely affecting the reliability of the microcomputer. 14.
Chapter 14 Standby Function Fig. 14-9 Example of Longer Oscillation Settling Time NMI (effective at falling edge) CPU operation 216/fCLK STOP mode Wait for oscillation to settle Normal operation Count value of oscillation settling time counter Cleared by effctive edge Oscillation settling time is extended by this period.
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CHAPTER 15 RESET FUNCTION 15.1 RESET FUNCTION When the signal applied to the RESET input pin is low, the system is reset, and each hardware component is set to the state indicated in Table 15-2. All pins, except the power supply pin, assume the high-impedance state. Table 15-1 lists the states of pins during reset and after the reset state is released.
µPD78214 Sub-Series Table 15-1 Pin States during Reset and After Reset State Is Released Pin name I/O During reset Output Hi-Z Hi-Z Input Hi-Z Hi-Z (input port) P30/RxD-P37/TO3 I/O Hi-Z Hi-Z (input port mode) P40/AD0-P47/AD7 I/O Hi-Z Hi-Z (input port mode)Note P50/A8-P57/A15 I/O Hi-Z Hi-Z (input port mode)Note P60/A16-P63/A19 Output Hi-Z 0 P64/RD, P65/WR I/O Hi-Z Hi-Z (input port mode)Note P66/WAIT/AN6, P67/REFRQ/AN7 I/O Hi-Z Hi-Z (input port mode) Input Hi-Z Hi-Z (input
Chapter 15 Reset Function Table 15-2 Hardware States after Reset (1/2) Hardware State after reset Program counter (PC) The contents of the reset vector table (0000H and 0001H) are set.
µPD78214 Sub-Series Table 15-2 Hardware States after Reset (2/2) Hardware Serial Mode register (CSIM) interface Shift register (SIO) 00H Undefined Asynchronous mode register (ASIM) 80H Asynchronous status register (ASIS) 00H Serial bus control register (SBIC) 00H Serial reception buffer (RXB) Undefined Serial transmission buffer (TXS) Undefined Baud rate generator control register (BRGC) 00H Real-time output port control register (RTPC) 00H Programmable wait control register (PW) 80H Refr
Chapter 15 Reset Function Fig. 15-3 Timing Charts for Reset Operation (a) For µPD78213 ★ RESET (input) Hi-Z ASTB (output) A8-A19 (output) AD0-AD7 RD (output) WR output Hi-Z Hi-Z Address (output) Program (input) Hi-Z Hi-Z Hi-Z Other I/O ports Reset period Instruction execution period after reset (b) For µPD78214 15 RESET (input) Hi-Z ASTB (output) P60-P63 (output) Hi-Z Hi-Z Other I/O ports Reset period Instruction execution period after reset 15.
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CHAPTER 16 APPLICATION EXAMPLES 16.1 OPEN-LOOP CONTROL OF STEPPER MOTORS This section provides an example of controlling stepper motors with the real-time output function, 8-bit timer/ counter 1, and the macro service function of the µPD78214. Fig. 16-1 shows the functional blocks for controlling two stepper motors. An interrupt signal is generated when the value in 8-bit timer/counter 1 (TM1) is matched with the value in compare register CR10 or CR11.
396 fCLK/16 fCLK/32 fCLK/64 fCLK/128 fCLK/256 fCLK/512 Prescaler mode register Multiplexer Internal bus Compare register CR11 Match detection interrupt INTC11 8-bit timer 1 TM1 Match detection interrupt INTC10 Compare register CR10 Internal bus Buffer register P0H Buffer register P0L Real-time output port (higher) Output latch Output latch Real-time output port (lower) Fig.
Chapter 16 Application Examples 16.2 SERIAL COMMUNICATION WITH MULTIPLE DEVICES Fig. 16-2 shows an example of a system configured with a serial bus interface. The serial bus interface can transfer addresses (for selecting devices), commands, and data, as well as acknowledge and busy signals, using only two lines: The serial clock and serial bus lines. When a master device communicates with multiple slave devices, the master device outputs an address for selecting a slave device on the serial bus line.
µPD78214 Sub-Series Fig. 16-3 Example of Communication with SBI SB0 Address Command Command SB0 Address Command Data SB0 Address Command Data SB0 Address Data Data Data SB0 Address Data Data Data Command Data Command : Bus release : Command trigger Fig.
CHAPTER 17 PROGRAMMING FOR THE µPD78P214 The µPD78P214 employs an electrically writable PROM of 16384 × 8 bits for program memory. Use the NMI and RESET pins to set the µPD78P214 to PROM programming mode when programming the PROM. The µPD78P214 provides programming characteristics compatible with the µPD27C256ANote. ★ Note 100 µs program pulses are not supported. 17.1 OPERATING MODE When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the µPD78P214 enters PROM programming mode.
µPD78214 Sub-Series Fig. 17-1 Timing Chart for PROM Write and Verify Repetition of X times Write A0-A14 Additional write Address input Hi-Z D0-D7 Verify Data input Hi-Z Hi-Z Data output Data input +12.
Chapter 17 Programming for The µPD78214 Fig. 17-2 Write Operation Flowchart Start writing (1) (2) Apply power supply voltage (3) Set an initial address (4) Input write data (5) Input a program pulse (6) Write failure (up to 24th) Verify mode Write failure (25th) Write success (8) Additional write (3X ms pulse) (9) Increment the address X: Number of times writing is repeated (10) < Last address 17 Last address > Last address Write completes (7) Defective device 17.
µPD78214 Sub-Series Fig. 17-3 PROM Read Timing Chart Address input A0-A14 CE (input) OE (input) D0-D7 Hi-Z Data output Hi-Z 17.4 NOTE When VPP is +12.5 V and VDD is +6 V, CE and OE must not be set to low at the same time.
CHAPTER 18 INSTRUCTION OPERATIONS This chapter describes the operation of each instruction of the µPD78214 sub-series. Refer to the 78K/II Series User’s Manual, Instructions (IEU-1311) for details of each operation, the corresponding machine language code (instruction code), and the number of clock states for each instruction. 18.1 LEGEND 18.1.
µPD78214 Sub-Series saddr, saddr’ : Memory address indicated in short direct addressing mode; FE20H-FF1FH immediate data or label saddrp : Memory address indicated in short direct addressing pair mode; FE20H-FF1EH immediate data or label addr16 : 16-bit address; 0000H-FEFFH immediate data or label addr11 : 11-bit address; 800H-FFFH immediate data or label addr5 : 5-bit address; 40H-7EH immediate data or label word : 16-bit data; 16-bit immediate data or label byte : 8-bit data; 8-bit immediate d
Chapter 18 Instruction Operations Z : Zero flag RBS1-RBS0 : Register bank selection flag IE : Interrupt request enable flag STBC : Standby control register jdisp8 : Signed 8-bit data (displacement: –128 to +127) () : Contents at address enclosed in parentheses or at address indicated in register enclosed in parentheses ××H : Hexadecimal number ×H, ×L : Eight high-order bits and eight low-order bits of 16-bit register pair 18.1.3 Flag Field Blank : No change 0 : Cleared to zero.
µPD78214 Sub-Series 18.2 LIST OF OPERATIONS (1) 8-bit data transfer instructions: MOV, XCH Mnemonic MOV XCH 406 Operand Flags No.
Chapter 18 Instruction Operations (2) 16-bit data transfer instructions: MOVW Mnemonic MOVW Operand Flags No.
µPD78214 Sub-Series Operand Mnemonic SUB SUBC AND OR Flags No.
Chapter 18 Instruction Operations Operand Mnemonic XOR CMP Flags No.
µPD78214 Sub-Series (5) Multiply/divide instructions: MULU, DIVUW Mnemonic Operand Flags No. of bytes Operation MULU r 2 AX ← A × r1 DIVUW r 2 AX (quotient), r (remainder) ← AX ÷ r When r = 0, r ← X, AX ← 0FFFFH Z AC CY (6) Increment/decrement instructions: INC, DEC, INCW, DECW Operand Mnemonic Flags No.
Chapter 18 Instruction Operations (8) BCD conversion instructions: ADJBA, ADJBS Flags No. of bytes Operation ADJBA 1 ADJBS 1 Mnemonic Operand Z AC CY Use the decimal adjust accumulator after addition. × × × Use the decimal adjust accumulator after subtraction. × × × (9) Bit manipulation instructions: MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1 Mnemonic MOV1 AND1 OR1 Operand Flags No. of bytes Operation Z AC CY CY, saddr.bit 3 CY ← (saddr.bit) × CY, sfr.bit 3 CY ← sfr.
µPD78214 Sub-Series Operand Mnemonic XOR1 SET1 CLR1 NOT1 412 Flags No. of bytes Operation Z AC CY CY, saddr.bit 3 CY ← CY ∨ (saddr.bit) × CY, sfr.bit 3 CY ← CY ∨ sfr.bit × CY, A.bit 2 CY ← CY ∨ A.bit × CY, X.bit 2 CY ← CY ∨ X.bit × CY, PSW.bit 2 CY ← CY ∨ PSW.bit × saddr.bit 2 (saddr.bit) ← 1 sfr.bit 3 sfr.bit ← 1 A.bit 2 A.bit ← 1 X.bit 2 X.bit ← 1 PSW.bit 2 PSW.bit ← 1 CY 1 CY ← 1 saddr.bit 2 (saddr.bit) ← 0 sfr.bit 3 sfr.bit ← 0 A.bit 2 A.
Chapter 18 Instruction Operations (10) Call/return instructions: CALL, CALLF, CALLT, BRK, RET, RETI, RETB Mnemonic Operand Flags No.
µPD78214 Sub-Series (13) Conditional branch instructions: BC, BL, BNC, BNL, BZ, BE, BNZ, BNE, BT, BF, BTCLR, DBNZ Mnemonic BC Operand No. of bytes Flags Operation $ addr16 2 PC ← PC + 2 + jdisp8 if CY = 1 addr16 2 PC ← PC + 2 + jdisp8 if CY = 0 $ addr16 2 PC ← PC + 2 + jdisp8 if Z = 1 $ addr16 2 PC ← PC + 2 + jdisp8 if Z = 0 saddr.bit, $ addr16 3 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $ addr16 4 PC ← PC + 4 + jdisp8 if sfr.bit = 1 A.
Chapter 18 Instruction Operations (14) CPU control instructions: MOV, SEL, NOP, EI, DI Mnemonic Operand Flags No.
µPD78214 Sub-Series 18.
Chapter 18 Instruction Operations (2) 16-bit instructions MOVW, ADDW, SUBW, CMPW, INCW, DECW, SHRW, and SHLW Table 18-2 16-Bit Instructions for Each Addressing Type Second operand First operand AX # word AX ADDW SUBW CMPW rp rp' saddrp sfr mem1 & mem1 SP ADDW SUBW CMPW MOVW ADDW SUBW CMPW MOVW ADDW SUBW CMPW MOVW MOVW MOVW n None SHLW SHRW DECW INCW PUSH POP rp MOVW MOVW saddrp MOVW MOVW sfrp MOVW MOVW mem1 & mem1 SP MOVW MOVW MOVW DECW INCW 18 417
µPD78214 Sub-Series (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, and BTCLR Table 18-3 Bit Manipulation Instructions for Each Addressing Type Second operand First operand CY CY A. bit /A. bit X. bit /X. bit MOV1 AND1 OR1 XOR1 AND1 OR1 MOV1 AND1 OR1 XOR1 AND1 OR1 saddr. bit /saddr. bit MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 /sfr. bit PSW. bit /PSW.
Chapter 18 Instruction Operations (4) Call instructions and branch instructions ★ CALL, CALLF, CALLT, BR, BC, BT, BF, BTCLR, DBNZ, BL, BNC, BNL, BZ, BE, BNZ, and BNE Table 18-4 Call Instructions and Branch Instructions for Each Addressing Type Instruction addressing operand $addr16 !addr16 rp !addr11 [addr5] Basic instruction BR BCNote CALL BR CALL BR MOV1 MOV1 Composite instruction BT BF BTCLR DBNZ Note BL, BNC, BNL, BZ, BF, BNZ, and BNE are the same as BC.
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APPENDIX A 78K/II SERIES PRODUCT LIST The following pages list the 78K/II series products. For details, refer to each User’s Manual.
µPD78214 Sub-Series µPD78214 Sub-Series Series name Product name Item µPD78212 PUSH PSW instruction execution time (number of clocks) Operating temperature and voltage ranges µPD78214 µPD78218A µPD78217A (µPD78P214) (µPD78P218A) µPD78213 333 ns 500 ns 333 ns 500 ns When the stack area is configured in the internal dual-port RAM: 5 or 7 Other cases: 7 or 9 When the stack area is configured in the internal dual-port RAM: 6 Other cases: 8 : –40 to +85˚C, VDD = +5 V ±0.
Appendix A 78K/II Series Product List (1/3) µPD78234 Sub-Series µPD78233 µPD78234 µPD78244 Sub-Series µPD78238 (µPD78P238) µPD78237 µPD78243 µPD78244 65 (instructions common to all 78K/II series products) 500 ns 333 ns 500 ns 333 ns 500 ns 333 ns When the stack area is configured in the internal dual-port RAM: 6 Other cases: 8 –10 to +70˚C, VDD = +5 V ±10% –40 to +85˚C, VDD = +5 V ±10% 8 bits × 8 × 4 banks P6 and PM6 None 16K 32K (32/16KNote) None None 512 None 640 16K 1024K 1024 5
µPD78214 Sub-Series Series name Product name Item µPD78214 Sub-Series µPD78212 µPD78213 µPD78218A Sub-Series µPD78214 µPD78218A µPD78217A (µPD78P214) (µPD78P218A) None 4 bits × 8 8 bits × 8 None Selected according to operating frequency — Comparator A/D converter AVREF input voltage range Restrictions on input voltage 3.4 V to VDD 3.6 V to VDD Pins selected by bits ANI0 to ANI2 of Pins subject to A/D the ADM register. Pin voltage is conversion. Pin voltage always 0 V to AVREF.
Appendix A 78K/II Series Product List (2/3) µPD78234 Sub-Series µPD78233 µPD78234 µPD78244 Sub-Series µPD78238 (µPD78P238) µPD78237 µPD78243 12 bits × 2 µPD78244 None None 8 bits × 8 Selected freely Selected according to operating frequency 3.6 V to VDD 3.4 V to VDD Pins subject to A/D conversion. Pin voltage is 0 V to AVREF during A/D conversion.
µPD78214 Sub-Series Series name Product name Item µPD78214 Sub-Series µPD78212 µPD78213 µPD78214 µPD78218A µPD78217A (µPD78P214) (µPD78P218A) µPD78224 (µPD78P224) µPD78220 External 7 8 Internal 12 9 Interrupts that can use macro service 15 6 Bits of macro service counter 8 bits only Incrementing MPD and MPT of type C macro service Increments lower 8 bits only (higher bits remain as is) Constraints on memoryto-SFR data transfer by type A macro service Occurs when transferred data is D0H
Appendix A 78K/II Series Product List (3/3) µPD78234 Sub-Series µPD78233 µPD78234 µPD78244 Sub-Series µPD78238 (µPD78P238) µPD78237 µPD78243 µPD78244 2 levels (programmable), vector/macro service 7 12 14 15 8/16 bits selectable (except type A) Increments 16 bits Occurs when transfer source Occurs when transferred data is D0H to DFH buffer (memory) address is 0FED0H to 0FEDFH Depends on mode. Refer to the relevant user's manual.
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APPENDIX B DEVELOPMENT TOOLS The development tools described on the following pages are available for the development of systems using µPD78214 sub-series.
430 Notes 1. 2. 3. 4. 5.
Appendix B Development Tools B.1 HARDWARE (1/2) IE-78240-R-A The IE-78240-R-A is an enhanced version of the IE-78210-R and IE-78240-R. This in-circuit emulator can be used for any model of the µPD78214 sub-series. It operates with a PC-9800 series or IBM PC/AT host machine. By using this emulator together with the optional screen debugger and device file, programs written in C or a structured assembly language can be debugged at the source program level.
µPD78214 Sub-Series HARDWARE (2/2) EV-9200G-74 This socket is mounted on the board of the user system developed for the 74pin QFP. It is used together with the EP-78210GJ or EP-78240GJ-R. EV-9200GC-64 This socket is mounted on the board of the user system developed for the 64pin QFP. It is used together with the EP-78210GC or EP-78240GC-R.
Appendix B Development Tools B.2 SOFTWARE B.2.1 Language Processing Software (1/3) 78K/II series relocatable assembler (RA78K/II) This relocatable assembler can be used for all the 78K/II series products. Its macro functions enhance efficiency in software development. It also includes a structured assembler, which makes the program control structure more comprehensive, thus improving software productivity and maintainability.
µPD78214 Sub-Series Language Processing Software (2/3) 78K/II series relocatable assembler (RA78K/II) Host machine 8-inch MS-DOSTM (Ver.3.30 to Ver.5.00ANote 3) PC-9800 series ★ Distribution medium OS 2DNote1 HP9000 See Section B.2.4. series300TM SPARCstationTM EWS-4800 78K/II series C compiler (CC78K/II) seriesTM Sun (RISC) µS5A10RA78K2 3.5-inch 2HD µS5A13RA78K2 2DNote2 5.25-inch 2HC µS7B10RA78K2 3.5-inch 2HC µS7B13RA78K2 (rel.7.05B) OSTM (rel.4.1.
Appendix B Development Tools Language Processing Software (3/3) 78K/II series C compiler library source file This source program is used to modify the libraries supplied with CC78K/II to satisfy user specifications. Host machine PC-9800 series Note OS MS-DOS (Ver.3.30 to Ver.5.00ANote) IBM PC/AT or compatible See Section B.2.4. HP9000 series300 HP-UX (rel.7.05B) SPARCstation Sun OS (rel.4.1.1) EWS-4800 series (RISC) EWS-UX/V (rel.4.0) Distribution medium Part number 5.
µPD78214 Sub-Series Software for the In-Circuit Emulator (2/2) In-circuit emulator control program ( IE78210 IE78240 ) Note 1 This program enables control of the in-circuit emulator for the 78K/II series from the host machine. It can automatically execute commands, thus enhancing efficiency in debugging. The following programs are available, depending on the type of in-circuit emulator: Emulator Host machine OS IE-78210-R IE-78210-R-EM Distribution medium 8-inch 2DNote 3 µS5A1IE78210-P01 5.
Appendix B Development Tools B.2.3 Software for the PROM Programmer PG-1500 controller This program provides the serial and parallel interfaces between PG-1500 and the host machine, enabling the host machine to control the PG-1500. Host machine PC-9800 series OS MS-DOS (Ver.3.10 to Ver.5.00ANote 1) Distribution medium 5-inch 2HD µS5A10PG1500 3.5-inch 2HD µS5A13PG1500 5-inch IBM PC/AT or compatible See Section B.2.4. Part number 2DNote 2 µS7B11PG1500 5-inch 2HC µS7B10PG1500 3.
µPD78214 Sub-Series B.3 UPGRADING OTHER IN-CIRCUIT EMULATORS TO 78K/II SERIES LEVEL The 78K series and 75X series in-circuit emulators can be upgraded to the level of the 78K/II series by replacing their internal boards with an optional board. Note that the upgraded in-circuit emulator requires an appropriate new control program. B.3.
Appendix B Development Tools B.3.2 Upgrading to IE-78240-R LevelNote 1 (Upgrading to IE-78240-R-A Level is recommended.) Emulator IE Group Number Required Board IE-78112-RNote 1 IE-78210-RNote 1 IE-78220-RNote 1 IE-78130-R IE-78230-RNote 1 1 IE-78240-R-EMNote 2 2 IE-78240-R-EM IE-78310-RNote 1 IE-78310A-R 3 IE-78200-R-EMNote 1 IE-78240-R-EMNote 2 Remarks The high-speed download function is not supported.
µPD78214 Sub-Series B.3.3 Upgrading to IE-78210-R LevelNote 2 (Upgrading to IE-78240-R-A level is recommended.
APPENDIX C SOFTWARE FOR EMBEDDED APPLICATIONS ★ C.1 FUZZY INFERENCE DEVELOPMENT SUPPORT SYSTEM Fuzzy knowledge-data creation tool Supports input and editing, as well as the evaluation (simulation) of fuzzy knowledge-data (fuzzy rules and membership functions). Host machine PC-9800 series IBM PC/AT or compatible Translator PC-9800 series IBM PC/AT or compatible PC-9800 series IBM PC/AT or compatible 5.25-inch 2HD µS5A10FE9000 3.5-inch 2HD µS5A13FE9000 5.25-inch 2HC µS7B10FE9200 3.
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APPENDIX D REGISTER INDEX D.1 REGISTER INDEX 16-bit capture register (CR02) ... 111 16-bit compare register (CR00,CR01) ... 111 16-bit timer 0 (TM0) ... 111 8-bit capture/compare register (CR11) ... 142 8-bit capture register (CR22) ... 161 8-bit compare register (CR10) ... 142 8-bit compare register (CR20) ... 161 8-bit compare register (CR21) ... 161 8-bit compare register (CR30) ... 206 8-bit timer 1 (TM1) ... 142 8-bit timer 2 (TM2) ... 161 8-bit timer 3 (TM3) ...
µPD78214 Sub-Series Port 3 (P3) ... 66 Port 4 (P4) ... 75 Port 5 (P5) ... 80 Port 6 (P6) ... 84 Port 7 (P7) ... 92 Port 0 buffer register (P0L, P0H) ... 97 Port 0 mode register (PM0) ... 61 Port 3 mode control register (PMC3) ... 72 Port 3 mode register (PM3) ... 72 Port 5 mode register (PM5) ... 80 Port 6 mode register (PM6) ... 89 Prescaler mode register 0 (PRM0) ... 207 Prescaler mode register 1 (PRM1) ... 143, 164 Priority specification flag register (PR0) ...
Appendix D Register Index D.2 REGISTER SYMBOL INDEX A ADCR: A/D conversion result register ... 227 ADM: A/D converter mode register ... 229, 304 ASIM: Asynchronous serial interface mode register ... 245 ASIS: Asynchronous serial interface status register ... 246 B BRGC: Baud rate generator control register ... 251 C CR00: 16-bit compare register ... 111 CR01: 16-bit compare register ... 111 CR02: 16-bit capture register ... 111 CR10: 8-bit compare register ...
µPD78214 Sub-Series PM0: Port 0 mode register ... 61 PM3: Port 3 mode register ... 72 PM5: Port 5 mode register ... 80 PM6: Port 6 mode register ... 89 PMC3: Port 3 mode control register ... 72 PR0: Priority specification flag register ... 306 PRM0: Prescaler mode register 0 ... 207 PRM1: Prescaler mode register 1 ... 143, 164 PUO: Pull-up-resistor-option register ... 65, 74, 78, 82, 91 PW: Programmable wait control register ... 347 R RFM: Refresh mode register ...
APPENDIX E INDEX E.1 INDEX 0 parity ... 247, 248 B 16-bit timer 0 ... 111, 114 Bank register ... 43 16-bit timer/counter ... 109 Basic operation ... 121 1M-byte expansion function ... 348 Baud rate ... 251, 254 4-bit counter ... 251 Baud rate generator ... 243, 251 4-bit separate real-time output port ... 97 Baud rate generator control register ... 251 64-pin ceramic shrink DIP with window ... 6 Baud rate generator for UART ... 243 64-pin plastic QFP ... 8 Baud rate setting ...
µPD78214 Sub-Series Clock synchronous serial interface mode register ... 262, 273 External memory expansion mode ... 346 Command ... 279 External SFR area ... 43 Command detection flag ... 274 External trigger ... 118, 149, 177 Command signal ... 278 F Command trigger bit ... 274 Framing error ... 249 Compare operation ... 117, 148, 176, 210 Frequency divider ... 251, 253 Compare register ... 111, 161, 142, 148, 206 Full-count ... 175 Controlling multiple-interrupt handling ...
Appendix E Index Interrupt status register ... 304, 307 Multiplexed analog ... 225 Interval timer ... 129, 151, 190, 192, 210, 211 N Interval ... 109, 139, 159, 205 Noise elimination ... 296 L Noise eliminator ... 389 Local bus interface function ... 345 Nonmaskable interrupt ... 308 Loop counter ... 49 Nonmaskable interrupt request ... 303, 307 M Number of I/O ports ... 60 Macro service ... 301, 319 Number of wait states ... 346 Macro service channel ...
µPD78214 Sub-Series Port 3 mode control register ... 72 Refresh mode register ... 367 Port 3 mode register ... 71 Refresh pulse ... 367 Port 4 ... 75 Register bank selection flag ... 46 Port 5 ... 80 Register ... 45 Port 5 mode register ... 80 Release detection flag ... 274 Port 6 ... 84 Release trigger bit ... 274 Port 6 mode register ... 89 Releasing the busy state ... 287 Port 7 ... 92 Reset ... 389 Port mode ... 346, 367 Reset function ... 389 Prescaler ...
Appendix E Index Special function register ... 43, 50 Wake up ... 269, 287 Specifying 1M-byte expansion mode ... 346 Wake-up function ... 269 Specifying the operation of the capture/compare register ... 144 Write timing ... 348 Stack pointer ... 46 Z Standby control register ... 379 Zero flag ... 46 Standby function ... 377 Standby mode ... 377 Start bit ... 247 Stop bit ... 247 Sub-data bank ... 44 Successive approximation ... 225 System clock ... 55 System reset ...
µPD78214 Sub-Series E.2 SYMBOL INDEX A ADCR ... 225, 227 A ... 48 ADM ... 228, 304 A0 ... 31 ALV0 ... 113 A1 ... 31 ALV1 ... 113 A2 ... 31 ALV2 ... 166 A3 ... 31 ALV3 ... 166 A4 ... 31 AN0 ... 225 A5 ... 31 AN1 ... 225 A6 ... 31 AN2 ... 225 A7 ... 31 AN3 ... 225 A8 ... 29, 31, 345 AN4 ... 225 A9 ... 29, 31, 345 AN5 ... 225 A10 ... 29, 31, 345 AN6 ... 30, 225, 239 A11 ... 29, 31, 345 AN7 ... 30, 225, 239 A12 ... 29, 31, 345 ANI0 ... 229 A13 ... 29, 31, 345 ANI1 ... 229 A14 ..
Appendix E Index CE2 ... 163, 167 CR00 ... 111, 117 CE3 ... 207, 208 CR01 ... 111, 117 CHT0 ... 323 CR02 ... 111, 118 CHT1 ... 323 CR10 ... 142, 148 CHT2 ... 323 CR11 ... 142, 148 CI ... 28, 161, 170 CR20 ... 161, 176 CIF00 ... 305 CR21 ... 161, 176 CIF01 ... 305 CR22 ... 161, 177 CIF10 ... 305 CR30 ... 206, 210 CIF11 ... 305 CRC0 ... 112, 119 CIF20 ... 305 CRC1 ... 144 CIF21 ... 305 CRC2 ... 165, 179 CISM00 ... 306 CRXE ... 262, 273 CISM01 ... 306 CS ... 229, 304 CISM10 ...
µPD78214 Sub-Series ES00 ... 294 INTP0 ... 28, 99, 149, 294, 302 ES01 ... 294 INTP1 ... 28, 177, 294, 302 ES10 ... 294 INTP2 ... 28, 161, 294, 302 ES11 ... 294 INTP3 ... 28, 118, 295, 302 ES20 ... 294 INTP4 ... 28, 295, 302, 303 ES21 ... 294 INTP5 ... 28, 225, 239, 295, 302, 303, 304 ES30 ... 295 INTSER ... 249, 302 ES31 ... 295 INTSR ... 249, 302 ES40 ... 295, 303 INTST ... 248, 302 ES41 ... 295, 303 IRAM ... 43 ES50 ... 295 ISM0 ... 304, 306 ES51 ... 295 ISM0H ... 306 ESNMI ...
Appendix E Index µPD78210 ... 20 PISM4 ... 306 µPD78212 ... 1 PISM5 ... 306 µPD78213 ... 1 PM0 ... 61 µPD78214 ... 1 PM3 ... 72 µPD78p214 ... 1, 399 PM5 ... 81 N PM6 ... 89 NC ... 31, 32 PMC3 ... 72 NMI ... 428, 302, 303 PMK0 ... 306 NMIS ... 307 PMK1 ... 306 O PMK2 ... 306 OE ... 31 PMK3 ... 306 OVE ... 247 PMK4 ... 306 OVF0 ... 112 PMK5 ... 306 OVF1 ... 143 Port 0 ... 60 OVF2 ... 163 Port 2 ... 63 P Port 3 ... 66 P0H ... 97 Port 4 ... 75 P0L ... 97 Port 5 ... 80 P0HM .
µPD78214 Sub-Series PRS2 ... 207 RELD ... 280 PRS3 ... 207 Releasing HALT mode ... 485 PRS10 ... 144 Releasing STOP mode ... 382 PRS11 ... 144 RELT ... 280 PRS12 ... 144 RESET ... 31, 389 PRS20 ... 164 RETB ... 308 PRS21 ... 164 RETB instruction ... 308 PRS22 ... 164 RETI ... 308 PRS23 ... 164 RETI instruction ... 308 PS0 ... 246 RFEN ... 367 PS1 ... 246 RFLV ... 367 PSW ... 45, 304, 308 RFM ... 367 PUO ... 65, 74, 78, 82, 91 RFT0 ... 367 PUO2 ... 65 RFT1 ... 367 PUO3 ...
Appendix E Index SO ... 29, 265 WUP ... 262, 273 SO pin ... 267 X SO latch ... 261 X ... 48 SP ... 46 X1 ... 31, 55 Specifying HALT mode ... 379 X2 ... 31, 55 Specifying STOP mode ... 382 Z SRIF ... 305 Z ... 46, 308 SRISM ... 306 SRMK ... 306 SRPR ... 307 STBC ... 379 STIF ... 305 STISM ... 306 STMK ... 306 STOP mode ... 377, 382 STP ... 379 STPR ... 307 T TM0 ... 111, 114 TM1 ... 142, 145 TM2 ... 161, 167 TM3 ... 206, 208 TMC0 ... 111, 207 TMC1 ... 143, 163 TO0 ... 29, 119 TO1 ...
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