Single-Chip Microcontrollers User's Manual

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User’s Manual

Printed in Japan

PD754144, 754244

4-Bit Single-Chip Microcontrollers

PD754144

PD754244

Document No. U10676EJ3V0UM00 (3rd edition)

Date Published November 2002 N CP(K)

1997

Summary of content (306 pages)

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User’s Manual µ PD754144, 754244 4-Bit Single-Chip Microcontrollers µPD754144 µPD754244 Document No.
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[MEMO] 2 User’s Manual U10676EJ3V0UM
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity.
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These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of July, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products.
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors.
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Major Revisions in This Edition Pages Description p.210 Correction of description in figure in 7.9 Application of Interrupt (6) Executing pending interrupt - interrupt occurs during interrupt service (INTBT has higher priority and INTT0 and INTT2 have lower priority) p.253 Correction of instruction code of “BR BCDE” in 11.3 Opcode of Each Instruction p.296 Deletion of flash-related products in configuration diagram in APPENDIX A DEVELOPMENT TOOLS p.
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INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the µPD754144 and 754244 and design application systems using these microcontrollers. Purpose This manual is intended to give users an understanding of the hardware functions of the µPD754144 and 754244 described in the Organization below. Organization This manual contains the following information.
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to devices Document Name µ PD754144, 754244 Data Sheet Document No. U10040E µ PD754144, 754244 User’s Manual This manual 75XL Series Selection Guide U10453E Documents related to development tools (software) (user’s manuals) Document Name RA75X Assembler Package Document No.
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TABLE OF CONTENTS CHAPTER 1 GENERAL ..................................................................................................................... 1.1 Functional Outline ............................................................................................................. 1.2 Ordering Information ......................................................................................................... 1.3 Differences Between Series Products .....................................................
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4.6 4.7 4.8 4.9 Accumulator ........................................................................................................................ Stack Pointer (SP) and Stack Bank Select Register (SBS) .......................................... Program Status Word (PSW) ............................................................................................. Bank Select Register (BS) ................................................................................................
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS ........................................................................ 7.1 Configuration of Interrupt Controller .............................................................................. 7.2 Types of Interrupt Sources and Vector Table ................................................................. 7.3 Hardware Controlling Interrupt Function ....................................................................... 7.4 Interrupt Sequence ..........................
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11.4.10 Branch instructions ................................................................................................................ 279 11.4.11 Subroutine/stack control instructions .................................................................................... 283 11.4.12 Interrupt control instructions .................................................................................................. 287 11.4.13 Input/output instructions ..................................................
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LIST OF FIGURES (1/3) Figure No. Title Page 3-1 Selecting MBE = 0 Mode and MBE = 1 Mode .................................................................................. 33 3-2 Data Memory Configuration and Addressing Range for Each Addressing Mode ............................ 35 3-3 Updating Address of Static RAM ....................................................................................................... 39 3-4 Example of Using Register Banks ......................................
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LIST OF FIGURES (2/3) Figure No. 14 Title Page 6-18 Example of Incorrect Resonator Connection ..................................................................................... 109 6-19 CPU Clock Switching Example .......................................................................................................... 113 6-20 Block Diagram of Basic Interval Timer/Watchdog Timer ...................................................................
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LIST OF FIGURES (3/3) Figure No. Title Page 7-9 Interrupt Nesting by Changing Interrupt Status Flag ........................................................................ 7-10 Block Diagram of KR4 to KR7 ............................................................................................................ 213 7-11 Format of INT2 Edge Detection Mode Register (IM2) ...................................................................... 214 8-1 Releasing Standby Mode .......................
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LIST OF TABLES Table No. 16 Title Page 2-1 Pin Functions of Digital I/O Ports ....................................................................................................... 2-2 Functions of Non-Port Pins ................................................................................................................ 25 2-3 Recommended Connection of Unused Pins ...................................................................................... 31 3-1 Addressing Modes ................
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CHAPTER 1 GENERAL The µPD754144 and 754244 are 4-bit single-chip microcontrollers in the NEC 75XL Series, the successor to the 75X Series that boasts a wealth of variations. The µPD754144 and 754244 have extended CPU functions compared to the µPD75048, a 75X Series product with on-chip EEPROM, enabling high-speed and low voltage (1.8 V) operation. This model is available in a small plastic SSOP (7.62 mm (300)). The features of the µPD754144 are as follows: • Low-voltage operation: VDD = 1.8 to 6.
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CHAPTER 1 GENERAL 1.1 Functional Outline µPD754144 Item Instruction execution time • 4, 8, 16, 64 µs (at f CC = 1.0 MHz) On-chip Mask ROM 4096 × 8 bits (0000H to 0FFFH) memory RAM 128 × 4 bits (000H to 07FH) EEPROM 16 × 8 bits (400H to 41FH) µPD754244 • 0.95, (at fX • 0.67, (at fX 1.91, 3.81, 15.3 µs = 4.19 MHz) 1.33, 2.67, 10.7 µs = 6.
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CHAPTER 1 GENERAL 1.2 Ordering Information Part Number Package µPD754141GS-×××-BA5 20-pin plastic SOP (7.62 mm (300)) µPD754141GS-×××-GJG 20-pin plastic SSOP (7.62 mm (300)) µPD754244GS-×××-BA5 20-pin plastic SOP (7.62 mm (300)) µPD754244GS-×××-GJG 20-pin plastic SSOP (7.62 mm (300)) Remark ××× indicates ROM code suffix. 1.3 Differences Between Series Products µPD754144 Item Instruction execution time 4, 8, 16, 64 µs (at fCC = 1.0 MHz) µPD754244 • 0.95, 1.91, 3.81, 15.3 µs (at fX = 4.
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CHAPTER 1 GENERAL 1.4 Block Diagram Basic interval timer/watchdog timer Port 3 4 P30 to P33 Port 6 4 P60 to P63 Port 7 4 P70 to P73 Port 8 P80 SP (8) INTBT RESET CY ALU 8-bit timer counter #0 PTO0/P30 INTT0 TOUT SBS Program counter INTT1 8-bit timer counter #1 PTO1/P31 8-bit timer counter #2 PTO2/P32 Cascaded 16-bit timer counter Bank General reg. Program memory (ROM) 4096 × 8 bits INTT2 Data memory (RAM) 128 × 4 bits EEPROM 16 × 8 bits INT0/P61 Bit seq.
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CHAPTER 1 GENERAL 1.5 Pin Configuration (Top View) • Pin configuration of µ PD754144 • 20-pin plastic SOP (7.62 mm (300)) µPD754144GS-×××-BA5 • 20-pin plastic SSOP (7.62 mm (300)) µPD754144GS-×××-GJG RESET 1 20 KRREN CL1 2 19 P80 CL2 3 18 P30/PTO0 VSS 4 17 P31/PTO1 IC 5 16 P32/PTO2 VDD 6 15 P33 P60/AVREF 7 14 P70/KR4 P61/INT0 8 13 P71/KR5 P62/PTH00 9 12 P72/KR6 P63/PTH01 10 11 P73/KR7 IC: Internally Connected (Directly connect to VDD.
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CHAPTER 1 GENERAL • Pin configuration of µ PD754244 • 20-pin plastic SOP (7.62 mm (300)) µPD754244GS-×××-BA5 • 20-pin plastic SSOP (7.62 mm (300)) µPD754244GS-×××-GJG RESET 1 20 KRREN X1 2 19 P80 X2 3 18 P30/PTO0 VSS 4 17 P31/PTO1 IC 5 16 P32/PTO2 VDD 6 15 P33 P60/AVREF 7 14 P70/KR4 P61/INT0 8 13 P71/KR5 P62/PTH00 9 12 P72/KR6 P63/PTH01 10 11 P73/KR7 IC: Internally Connected (Directly connect to VDD.
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CHAPTER 1 GENERAL Pin Name P30 to P33: Port 3 P60 to P63: Port 6 P70 to P73: Port 7 P80: Port 8 KR4 to KR7: Key return 4 to 7 INT0: External vectored interrupt 0 PTH00, PTH01: Programmable threshold port analog input 0, 1 PTO0 to PTO2: Programmable timer output 0 to 2 KRREN: Key return reset enable CL1, CL2: RC oscillator X1, X2: Crystal/ceramic oscillator IC: Internally connected RESET: Reset AVREF: Analog reference VSS: Ground VDD: Positive power supply User’s Manual U10676EJ
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CHAPTER 2 PIN FUNCTIONS 2.1 Pin Functions of µPD754244 Table 2-1. Pin Functions of Digital I/O Ports Pin Name P30 I/O Alternate Function I/O PTO0 P31 PTO1 P32 PTO2 P33 – 8-Bit I/O After Reset I/O Circuit Type Note 1 Programmable 4-bit I/O port (Port 3). Input/output can be specified in 1-bit units. On-chip pull-up resistor can be specified by software in 4-bit units. × Input E-B × Input F -A 4-bit input port (Port 7). A pull-up resistor can be incorporated (mask option).
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CHAPTER 2 PIN FUNCTIONS Table 2-2. Functions of Non-Port Pins Pin Name PTO0 I/O Alternate Function Output P30 PTO1 P31 PTO2 P32 INT0 Input P61 KR4 to KR7 Input P70 to P73 PTH00 Input P62 PTH01 After Reset I/O Circuit TypeNote Timer counter output pins. Input E-B Edge-detected vectored interrupt input Noise (edge to be detected is selectable). eliminator/ asynchronous Noise eliminator is selectable. selectable Input F -A Falling edge-detected testable input.
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CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P30 to P33 (Port 3) ... I/O pins shared with PTO0 to PTO2 P60 to P63 (Port 6) ... I/O pins shared with AVREF, INT0, PTH00, PTH01 P80 (Port 8) ... I/O pin These are 4-bit I/O ports with output latches (ports 3 and 6) and a 1-bit I/O port with an output latch (port 8). Ports 3 and 6 also have the following functions, in addition to the I/O port function.
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CHAPTER 2 PIN FUNCTIONS 2.2.4 INT0 ... input pin shared with port 6 This pin inputs the vectored interrupt signal detected by the edge. A noise eliminator is selectable for INT0. The edge to be detected can be specified by using the edge detection mode register (IM0).
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CHAPTER 2 PIN FUNCTIONS 2.2.8 AVREF ... input pin shared with port 6 This is a reference voltage input pin. An analog reference voltage for the programmable threshold port is input. 2.2.9 CL1 and CL2 (µPD754144 only) These pins are used to connect the RC oscillator resistor (R) and capacitor (C) of the system clock oscillator. No external clock can be input. RC oscillation µ PD754144 CL1 C R CL2 VSS 2.2.
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CHAPTER 2 PIN FUNCTIONS 2.2.12 IC The IC (Internally Connected) pin sets the test mode in which the µPD754244 is tested before shipment. Usually, you should directly connect the IC pin to the VDD pin with as short a wiring length as possible. If a voltage difference is generated between the IC and VDD pins because the wiring length is too long, or because external noise is superimposed on the IC pin, your program may not be correctly executed. • Directly connect the IC pin to the VDD pin.
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CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits The following diagrams show the I/O circuits of the pins of the µPD754244. Note that in these diagrams the I/ O circuits have been slightly simplified. Type A Type D VDD VDD Data P-ch OUT P-ch IN N-ch Output disable N-ch Push-pull output that can be placed in output high-impedance (both P-ch, N-ch off). CMOS specification input buffer. Type E-B Type B VDD P.U.R. P.U.R.
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CHAPTER 2 PIN FUNCTIONS 2.4 Processing of Unused Pins Table 2-3. Recommended Connection of Unused Pins Pin Recommended Connection P30/PTO0 Input: Independently connect to VSS or V DD via a resistor. P31/PTO1 Output: Leave open. P32/PTO2 P33 P60/AVREF P61/INT0 P62/PTH00 P63/PTH01 P70/KR4 Connect to VDD. P71/KR5 P72/KR6 P73/KR7 P80 Input: Independently connect to V SS or V DD via a resistor. Output: Leave open.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP The 75XL architecture employed for the µPD754244 has the following features. • Internal RAM: 4K words × 4 bits MAX. (12-bit address) • Expandability peripheral hardware To realize these superb features, the following techniques have been employed. (1) Bank configuration of data memory (2) Bank configuration of general-purpose registers (3) Memory mapped I/O This chapter describes these features. 3.1 Bank Configuration of Data Memory and Addressing Modes 3.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-1. Selecting MBE = 0 Mode and MBE = 1 Mode
SET 1 MBE MBE =1 CLR1 MBE MBE = 0 CLR 1 MBE Internal hardware and static RAM manipulation repeated.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 3.1.2 Addressing mode of data memory The 75XL architecture employed for the µPD754244 provides the seven types of addressing modes shown in Table 3-1. This means that the data memory space can be efficiently addressed by the bit length of the data to be processed and that programming can be carried out efficiently. (1) 1-bit direct addressing (mem.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-2. Data Memory Configuration and Addressing Range for Each Addressing Mode Addressing mode mem mem. bit @HL @H+mem. bit Memory bank enable flag MBE = 0 MBE = 1 MBE = 0 MBE = 1 000H Generalpurpose register area 01FH 020H MBS = 0 MBS = 0 MBS = 4 MBS = 4 MBS = 15 MBS = 15 @DE @DL – Stack addressing fmem. bit pmem.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Table 3-1. Addressing Modes Addressing Mode Representation Specified Address • When MBE = 0 When mem = 00H to 7FH: MB = 0 When mem = 80H to FFH: MB = 15 • When MBE = 1: 4-bit direct addressing mem MB = MBS Address specified by MB and mem.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (2) 4-bit direct addressing (mem) This addressing mode is used to directly address the entire memory space in 4-bit units by using the operand of an instruction. Like the 1-bit direct addressing mode, the area that can be addressed is fixed to the data area of addresses 000H to 07FH and the peripheral hardware area of F80H to FFFH in the mode of MBE = 0. In the mode of MBE = 1, MB = MBS, and the entire data memory space can be addressed.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Examples 1. To compare data 50H to 57H with data 60H to 67H DATA1 EQU 57H DATA2 EQU 67H SET1 MBE SEL MB0 MOV D, #DATA1 SHR 4 MOV HL, #DATA2 AND 0FFH LOOP : MOV A, @DL SKE A, @HL BR NO DECS L BR ; A = (HL)? ; NO ; YES, L ← L – 1 LOOP 2.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-3. Updating Address of Static RAM XFH X0H 0XH DECS D DECS L @DL 4-bit transfer DECS D DECS E INCS L DECS DE INCS D @DE 4-bit transfer INCS E INCS DE INCS D Direct addressing bit manipulation 4-bit transfer 8-bit transfer DECS H Auto decrement DECS L DECS HL @HL 4-bit manipulation 8-bit manipuIation DECS H Auto increment INCS L INCS HL INCS H @H+mem.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (5) 8-bit register indirect addressing (@HL) This addressing mode is used to indirectly address the entire data memory space in 8-bit units by using a data pointer (HL register pair).
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (6) Bit manipulation addressing This addressing mode is used to manipulate the entire memory space in bit units (such as Boolean processing and bit transfer). While the 1-bit direct addressing mode can only be used with the instructions that set, reset, or test a bit, this addressing mode can be used in various ways such as Boolean processing by the AND1, OR1, and XOR1 instructions, and test and reset by the SKTCLR instruction.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (b) Specific address bit register indirect addressing (pmem, @L) This addressing mode is to indirectly specify and successively manipulate the bits of the peripheral hardware units such as I/O ports. The data memory addresses to which this addressing mode can be applied are FC0H to FFFH. This addressing mode specifies the higher 10 bits of a 12-bit data memory address directly by using an operand, and the lower 2 bits by using the L register.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (c) Special 1-bit direct addressing (@H+mem.bit) This addressing mode enables bit manipulation in the entire memory space. The higher 4 bits of the data memory address of the memory bank specified by MBE and MBS are indirectly specified by the H register, and the lower 4 bits and the bit address are directly specified by the operand. This addressing mode can be used to manipulate the respective bits of the entire data memory area in various ways.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (7) Stack addressing This addressing mode is used to save or restore data when interrupt servicing or subroutine processing is executed. The address of data memory bank 0 pointed to by the stack pointer (8 bits) is specified in this addressing mode. In addition to being used during interrupt servicing or subroutine processing, this addressing is also used to save or restore register contents by using the PUSH or POP instruction. Examples 1.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 3.2 Bank Configuration of General-Purpose Registers The µPD754244 is provided with four register banks with each bank consisting of eight general-purpose registers: X, A, B, C, D, E, H, and L. The general-purpose register area consisting of these registers is mapped to the addresses 00H to 1FH of memory bank 0 (refer to Figure 3-5 Configuration of General-Purpose Registers (4-Bit Processing)).
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-4.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (1) To use as 4-bit registers When the general-purpose register area is used as a 4-bit register area, a total of eight general-purpose registers, X, A, B, C, D, E, H, and L, specified by RBE and RBS can be used as shown in Figure 3-5. Of these registers, A plays a central role in transferring, operating, and comparing 4-bit data as a 4-bit accumulator. The other registers can transfer, compare, and increment or decrement data with the accumulator.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-5. Configuration of General-Purpose Registers (4-Bit Processing) A X 00H 01H L H 02H 03H E D 04H 05H C B 06H 07H A X 08H 09H L H 0AH 0BH Register bank 1 (RBE.RBS = 1) E D 0CH 0DH C B 0EH 0FH A X 10H 11H L H 12H 13H Register bank 2 (RBE.RBS = 2) E D 14H 15H C B 16H 17H A X 18H 19H L H 1AH 1BH E D 1CH 1DH C B 1FH 48 Register bank 0 (RBE.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-6. Configuration of General-Purpose Registers (8-Bit Processing) XA XA' 00H 00H HL HL' 02H 02H DE DE' 04H 04H BC BC' 06H 06H When RBE.RBS = 0 XA' When RBE.RBS = 1 XA 08H 08H HL' HL 0AH 0AH DE' DE 0CH 0CH BC' BC 0EH 0EH XA XA' 10H 10H HL HL' 12H 12H DE DE' 14H 14H BC BC' 16H 16H When RBE. RBS = 2 XA' When RBE.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 3.3 Memory-Mapped I/O The µPD754244 employs memory-mapped I/O that maps peripheral hardware units such as I/O ports and timers to addresses F80H to FFFH on the data memory space, as shown in Figure 3-2. Therefore, no special instructions to control the peripheral hardware units are provided, and all the hardware units are controlled by using memory manipulation instructions.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7 shows the I/O map of the µPD754244. The meanings of the symbols shown in this figure are as follows. • Symbol ............ Name indicating the address of an internal hardware unit Can be written in operands of instructions • R/W ................. Indicates whether the hardware unit in question can be read or written R/W: Read/write R: Read only W: Write only • Number of bits that can be manipulated ..........
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD754244 I/O Map (1/8) Hardware name (symbol) Address R/W b3 F80H F82H b2 b1 b0 Stack pointer (SP) R/W Register bank selection register (RBS) F83H ................................................................................ 1-bit 4-bit – – 8-bit Bit manipulation addressing – – – ................................................................................
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD754244 I/O Map (2/8) Hardware name (symbol) Address R/W b3 F90H F92H b2 b1 b0 Timer counter 2 mode register (TM2) Number of bits that can be manipulated 1-bit R/W 4-bit 8-bit Bit manipulation addressing (W) – – – – – TOE2 REMC NRZB NRZ ................................................................................
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD754244 I/O Map (3/8) Hardware name (symbol) Address R/W b3 FA0H b2 b1 b0 Timer counter 0 mode register (TM0) FA2H TOE0Note 1 FA3H Unmounted FA4H Timer counter 0 count register (T0) FA6H FA8H – – 1-bit R/W – Number of bits that can be manipulated 4-bit 8-bit Bit manipulation addressing (W) – mem.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD754244 I/O Map (4/8) Hardware name (symbol) Address R/W b3 FB0H b2 b1 b0 Number of bits that can be manipulated 1-bit IST1 IST0 MBE RBE ................................................................................ R/W (R/W) 4-bit (R/W) 8-bit (R) Bit manipulation addressing fmem.bit Remarks R only possible as 8-bit manipulation. Program status word (PSW) .......................................................................
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD754244 I/O Map (5/8) Hardware name (symbol) Address R/W b3 b2 b1 b0 Number of bits that can be manipulated 1-bit 4-bit 8-bit Bit manipulation addressing FC0H Bit sequential buffer 0 (BSB0) R/W mem.bit FC1H Bit sequential buffer 1 (BSB1) R/W pmem.@L FC2H Bit sequential buffer 2 (BSB2) R/W FC3H Bit sequential buffer 3 (BSB3) R/W FC4H Unmounted Remarks FC5H FC6H Reset detection flag register (RDF) ....................
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD754244 I/O Map (6/8) Hardware name (symbol) Address R/W b3 b2 b1 b0 FD0H to FD3H Unmounted FD4H Programmable threshold port (PTH0) FD5H Unmounted FD6H Note Note Number of bits that can be manipulated 1-bit 4-bit R Note Note PTHM3 PTHM2 PTHM1 PTHM0 ................................................................................ R/W 8-bit – Bit manipulation addressing mem.bit – – mem.
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD754244 I/O Map (7/8) Hardware name (symbol) Address R/W b3 FE0H to FE7H FE8H b2 b1 b0 Number of bits that can be manipulated 1-bit 4-bit 8-bit Bit manipulation addressing Remarks Unmounted PM33 PM32 PM31 PM30 ................................................................................ R/W – – – – Port mode register group A (PMGA) ................................................................................
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CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Figure 3-7. µPD754244 I/O Map (8/8) Hardware name (symbol) Address R/W b3 b2 FF0H to FF2H Unmounted FF3H Port 3 (PORT3) FF4H Unmounted b1 b0 Number of bits that can be manipulated 1-bit 4-bit 8-bit R/W – R/W – Bit manipulation addressing Remarks fmem.bit pmem.@L FF5H FF6H Port 6 (PORT6) FF7HNote 1 FF8H Port 7 (PORT7) ................................................................................ R KR7 KR6 KR5 KR4 Port 8 (PORT8) ...
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CHAPTER 4 INTERNAL CPU FUNCTION 4.1 Function to Select MkI and MkII Modes 4.1.1 Difference between MkI and MkII modes The CPU of the µPD754244 has two modes to be selected: MkI and MkII. These modes can be selected by using bit 3 of the stack bank select register (SBS). • MkI mode: In this mode, the µPD754144 is upwardly-compatible with the 75X Series. This mode can be used with the CPU in the 75XL Series having a ROM capacity of up to 16 KB.
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CHAPTER 4 INTERNAL CPU FUNCTION 4.1.2 Setting stack bank select register (SBS) The MkI mode or MkII mode is selected by using the stack bank select register (SBS). Figure 4-1 shows the format of this register. The stack bank select register is set by using a 4-bit memory manipulation instruction. To use the MkI mode, be sure to initialize the stack bank select register to 1000B at the beginning of the program. To use the MkII mode, initialize the register to 0000B. Figure 4-1.
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CHAPTER 4 INTERNAL CPU FUNCTION 4.2 Program Counter (PC) ··· 12 bits This is a binary counter that holds an address of the program memory. Figure 4-2. Configuration of Program Counter PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 The value of the program counter (PC) is usually automatically incremented by the number of bytes of an instruction each time that instruction has been executed.
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CHAPTER 4 INTERNAL CPU FUNCTION 4.3 Program Memory (ROM) ··· 4096 × 8 bits The program memory stores a program, interrupt vector table, the reference table of the GETI instruction, and table data. The program memory is addressed by the program counter. The table data can be referenced by using a table reference instruction (MOVT). Figure 4-3 shows address ranges in which execution can be branched by a branch or subroutine call instruction.
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CHAPTER 4 INTERNAL CPU FUNCTION Figure 4-3.
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CHAPTER 4 INTERNAL CPU FUNCTION 4.4 Data Memory (RAM) ... 128 words × 4 bits The data memory consists of data areas and a peripheral hardware area as shown in Figure 4-4. The data memory consists the following banks with each bank made up of 256 words × 4 bits. • Memory bank 0 (data areas) • Memory bank 4 (EEPROM) • Memory bank 15 (peripheral hardware area) 4.4.
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CHAPTER 4 INTERNAL CPU FUNCTION 4.4.2 Specifying bank of data memory A memory bank is specified by a 4-bit memory bank select register (MBS) when bank specification is enabled by setting a memory bank enable flag (MBE) to 1 (MBS = 0, 4, or 15). When bank specification is disabled (MBS = 0), bank 0 or 15 is automatically specified depending on the addressing mode selected at that time. The addresses in the bank are specified by 8-bit immediate data or a register pair.
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CHAPTER 4 INTERNAL CPU FUNCTION Figure 4-4.
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CHAPTER 4 INTERNAL CPU FUNCTION The contents of the data memory are undefined at reset. Therefore, they must be initialized at the beginning of program execution (RAM clear). Otherwise, unexpected bugs may occur.
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CHAPTER 4 INTERNAL CPU FUNCTION 4.5 General-Purpose Registers ... 8 × 4 bits × 4 banks General-purpose registers are mapped to the specific addresses of the data memory. Four banks of registers, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, and A), are available. The register bank (RB) that becomes valid when an instruction is executed is determined by the following expression. RB = RBE. RBS (RBS = 0 to 3) Each general-purpose register is manipulated in 4-bit units.
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CHAPTER 4 INTERNAL CPU FUNCTION 4.6 Accumulator With the µPD754244, the A register or XA register pair functions as an accumulator. The A register plays a central role in 4-bit data processing, while the XA register pair is used for 8-bit data processing. When a bit manipulation instruction is used, the carry flag (CY) is used as a bit accumulator. Figure 4-7. Accumulator CY X Bit accumulator A 4-bit accumulator A 8-bit accumulator 4.
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CHAPTER 4 INTERNAL CPU FUNCTION When 00H is set to SP as the initial value, memory bank 0 specified by SBS is used as the stack area, starting from the highest address (07FH). The stack area can be used only in memory bank 0. If stack operation is performed from address 000H onwards, the stack pointer will point to unmounted area 0FFH. Therefore, be careful not to allow the stack pointer to exceed 000H.
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CHAPTER 4 INTERNAL CPU FUNCTION Figure 4-9. Data Saved to Stack Memory (MkI Mode) PUSH instruction CALL, CALLF instruction Interrupt Stack Stack Stack SP – 4 PC11-PC8 SP – 3 MBE RBE 0 PC11-PC8 SP – 6 0 SP – 5 MBE RBE 0 SP – 2 Register pair, low SP – 2 PC3-PC0 SP – 4 PC3-PC0 SP – 1 Register pair, high SP – 1 PC7-PC4 SP – 3 PC7-PC4 SP – 2 IST1 IST0 MBE RBE PSW SP – 1 CY SK2 SK1 SK0 SP SP 0 SP Figure 4-10.
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CHAPTER 4 INTERNAL CPU FUNCTION Figure 4-11. Data Saved to Stack Memory (MkII Mode) PUSH instruction CALL, CALLA, CALLF instruction Interrupt Stack Stack Stack PC11-PC8 SP – 6 SP – 5 0 0 0 PC11-PC8 SP – 6 SP – 5 0 0 0 0 SP – 2 Register pair, low SP – 4 PC3-PC0 SP – 4 PC3-PC0 SP – 1 Register pair, high SP – 3 PC7-PC4 SP – 3 PC7-PC4 SP – 2 SP * * MBE RBE Note SP – 1 * * * * SP 0 SP – 2 IST1 IST0 MBE RBE PSW SP – 1 CY SK2 SK1 SK0 SP Figure 4-12.
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CHAPTER 4 INTERNAL CPU FUNCTION 4.8 Program Status Word (PSW) ... 8 Bits The program status word (PSW) consists of flags closely related to the operations of the processor. PSW is mapped to addresses FB0H and FB1H of the data memory space, and the 4 bits of address FB0H can be manipulated by using a memory manipulation instruction. Figure 4-13.
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CHAPTER 4 INTERNAL CPU FUNCTION Table 4-4. Carry Flag Manipulation Instruction Instruction (Mnemonic) Operation and Processing of Carry Flag Carry flag manipulation SET1 CY Sets CY to 1 instruction CLR1 CY Clears CY to 0 NOT1 CY Inverts content of CY SKT CY Skips if content of CY is 1 MOV1 mem*.bit, CY Transfers content of CY to specified bit MOV1 CY, mem*.bit Transfers content of specified bit to CY AND1 CY, mem*.
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CHAPTER 4 INTERNAL CPU FUNCTION (3) Interrupt status flags (IST1 and IST0) The interrupt status flags record the status of the processing under execution (for details, refer to Table 7-3 IST, IST0, and Interrupt Servicing). Table 4-5. Contents of Interrupt Status Flags IST1 IST0 Status of Processing Being Executed Processing and Interrupt Control 0 0 Status 0 Normal program is being executed. All interrupts can be acknowledged 0 1 Status 1 Interrupt with lower or higher priority is serviced.
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CHAPTER 4 INTERNAL CPU FUNCTION (5) Register bank enable flag (RBE) This flag specifies whether the register bank of the general-purpose registers is expanded or not. RBE can be set or reset at any time by using a bit manipulation instruction, regardless of the setting of the memory bank. When this flag is set to “1”, one of four general-purpose register banks 0 to 3 can be selected depending on the contents of the register bank select register (RBS).
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CHAPTER 4 INTERNAL CPU FUNCTION 4.9 Bank Select Register (BS) The bank select register (BS) consists of a register bank select register (RBS) and a memory bank select register (MBS) which specify the register bank and the memory bank to be used, respectively. RBS and MBS are set by the SEL RBn and SEL MBn instructions, respectively. BS can be saved to or restored from the stack area in 8-bit units by the PUSH BS or POP BS instruction. Figure 4-14.
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CHAPTER 4 INTERNAL CPU FUNCTION (2) Register bank select register (RBS) The register bank select register specifies a register bank to be used as general-purpose registers. It can select bank 0 to 3. RBS is set by the SEL RBn instruction (n = 0-3). When the RESET signal is asserted, RBS is initialized to “0”. Table 4-7.
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CHAPTER 5 EEPROM The µPD754244 incorporates not only a 128-word × 4-bit static RAM but also a 16-word × 8-bit EEPROM (Electrically Erasable PROM) as data memory. EEPROM, unlike static RAM, can retain its contents when the power is turned off. Unlike EPROM, contents can electrically be erased without using ultraviolet rays. It is, therefore, suitable for application fields such as keyless entry and as a data carrier. EEPROM is mapped onto memory bank 4 of the data memory.
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CHAPTER 5 EEPROM 5.3 EEPROM Write Control Register (EWC) The EEPROM write control register (EWC) is an 8-bit register used to control manipulation of EEPROM. Figure 5-1 shows its configuration. Figure 5-1.
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CHAPTER 5 EEPROM Cautions 1. The write time depends on the system clock oscillation frequency. 2. Set EWTC4-EWTC6 so that the write time is as follows. With µPD754144 ··· 18 × 28/fCC (4.6 ms: fCC = 1.0 MHz) With µPD754244 ··· 4.0 ms MIN., 10.0 ms MAX. Clear EWE to 0 after writing. 3. Be sure to clear (0) the ERE flag before executing a STOP instruction to disable reading. If the ERE flag is set (1), a current of approximately 10 µA always flows in the read circuit.
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CHAPTER 5 EEPROM 5.5 EEPROM Manipulation Method 5.5.1 EEPROM manipulation instructions Instructions that can be used to manipulate the EEPROM are shown below, divided into read instructions and write instructions. (1) Read manipulation instructions Instruction Group Transfer instruction Compare instruction Mnemonic Operand MOV XA, @HL MOV XA, mem SKE XA, @HL Remark Operation instruction such as ADDS, AND, etc., cannot be used.
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CHAPTER 5 EEPROM 5.5.2 Read manipulation The following procedure is used to read EEPROM. EWST, ERE and EWE can be set simultaneously by an 8-bit memory manipulation instruction to EWC. <1> Check that the write status flag (EWST) is 0 (write enabled = writing is currently not being performed). <2> Set the write enable/disable control bit (EWE) to 0 (write disabled). <3> Execute the read instruction. Figure 5-2.
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CHAPTER 5 EEPROM 5.5.3 Write manipulation Use the following procedure to write to EEPROM. Any instruction other than one related to EEPROM writing can be executed even during an EEPROM write operation. EWST, EWTC and EWE can be set simultaneously by an 8-bit memory manipulation instruction to EWC. <1> Check that the read status (EWST) is 0 (write enabled = currently not being written). <2> Use EWTC4 to EWTC6 to set write time. <3> Set the write enable/disable control bit (EWE) to 1 (write enabled).
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CHAPTER 5 Example EEPROM Set the write time to 18 × 28/fX and after checking the EEPROM write status flag (EWST), write 8-bit data (0AH) at 08H of memory bank 4. SET1 WAIT; MBE SEL MB15 ; Selection of bank 15 MOV XA, #01011000B ; Write enable MOV EWC, XA ; Set the write time to 18 × 28 /fX SKF EWST BR A1 SEL MB4 MOV XA, #0AH MOV 08H, XA CLR1 MBE SKF EWST BR WAIT CLR1 EWE ; Write Caution The development tool simulates writing data to EEPROM by writing the data to RAM.
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CHAPTER 5 EEPROM 5.6 Cautions on EEPROM Writing Cautions on EEPROM writing are shown below. Be sure to read these before writing to EEPROM. Cautions 1. Before writing, make sure that EWST is 0. While EEPROM is being written, if a write instruction is executed again, the instruction executed later is ignored. 2. There are restrictions on the write instruction. Refer to 5.5.1 EEPROM manipulation instructions for details. 3. Set EWTC4 to EWTC6 so that the write time is as follows. With µPD754144 ...
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Ports The µPD754244 uses memory mapped I/O, and all the I/O ports are mapped to the data memory space. Figure 6-1. Data Memory Address of Digital Ports Address 3 2 FF0H — FF1H — FF2H — FF3H P33 P32 FF4H — FF5H — 1 0 P31 P30 Port 3 FF6H P63 P62 P61 P60 Port 6 FF7H P73 P72 P71 P70 Port 7 FF8H – – – P80 Port 8 Table 6-2 lists the instructions that manipulate the I/O ports.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.1 Types, features, and configurations of digital I/O ports Table 6-1 shows the types of digital I/O ports. Figures 6-2 to 6-9 show the configuration of each port. Table 6-1. Types and Features of Digital Ports Port PORT3 Function 4-bit I/O Operation and Features Can be set to input or output mode in 1-bit units. PORT6 Remarks Also used for PTO0 to PTO2 pins. Also used for AVREF, INT0, PTH00, and PTH01 pins.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-2. P3n Configuration (n = 0 to 2) VDD POGA bit 3 Pull-up resistor Input buffer MPX P-ch Internal bus Input buffer Output buffer Output latch P3n/PTOn PM3n PTOn Figure 6-3.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-4. P60 Configuration VDD POGA bit 6 Input buffer with hysteresis characteristics Pull-up resistor Internal bus MPX Input buffer P-ch Output buffer Output latch P60/AVREF AVREF PM60 Figure 6-5.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-6. P62 Configuration VDD POGA bit 6 Input buffer with hysteresis characteristics Pull-up resistor P-ch Internal bus MPX Input buffer Output buffer Output latch P62/PTH00 PTH00 PM62 Figure 6-7.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-8. P7n Configuration (n = 0 to 3) Key return reset One-shot pulse generator VDD Interrupt control Pull-up resistor (mask option) Falling edge detector Input buffer with hysteresis characteristics Input buffer Internal bus P70/KR4 P71/KR5 P72/KR6 P73/KR7 Figure 6-9.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.2 Setting I/O mode The input or output mode of each I/O port is set by the corresponding port mode register as shown in Figure 610. Ports 3 and 6 can be set to the input or output mode in 1-bit units by using port mode register group A (PMGA). Port 8 is set to the input or output mode by using port mode register group C (PMGC).
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-10.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.3 Digital I/O port manipulation instruction Because all the I/O ports of the µPD754244 are mapped to the data memory space, they can be manipulated by using data memory manipulation instructions. Table 6-2 shows these data memory manipulation instructions, which are considered to be especially useful for manipulating the I/O pins and their range of applications. (1) Bit manipulation instruction Because specific address bit direct addressing (fmem.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Table 6-2. I/O Pin Manipulation Instructions PORT PORT3 PORT6 PORT7 PORT8 Instruction IN A, PORTnNote 1 IN XA, PORTnNote 1 OUT OUT PORTn, ANote 1 PORTn, XANote 1 – – – PORTnNote 1 MOV A, MOV XA, PORTnNote 1 – ANote 1 MOV PORTn, MOV PORTn, XANote 1 – PORTnNote 1 XCH A, XCH XA, PORTnNote 1 MOV1 CY, PORTn. bit MOV1 CY, PORTn. @LNote 2 MOV1 PORTn. bit, CY – – CYNote 2 MOV1 PORTn. @L, INCS PORTnNote 1 SET1 PORTn.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.4 Operation of digital I/O port The operations of each port and port pin when a data memory manipulation instruction is executed to manipulate a digital I/O port differ depending on whether the port is set to the input or output mode (refer to Table 6-3).
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Table 6-3.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.5 Connecting pull-up resistor Each port pin of the µPD754244 can be connected to a pull-up resistor. Some pins can be connected to a pullup resistor via software and others can be connected by a mask option. Table 6-4 shows how to specify the connection of the pull-up resistor to each port pin. The pull-up resistor is connected via software in the format shown in Figure 6-11.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1.6 I/O timing of digital I/O port Figure 6-12 shows the timing at which data is output to the output latch and the timing at which the pin data or the data of the output latch is loaded to the internal bus. Figure 6-13 shows the ON timing when an on-chip pull-up resistor connection is specified via software. Figure 6-12.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-13.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.2 Clock Generator The clock generator supplies various clocks to the CPU and peripheral hardware units and controls the operation mode of the CPU. 6.2.1 Configuration of clock generator Figure 6-14 shows the configuration of the clock generator. Figure 6-14.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-14.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.2.2 Function and operation of clock generator The clock generator generates the following types of clocks and controls the operation mode of the CPU in the standby mode. • System clock • CPU clock fX Φ • Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) as follows. (a) When the RESET signal is asserted, the slowest mode of the system clockNote 1 is selected (PCC = 0).
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (1) Processor clock control register (PCC) PCC is a 4-bit register that selects the CPU clock Φ with the lower 2 bits and controls the CPU operation mode with the higher 2 bits (refer to Figure 6-15). When either bit 3 or 2 of this register is set to “1”, the standby mode is set.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-15. Format of Processor Clock Control Register Address FB3H 3 2 1 0 PCC3 PCC2 PCC1 PCC0 Symbol PCC CPU operating mode control bits PCC3 PCC2 Operating mode 0 0 Normal operating mode 0 1 HALT mode 1 0 STOP mode 1 1 Setting prohibited CPU clock selection bits (µPD754144: When fCC = 1.0 MHz) PCC1 PCC0 CPU clock frequency 1 machine cycle 0 0 Φ = fCC/64 (15.6 kHz) 64 µs 0 1 Φ = fCC/16 (62.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) System clock oscillator (a) µPD754144 (RC oscillation) The system clock oscillator oscillates by means of a resistor (R) and capacitor (C) connected to the CL1 and CL2 pins. An external clock cannot be input for RC oscillation. The relationship between the output frequency of the system clock oscillator (fCC), resistance (R), and capacitance (C) is as follows.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Cautions 1. The X2 pin of the µPD754244 is internally pulled up to VDD by a resistor of 50 kΩ (typ.) 2. Wire the portion enclosed by the dotted lines in Figures 6-16 and 6-17 as follows to in the STOP mode. prevent adverse influence by wiring capacitance when using the system clock oscillator. • Keep the wiring length as short as possible. • Do not cross the wiring with any other signal lines.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-18.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-18.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.2.3 Setting CPU clock (1) Time required to switch CPU clock The CPU clock can be switched by using the lower 2 bits of PCC. The processor does not operate with the selected clock, however, immediately after data has been written to the registers; it operates with the prechange clock for the duration of a certain number of machine cycles. To stop oscillation of the system clock, therefore, execute the STOP instruction after a specific time has elapsed. Table 6-5.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-19. CPU Clock Switching Example On Commercial power supply Off Minimum operating supply voltage VDD pin voltage RESET signal <1> Wait Note 1 <5> Wait Note 3 fX CPU clock fX <3> 0.67 µ s <4> STOP mode <2> Lowest speed of system clock Note 2 Internal reset operation fX <6> 0.67 µ s <1> Wait timeNote 1 to secure the oscillation stabilization time in response to RESET signal generation.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.3 Basic Interval Timer/Watchdog Timer The µPD754244 has an 8-bit basic interval timer/watchdog timer that has the following functions. (a) Interval timer operation to generate reference time interrupt (b) Watchdog timer operation to detect program hang-up and reset CPU (c) To select and count wait time when standby mode is released (µPD754244 only) (d) To read count value 6.3.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.3.2 Basic interval timer mode register (BTM) BTM is a 4-bit register that controls the operation of the basic interval timer (BT). This register is set by a 4-bit memory manipulation instruction. Bit 3 of BT can be manipulated by a bit manipulation instruction. Example To set the interrupt generation interval of the µPD754244 to 1.37 ms (at fX = 6.0 MHz)Note SEL MB15 CLR1 WDTM MOV A, #1111B MOV BTM,A ; or CLR1 MBE ; BTM ← 1111B Note It is 1.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-21. Format of Basic Interval Timer Mode Register Address F85H 3 2 1 0 BTM3 BTM2 BTM1 BTM0 Symbol BTM µPD754144: fCC = 1.0 MHz Specifies input clock Interrupt interval time 12 220/fCC (1.05 s) 9 2 /fCC (131 ms) 7 0 0 0 fCC/2 (244 Hz) 0 1 1 fCC/2 (1.95 kHz) 17 1 0 1 fCC/2 (7.81 kHz) 15 2 /fCC (32.8 ms) 1 1 1 fCC/25 (31.3 kHz) 213/fCC (8.19 ms) Other Setting prohibited – µPD754244: fX = 6.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.3.3 Watchdog timer enable flag (WDTM) WDTM is a flag that enables assertion of the reset signal when an overflow occurs. This flag is set by a bit manipulation instruction. Once this flag has been set, it cannot be cleared by an instruction. Example To set watchdog timer function SEL MB15 SET1 WDTM ; or CLR1 MBE • • • SET1 BTM.3 ; Sets bit 3 of BTM to “1” The contents of this flag are cleared to 0 when the RESET signal is asserted. Figure 6-22.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.3.4 Operation as basic interval timer When WDTM is reset to “0”, the interrupt request flag (IRQBT) is set by the overflow of the basic interval timer (BT), and the basic interval timer/watchdog timer operates as the basic interval timer. BT is always incremented by the clock supplied by the clock generator and its counting operation cannot be stopped. Four time intervals at which an interrupt occurs can be selected by BTM (µPD754244 only. Refer to Figure 621).
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.3.5 Operation as watchdog timer The basic interval timer/watchdog timer operates as a watchdog timer that asserts the internal reset signal when an overflow occurs in the basic interval timer (BT), if WDTM is set to “1”. However, if the overflow occurs during the oscillation wait time that elapses after the STOP instruction has been released, the reset signal is not asserted. (Once WDTM has been set to “1”, it cannot be cleared by any means other than reset.
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CHAPTER 6 Example PERIPHERAL HARDWARE FUNCTION To use the µPD754244 as a watchdog timer with a time interval of 5.46 ms (at fX = 6.0 MHz).Note Divide the program into several modules, each of which is completed within the set time of BTM (5.46 ms), and clear BT at the end of each module. If a hang-up occurs, BT is not cleared within the set time. As a result, BT overflows, and the internal reset signal is asserted.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.3.6 Other functions The basic interval timer/watchdog timer has the following functions, regardless of the operations as the basic interval timer or watchdog timer.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4 Timer Counter The µ PD754244 incorporates a three-channel timer counter. The timer counter has the following functions. (a) Programmable interval timer operation (b) Square wave output of any frequency to PTO0-PTO2 pins (c) Count value read function The timer counter can operate in the following four modes as set by the mode register. Table 6-6.
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Figure 6-23. Block Diagram of Timer Counter (Channel 0) Internal bus 8 – SET1Note TM06 TM05 TM04 TM03 TM02 8 TM0 0 8 0 T0 enable flag Modulo register (8) 8 T0 CP Clear Timer operation starts Note Execution of the instruction Caution Be sure to clear bits 1 and 0 to 0 when setting data to TM0.
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Figure 6-24.
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Figure 6-25.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (1) Timer counter mode registers (TM0, TM1, TM2) A timer counter mode register (TMn) is an 8-bit register that controls the corresponding timer counter. Figures 6-26 to 6-28 show the formats of the various mode registers. The timer counter mode register is set by an 8-bit memory manipulation instruction. Bit 3 of this register is a timer start bit and can be manipulated in 1-bit units independently of the other bits.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-26. Format of Timer Counter Mode Register (Channel 0) Address FA0H 7 – 6 TM06 5 TM05 4 3 TM04 2 TM03 TM02 0 1 0 Symbol Note Note TM0 0 Count pulse (CP) select bit µPD754144: fCC = 1.0 MHz TM06 TM05 TM04 Count pulse (CP) 10 1 0 0 fCC/2 (977 Hz) 1 0 1 fCC/28 (3.91 kHz) 1 1 0 fCC/26 (15.6 kHz) 1 1 1 4 fCC/2 (62.5 kHz) Other Setting prohibited µPD754244: fX = 6.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-27. Format of Timer Counter Mode Register (Channel 1) (1/2) Address 7 6 5 4 3 2 1 0 FA8H – TM16 TM15 TM14 TM13 TM12 TM11 TM10 Symbol TM1 Count pulse (CP) select bit µ PD754144: fCC = 1.0 MHz TM16 TM15 TM14 0 1 0 Overflow of timer counter (channel 2) 0 1 1 5 fCC/2 (31.3 kHz) 1 0 0 fCC/212 (244 Hz) 1 0 1 10 fCC/2 (977 Hz) 1 1 0 fCC/2 (3.91 kHz) 1 1 1 fCC/26 (15.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-27. Format of Timer Counter Mode Register (Channel 1) (2/2) Timer start command bit TM13 Clears counter and IRQT1 flag when "1" is written. Starts count operation if bit 2 is set to "1".
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-28. Format of Timer Counter Mode Register (Channel 2) (1/2) Address 7 6 5 4 3 2 1 0 F90H – TM26 TM25 TM24 TM23 TM22 TM21 TM20 Symbol TM2 Count pulse (CP) select bit µ PD754144: fCC = 1.0 MHz TM26 TM25 TM24 0 1 0 fCC/2 (500 MHz) 0 1 1 fCC (1.0 MHz) 1 0 0 fCC/210 (977 Hz) 1 0 1 8 fCC/2 (3.91 kHz) 1 1 0 fCC/26 (15.6 kHz) 1 1 1 fCC/24 (62.5 kHz) Other Count pulse (CP) Setting prohibited µ PD754244: fX = 6.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-28. Format of Timer Counter Mode Register (Channel 2) (2/2) Timer start command bit TM23 Clears counter and IRQT2 flag when "1" is written. Starts count operation if bit 2 is set to "1".
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) Timer counter output enable flags (TOE0, TOE1) Timer counter output enable flags TOE0 and TOE1 enable or disable output to the PTO0 and PTO1 pins in the timer out F/F (TOUT F/F) status. The timer out F/F is inverted by a match signal from the comparator. When bit 3 (timer start command bit) of timer counter mode register TM0 or TM1 is set to “1”, the timer out F/F is cleared to “0”.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (3) Timer counter control register (TC2) The timer counter control register (TC2) is an 8-bit register that controls the timer counter (channel 2). Figure 6-30 shows the format of this register. This register controls timer output enable carrier generator mode used in combination with the timer counter (channel 1). TC2 is set by an 8- or 4-bit manipulation instruction and bit manipulation instruction.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4.2 Operation in 8-bit timer counter mode In this mode, the timer counter is used as an 8-bit timer counter. In this case, the timer counter operates as an 8-bit programmable interval timer or counter.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-31. Setting of Timer Counter Mode Register (1/3) (a) Timer counter (channel 0) Address FA0H 7 – 6 TM06 5 TM05 4 TM04 3 1 0 Symbol Note Note TM0 2 TM03 TM02 0 0 Count pulse (CP) select bit TM06 TM05 TM04 Count pulse (CP) 10 1 0 0 fX/2 1 0 1 fX/2 1 1 0 fX/26 1 1 1 fX/2 Other 8 4 Setting prohibited Timer start command bit TM03 Clears counter and IRQT0 flag when "1" is written.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-31.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-31. Setting of Timer Counter Mode Register (3/3) (c) Timer counter (channel 2) Address 7 6 5 4 3 2 1 0 F90H – TM26 TM25 TM24 TM23 TM22 TM21 TM20 Symbol TM2 Count pulse (CP) select bit TM26 TM25 TM24 0 1 0 fX/2 0 1 1 fX 1 0 0 fX/2 1 0 1 fX/2 1 1 0 fX/26 1 1 1 fX/24 Other Count pulse (CP) 10 8 Setting prohibited Timer start command bit TM23 Clears counter and IRQT2 flag when "1" is written.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (b) Timer counter control register (TC2) In the 8-bit timer counter mode, set TC2 as shown in Figure 6-32 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register). TC2 is manipulated by an 8- or 4-bit, or bit manipulation instruction. The value of TC2 is cleared to 00H when the internal reset signal is asserted. The flags shown by a solid line in the figure below are used in the 8-bit timer counter mode.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION [Timer set time] (cycle) is calculated by dividing [contents of modulo register + 1] by [count pulse (CP) frequency] selected by the mode register. T (sec) = where, = (n+1) n +1 fCP (resolution) . T (sec): Timer set time (seconds) fCP (Hz): CP frequency (Hz) n: Contents of modulo register (n ≠ 0) Once the timer has been set, interrupt request flag IRQTn is set at the set time interval of the timer.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Table 6-7. Resolution and Longest Set Time (8-Bit Timer Counter Mode) (2/3) (TM10 = 0, TM11 = 0, TM20 = 0, TM21 = 0) 8-bit timer counter (channel 2) Mode Register 8-bit Timer Counter (Channel 2) TM26 TM25 TM24 Resolution Longest set time 0 1 0 333 ns 85.3 µs 0 1 1 167 ns 42.7 µs 1 0 0 171 µs 43.7 ms 1 0 1 42.7 µs 10.9 ms 1 1 0 10.7 µs 2.73 ms 1 1 1 2.67 µs 683 µs (b) µPD754244: at 4.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Table 6-7. Resolution and Longest Set Time (8-Bit Timer Counter Mode) (3/3) (TM10 = 0, TM11 = 0, TM20 = 0, TM21 = 0) (c) µPD754144: at 1.0 MHz 8-bit timer counter (channel 0) Mode Register 8-bit Timer Counter (Channel 0) TM06 TM05 TM04 Resolution Longest set time 1 0 0 1024 µs 262ms 1 0 1 256 µs 65.5 ms 1 1 0 64 µs 16.4 ms 1 1 1 16 µs 4.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (3) Timer counter operation (8-bit) The timer counter operates as follows. Figure 6-34 shows the configuration when the timer counter operates. <1> The count pulse (CP) is selected by the timer counter mode register (TMn) and is input to the timer counter count register (Tn). <2> The contents of Tn are compared with those of the modulo register (TMODn).
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-34. Configuration When Timer Counter Operates INTTn (lRQTn set signal) Internal clock Timer counter modulo register (TMODn) Coincidence Comparator MPX CP Timer counter count register (Tn) PTOn TOUT F/F Clear Figure 6-35.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (4) Application of 8-bit timer counter mode As an interval timer that generates an interrupt at 50 ms intervalsNote • Set the higher 4 bits of the timer counter mode register (TMn) to 0100B, and select 62.5 ms (at fX = 4.19 MHz of µPD754244) as the longest set time. • Set the lower 4 bits of TMn to 1100B.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4.3 Operation in PWM pulse generator mode (PWM mode) In this mode, the timer counter (channel 2) is used as a PWM pulse generator. The timer counter operates as an 8-bit PWM pulse generator. When the timer counter (channel 2) is used as a PWM pulse generator, the timer counters (channel 0 and 1) can be used as 8-bit timer counter. (1) Register setting In the PWM mode, the following five registers are used.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-36. Setting of Timer Counter Mode Register Address 7 6 5 4 3 2 1 0 F90H – TM26 TM25 TM24 TM23 TM22 TM21 TM20 Symbol TM2 Count pulse (CP) select bit TM26 TM25 TM24 0 1 0 fX/2 0 1 1 fX 1 0 0 fX/210 1 0 1 fX/28 1 1 0 fX/26 1 1 1 fX/24 Other Count pulse (CP) Setting prohibited Timer start command bit TM23 Clears counter and IRQT2 flag when "1" is written. Starts count operation if bit 2 is set to "1".
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (b) Timer counter control register (TC2) In the PWM mode, set TC2 as shown in Figure 6-37 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register). TC2 is manipulated by an 8-, 4-, or bit manipulation instruction. TC2 is cleared to 00H when the internal reset signal is asserted. The flags shown by a solid line in the figure below are used in the PWM mode. Do not use the flags shown by a dotted line in the PWM mode (set these flags to 0).
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) PWM pulse generator operation The timer counter (channel 2) in PWM pulse generator mode has two registers, a high-level period setting timer counter modulo register (TMOD2H) and a low-level period setting timer counter modulo register (TMOD2). Figure 6-38 shows the PWM pulse generator configuration. Each modulo register inverts its signal when the time set to each elapses. Therefore, pulses output from the PTO0 pin can be set arbitrarily for each modulo register.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-38. PWM Pulse Generator Operating Configuration Timer counter (channel 2) High level period setting timer counter modulo register (TMOD2H) Timer counter (Channel 2) modulo register (TMOD2) MPX Coinci- INTT2 dence TOUT F/F Comparator fx fx/2 4 Internal fx/26 f x/2 clock fx/28 fx/210 CP MPX Note Timer counter count register (T2) PTO2 Clear Note This is the IRQT2 set signal. It is only set when TMOD2 matches T2. Figure 6-39.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (3) Application of PWM mode To output a pulse with a frequency of 38.0 kHz (cycle of 26.3 µs) and a duty factor of 1/3 to the PTO2 pinNote • Set the higher 4 bits of the timer counter mode register (TM2) to 0011B and select 61.0 µs as the longest set time. • Set the lower 4 bits of TM2 to 1101B, and select the PWM mode and count operation, and issue the timer start command. • Set the timer counter output enable flag (TOE2) to “1” to enable timer output.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4.4 Operation in 16-bit timer counter mode In this mode, two timer counter channels, 1 and 2, are used in combination to implement 16-bit programmable interval timer or event timer operation. (1) Register setting In the 16-bit timer counter mode, the following seven registers are used.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-40.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (b) Timer counter control register (TC2) In the 16-bit timer counter mode, set TC2 as shown in Figure 6-41 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register). TC2 is manipulated by an 8-, 4-, or bit manipulation instruction. TC2 is cleared to 00H when the internal reset signal is asserted. The flags shown by a solid line in Figure 6-40 are used in the 16-bit timer counter mode.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) Time setting of timer counter [Timer set time] (cycle) is calculated by dividing [contents of modulo register + 1] by [count pulse (CP) frequency] selected by the mode register. T (sec) = n+1 fCP = (n+1) . (resolution) where, T (sec): Timer set time (seconds) fCP (Hz): CP frequency (Hz) n: Contents of modulo register (n ≠ 0) Once the timer has been set, interrupt request flag IRQT2 is set at the set time interval of the timer.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Table 6-8. Resolution and Longest Set Time (16-Bit Timer Counter Mode) (2/2) (TM10 = 0, TM11 = 1, TM20 = 0, TM21 = 1) (c) µPD754244: at 4.19 MHz Mode Register 16-Bit Timer Counter TM26 TM25 TM24 Resolution Longest Set Time 0 1 0 477 ns 31.3 ms 0 1 1 238 ns 15.6 ms 1 0 0 244 µs 16.0 s 1 0 1 61.0 µs 4.0 s 1 1 0 15.3 µs 1.0 s 1 1 1 3.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (3) Timer counter operation (at 16-bit) The timer counter operates as follows. Figure 6-42 shows the configuration when the timer counter operates. <1> The count pulse (CP) is selected by timer counter mode registers TM1 and TM2 and is input to timer counter count register T2. The overflow of T2 is input to count register T1. <2> The contents of T1 are compared with those of timer counter modulo register TMOD1.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-42.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-43.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (4) Application of 16-bit timer counter mode As an interval timer that generates an interrupt at 5-second intervalsNote • Set the higher 4 bits of the mode register (TM1) to 0010B, and select the overflow of timer counter count register (T2). • Set the higher 4 bits of TM2 to 0100B and select 16.0 second as the longest set time. • Set the lower 4 bits of TM1 to 0010B and select the 16-bit timer counter mode.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4.5 Operation in carrier generator mode (CG mode) In the PWM mode, timer counter channels 1 and 2 operate in combination to implement an 8-bit carrier generator operation. When using CG mode, use it in combination with channel 1 and channel 2 of the timer counter. Timer counter channel 1 generates a remote controller signal. Timer counter channel 2 generates a carrier clock. (1) Register setting In the CG mode, the following eight registers are used.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-44.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (b) Timer counter control register (TC2) In the CG mode, set the timer counter output enable flag (TOE1) and TC2 as shown in Figure 6-45 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register). TOE1 is manipulated by a bit manipulation instruction. TC2 is manipulated by an 8-, 4-, or bit manipulation instruction. TOE1 and TC2 are cleared to 00H when the internal reset signal is asserted.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) Carrier generator operation The carrier generator operation is performed as follows. Figure 6-47 shows the configuration of the timer counter in the carrier generator mode. (a) Timer counter (channel 1) operation The timer counter (channel 1) in carrier generator mode determines the time required to output the carrier clock generated by the timer counter (channel 2) to the PTO2 pin, and the time to stop the output.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION <4> The operations <2> and <3> are repeated. <5> The no return zero data is reloaded from NRZB to NRZ when timer counter channel 1 generates an interrupt. <6> A carrier clock or high level is output when NRZ is set to 1 by the remote controller output flag (REMC). When NRZ = 0, a low level is output. Figure 6-48 shows the timing of the carrier generator operation. The carrier generator operation is usually started by the following procedure.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-47.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-48.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Remark If a timer (channel 1) interrupt is generated when the PTO2 pin is low and the carrier clock is high (NRZ = 0, carrier clock = high level), the carrier is output to the PTO2 pin from the pulse after the carrier clock. If a timer (channel 1) interrupt is generated when the PTO2 pin is high and the carrier clock is high (NRZ = 1, carrier clock = high level), the PTO2 pin does not become low until the end of the carrier clock being output.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (3) Application of CG mode To use the timer counter as a carrier generator for remote controller signal transmission The examples shown below apply to the operation of the µPD754244 at fX = 4.19 MHz. With fX = 6.0 MHz operation of the µPD754244 and f CC = 1.0 MHz operation of the µPD754144, the cycles and signal output periods are different even if the settings are the same. <1> To generate a carrier clock with a frequency of 38.0 kHz (cycle of 26.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION <2> To output a leader code with a 9 ms period to output a carrier clock and a 4.5 ms period to output a low level (Refer to the figure below.) • Set the higher 4 bits of the timer counter mode register (TM1) to 0110B and select 15.6 ms as the longest set time. • Set the lower 4 bits of TM1 to 1100B. Then, select the 8-bit timer counter mode, count operation, and timer start command. • The initial set value of the timer counter modulo register (TMOD1) is as follows.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION <3> To output a custom code with a 0.56 ms period to output a carrier clock when data is “1”, a 1.69 ms to output a low level, a 0.56 ms to output a carrier clock when data is “0”, and a 0.56 ms period to output a low level (refer to the figure below). • Set the higher 4 bits of the timer counter mode register (TM1) to 0011B and select 1.95 ms as the longest set time. • Set the lower 4 bits of TM1 to 1100B.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION In the following example, it is assumed that the output latch of the PTO2 pin is cleared to “0” and that the output mode has been set. It is also assumed that the carrier clock is generated with the status of the program in the preceding example (2). ; SEND_CARIER_DATA_PRO SEL MB15 ; or CLR1 MBE MOV HL, #00H ; Sets pointer of BSB (bit sequential buffer) to L.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION BR SEND_1_F CALL !SEND_D_1 BR SEND_1_F ; If data is 0, proceeds to transmission processing of next data with PTO2 pin outputting low level SEND_END : ; Completes transmission of 16 bits of data ; GET_DATA: ; Searches data of BSB indicated by @L. Sets value to H register SKT BSB0.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.4.6 Notes on using timer counter (1) Error when timer starts After the timer has been started (bit 3 of TMn has been set to “1”), the time required for generation of the match signal, which is calculated by the expression (contents of modulo register + 1) × resolution, deviates by up to one clock of the count pulse (CP). This is because timer counter count register Tn is cleared asynchronously to CP, as shown below.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (2) Note on starting timer Usually, count register Tn and interrupt request flag IRQTn are cleared when the timer is started (bit 3 of TMn is set to “1”). However, if the timer is in an operation mode, and if IRQTn is set as soon as the timer is started, IRQTn may not be cleared. This does not pose any problem when IRQTn is used as a vector interrupt.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (3) Notes on changing count pulse When it is specified to change the count pulse (CP) by rewriting the contents of the timer counter mode register (TMn), the specification becomes valid immediately after execution of the instruction that commands the specification.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (4) Operation after changing modulo register The contents of the timer counter modulo register (TMODn) and high-level period setting timer counter modulo register (TMOD2H) are changed as soon as an 8-bit data memory manipulation instruction has been executed.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (5) Note on application of carrier generator (on starting) When the carrier clock is generated, after the timer has been started (by setting bit 3 of TM2 to “1”), the highlevel period of the initial carrier clock may deviate by up to one clock of the count pulse (CP) (up to two clocks of CP if the frequency of CP is higher than one machine cycle) from the value calculated by the expression (contents of modulo register + 1) × resolution (for details, refer to (1) Erro
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (6) Notes on application of carrier generator (reload) To output a carrier to the PTO2 pin, the time required for the initial carrier to be generated deviates by up to one carrier clock after reloading (the contents of the no return zero buffer flag (NRZB) are transferred to the no return zero flag (NRZ) by occurrence of the interrupt of timer counter channel 1, and the contents of NRZ are updated to “1”).
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION (7) Notes on application of carrier generator (restarting) If forced reloading is performed by directly rewriting the contents of the no return zero flag (NRZ) and then the timer is restarted (by setting bit 3 of TM2 to “1”) when the carrier clock is high (TOUT F/F holds “1”), the carrier may not be output to the PTO2 pin as shown below. SET1 NRZ NRZ TOUT F/F 0 0 1 1 0 1 1 0 1 0 Clock PTO2 SET1 TM2.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.5 Programmable Threshold Port (Analog Input Port) The µPD754244 provides analog input pins (PTH00, PTH01) whose threshold voltage (reference voltage) is selectable within sixteen steps. The following operations can be performed with these analog input pins.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Figure 6-49.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.5.2 Programmable threshold port mode (PTHM) register PTHM is an 8-bit register that controls the programmable threshold port operation, and it is set by an 8-bit memory manipulation instruction. The threshold voltage can be selected by specifying the lower four bits of PTHM within 16 steps as follows. AVREF × 0.5 15.5 - AVREF × 16 16 It is also possible to reduce the current consumption if the comparator operation is stopped (PTHM7 = 0).
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.5.3 Programmable threshold port application (1) An analog input voltage input to the PTH00 pin is A/D converted with 4-bit resolution. Figure 6-51. Application Example of Programmable Threshold Port AVREF PTH00 input voltage 7.5/16 ⋅ AVREF Reference voltage (VREF) Conversion start Conversion end VSS Comparison result 1 0 1 0 The conversion result is stored in bit sequential buffer BSB0 (refer to 6.6 Bit Sequential Buffer).
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.6 Bit Sequential Buffer ... 16 Bits The bit sequential buffer (BSB) is a special data memory used for bit manipulation. It can manipulate bits by sequentially changing the address and bit specification. Therefore, this buffer is useful for processing data with a long bit length in bit units. This data memory is configured of 16 bits and can be addressed by a bit manipulation instruction in the pmem.@L addressing mode.
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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION Example For serial output of the 16-bit data of BUFF1, 2 from bit 0 of port 3 LOOP0: CLR1 MBE MOV XA, BUFF1 MOV BSB0, XA MOV XA, BUFF2 MOV BSB2, XA MOV L, #0 SKT BSB0, @L BR LOOP1 NOP SET1 LOOP1: ; Sets BSB0, 1 ; Sets BSB2, 3 ; Tests specified bit of BSB ; Dummy (to adjust timing) PORT3.0 BR LOOP2 CLR1 PORT3.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS The µPD754244 has six vectored interrupt sources and one test input that can be used for various applications. The interrupt controller of the µPD754244 has unique features and can service interrupts at extremely high speed.
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Figure 7-1. Block Diagram of Interrupt Controller Internal bus 2 4 Interrupt enable flag (IE×××) IM2 IME IPS IST1 IST0 IM0 Decoder CHAPTER 7 VRQn Note1 Edge detector IRQBT IRQ0 INTT0 IRQT0 INTT1 IRQT1 INTT2 IRQT2 INTEE IRQEE Vector table address generator Priority controller KR4/P70 Falling edge detectorNote2 IRQ2 KR7/P73 Key return reset circuit IM2 Notes 1. 187 2. Standby release signal Noise eliminator (Standby release is disable when noise eliminator is selected.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.2 Types of Interrupt Sources and Vector Table The µPD754244 has the following six interrupt sources and nesting of interrupts can be controlled by software. Table 7-1.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Figure 7-2.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.3 Hardware Controlling Interrupt Function (1) Interrupt request flag and interrupt enable flag The µPD754244 has the following six interrupt request flags (IRQ×××) corresponding to the respective interrupt sources.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Table 7-2. Signals Setting Interrupt Request Flags Interrupt Request Signal Setting Interrupt Request Flag Flag IRQBT Set by reference time interval signal from basic interval timer Interrupt Enable Flag IEBT watchdog timer IRQ0 Set by detection of edge of INT0/P61 pin input signal.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Figure 7-3. Interrupt Priority Select Register Address FB2H 3 2 1 0 IPS3 IPS2 IPS1 IPS0 Symbol IPS Selection of higher-priority interrupts 0 0 0 No interrupts are handled as higher-priority interrupts. 0 0 1 VRQ1 Vectored interrupt (INTBT) on left is selected as VRQ2 higher priority. 0 1 0 (INT0) 0 1 1 1 0 0 1 0 1 1 1 0 Setting prohibited Note VRQ5 Vectored interrupt (INTT0) on left is selected as VRQ6 higher priority.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (3) Hardware of INT0 (a) Figure 7-4 shows the configuration of INT0, which is an external interrupt input that can be detected at the rising or falling edge depending on the specification. INT0 also has a noise elimination function which uses a sampling clock (refer to Figure 7-5 I/O Timing of Noise Eliminator). The noise eliminator eliminates a pulse having a width narrower than 2 cyclesNote of the sampling clock as noise.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Selector Figure 7-4. Configuration of INT0 Edge detector INT0 (IRQ0 set signal) Noise eliminator INT0/P61 IM02 IM00, IM01 IM03 Selector IM0 Φ fX/64 Input buffer Specifies edge to be detected. Selects sampling clock. 4 Internal bus Note Even if fX/64 is selected, the HALT mode cannot be released by INT0. Figure 7-5.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Figure 7-6.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (4) Interrupt status flag The interrupt status flags (IST0 and IST1) indicate the status of the processing currently being executed by the CPU and are included in PSW. The interrupt priority controller controls nesting of interrupts according to the contents of these flags as shown in Table 7-3. Because IST0 and IST1 can be changed by using a 4-bit or bit manipulation instruction, interrupts can be nested with the status under execution changed.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.4 Interrupt Sequence When an interrupt occurs, it is processed according to the procedure illustrated below. Figure 7-7.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.5 Nesting Control of Interrupts The µPD754244 can nest interrupts by the following two methods. (1) Nesting with interrupt having high priority specified This method is the standard nesting method of the µPD754244. One interrupt source is selected and nested.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (2) Nesting by changing interrupt status flags Nesting can be implemented if the interrupt status flags are changed by program. In other words, nesting is enabled when IST1 and IST0 are cleared to “0, 0” by an interrupt servicing program, and status 0 is set. This method is used to nest two or more interrupts, or to implement nesting level 3 or higher. Before changing IST1 and IST0, disable interrupts by using the DI instruction. Figure 7-9.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.6 Servicing of Interrupts Sharing Vector Address Because interrupt sources INTT1 and INTT2 share vector tables, you should select one or both of the interrupt sources in the following way. (1) To use one interrupt Of the two interrupt sources sharing a vector table, set the interrupt enable flag of the necessary interrupt source to “1”, and clear the interrupt enable flag of the other interrupt source to “0”.
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CHAPTER 7 1. To use both INTT1 and INTT2 as having higher priority, and give priority to INTT2 DI IRQT2 BR VSUBBT ; IRQT2=1? ...... SKTCLR Service routine of INTT2 EI ... RETI : IRQT1 ......... VSUBBT: CLR1 Service routine of INTT1 EI RETI 2. To use both INTT1 and INTT2 as having lower priority, and give priority to INTT2 IRQT2 BR VSUBBT ............... SKTCLR ; IRQT2 =1? Service routine of INTT2 ... RETI VSUBBT: CLR1 .........
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.7 Machine Cycles Until Interrupt Servicing The number of machine cycles required from when an interrupt request flag (IRQxxx) has been set until the interrupt routine is executed is as follows. (1) If IRQxxx is set while interrupt control instruction is being executed If IRQxxx is set while an interrupt control instruction is being executed, the next instruction is executed.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (2) If IRQxxx is set while instruction other than (1) is executed (a) If IRQxxx is set at the last machine cycle of the instruction under execution In this case, the one instruction following the instruction under execution is executed, three machine cycles of interrupt servicing is performed, and then the interrupt routine is executed.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.8 Effective Usage of Interrupts Use the interrupt function effectively as follows. (1) Use different register banks for the normal routine and interrupt routine. The normal routine uses register banks 2 and 3 with RBE = 1 and RBS = 2. For the interrupt service routine for one nested interrupt, use register bank 0 with RBE = 0, so that you do not have to save or restore the registers.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (1) Enabling or disabling interrupt
<1> Reset . . . <2> EI IE0 EI IET1 <3> EI . . . . . . <4> DI IE0 . . . . . . <5> DI . . . . . . . . . . . . . . . . Disables interrupts Enables INT0 and INTT1 Enables INTT1 Disables interrupts <1> All the interrupts are disabled by the RESET signal. <2> An interrupt enable flag is set by the EI IE××× instruction. At this stage, the interrupts are still disabled.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (2) Example of using INTBT and INT0 (falling edge active): not nested (all interrupts have higher priority)
Reset <1> SEL RB2 <2> MOV MOV A, #1 ; RBE = 1, MBE = 0 IM0, A CLR1 IRQ0 IEBT <3> EI EI IE0 EI EI . . . . . . . . . . . . . . . . . . . . . . . . . Status (INT0 servicing program) ; RBE = 0 IET0 <4> INT0 Status 1 <5> RETI Status 0 <1> All the interrupts are disabled by the RESET signal and status 0 is set.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (3) Nesting of interrupts with higher priority (INTBT has higher priority and INTT0 and INTT2 have lower priority) ; RBE = 1, MBE = 0 Reset SEL EI EI EI <1> MOV MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (4) Executing pending interrupt - interrupt input while interrupts are disabled -
Reset EI <2> <4> IE0 . . . . . . . . . . . . EI . . . . . . . . . . . . . . . . . . . . EI . . . . . . . . . . . . . . . . . . . . <1> INT0 <3> INTT0 RETI IET0 RETI <1> The request flag is held pending even if INT0 is set while the interrupts are disabled.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (5) Executing pending interrupt - two interrupts with lower priority occur simultaneously -
Reset EI EI EI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (6) Executing pending interrupt - interrupt occurs during interrupt service (INTBT has higher priority and INTT0 and INTT2 have lower priority) -
Reset EI IEBT EI IET0 EI IET2 MOV A, #9 MOV IPS, A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2> INTT2 PUSH rp . . . . . . .
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS (7) Enabling nesting of two interrupts - INTT0 and INT0 are nested doubly and INTBT and INTT2 are nested singly -
Reset EI EI IET0 IE0 EI EI EI IEBT IET2 Status 0 <2> DI CLR1 DI DI <1> INTBT Status 1 IST0 IEBT IET2 EI Status 0 Status 0 <3> INTT0 Status 1 <4> RETI Status 0 <5> EI IEBT EI IET2 RETI <1> When an INTBT that does not enable nesting occurs, the INTBT servicing routine is sta
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 7.10 Test Function 7.10.1 Types of test sources The µPD754244 has a test source, INT2. INT2 is an edge-detection testable input. Table 7-5. Types of Test Sources Test Source INT2 Internal/External (detects falling edge of input to KR4 to KR7 pins) External 7.10.2 Hardware controlling test function (1) Test request and test enable flags The test request flag (IRQ2) is set to “1” when a test request is generated (INT2).
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Figure 7-10.
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CHAPTER 7 INTERRUPT AND TEST FUNCTIONS Figure 7-11. Format of INT2 Edge Detection Mode Register (IM2) Address 3 2 1 0 FB6H 0 0 IM21 IM20 Symbol IM2 IM21 IM20 0 0 Assigned nothing 0 1 Inputs falling edge of any of KR4/P70 to KR7/P73 pin INT2 test source Test input pin – KR4-KR7 Setting prohibited Other Cautions1. If the contents of the edge detection mode register are changed, the test request flag may be set. Disable the test input before changing the contents of the mode register.
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CHAPTER 8 STANDBY FUNCTION The µPD754244 possesses a standby function that reduces the power consumption of the system. This standby function can be implemented in the following two modes. • STOP mode • HALT mode The functions of the STOP and HALT modes are as follows. (1) STOP mode In this mode, the system clock oscillator is stopped and therefore the entire system is stopped. The power consumption of the CPU is substantially reduced.
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CHAPTER 8 STANDBY FUNCTION 8.1 Settings and Operating Statuses of Standby Mode Table 8-1.
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CHAPTER 8 STANDBY FUNCTION The STOP mode is set by the STOP instruction, and the HALT mode is set by the HALT instruction (the STOP and HALT instructions respectively set bits 3 and 2 of PCC). Be sure to write a NOP instruction after the STOP and HALT instructions.
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CHAPTER 8 STANDBY FUNCTION 8.2 Releasing Standby Mode Both the STOP and HALT modes can be released when an interrupt request signal occurs that is enabled by the corresponding interrupt enable flag, or when the RESET signal is asserted. Furthermore, STOP mode can be released without altering the interrupt enable flag, when the KRREN pin is high, by using a falling edge input (key return reset) at the KRn pin. Figure 8-1 illustrates how each mode is released. Figure 8-1.
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CHAPTER 8 STANDBY FUNCTION Figure 8-1. Releasing Standby Mode (2/2) (c) Releasing HALT mode by RESET signal HALT Note Wait instruction RESET signal Operation mode Operation mode HALT mode Oscillates Clock (d) Releasing HALT mode by interrupt HALT instruction Standby release signal Operation mode Clock HALT mode Operation mode Oscillates Note µPD754244: The following two times can be selected by mask option. 217/fX (21.8 ms at 6.0 MHz, 31.3 ms at 4.19 MHz) 215/fX (5.46 ms at 6.0 MHz, 7.
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CHAPTER 8 STANDBY FUNCTION <3> Clear again the IRQ used to release STOP mode to enter STOP mode. In this STOP mode, IRQ of the selected interrupt is set and HALT mode is entered. Then, after a wait time, the system returns to the normal operating mode. In the case of the µPD754244, when the STOP mode has been released by an interrupt, the wait time is determined by the setting of BTM (refer to Table 8-2).
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CHAPTER 8 STANDBY FUNCTION Figure 8-3. STOP Mode Release by Key Return Reset or RESET Input IE×××←0 STOP Key return reset or RESET input NOP The differences between release by a key return reset and release by RESET input are as follows.
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CHAPTER 8 STANDBY FUNCTION 8.3 Operation After Release of Standby Mode (1) When the standby mode has been released by the RESET signal, the normal reset operation is performed. (2) When the standby mode has been released by an interrupt, whether or not a vectored interrupt is executed when the CPU has resumed instruction execution is determined by the contents of the interrupt master enable flag (IME).
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CHAPTER 8 STANDBY FUNCTION (1) Application example of STOP mode (when using the µPD754244 at fX = 6.0 MHz) • The STOP mode is set at the falling edge of INT0 and released at the rising edge. • All the I/O ports go into a high-impedance state (if the pins are externally processed so that the current consumption is reduced in a high-impedance state). • Interrupts INTBT and INTT0 are used in the program.
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CHAPTER 8 STANDBY FUNCTION (INT0 servicing program, MBE = 0) VSUB0: WAIT: SKT PORT6.1 ; P61 = 1? BR PDOWN ; Power down SET1 BTM.3 ; Power on SKT IRQBT ; Waits for 21.8 ms BR WAIT SKT PORT6.1 BR PDOWN MOV A, #0011B MOV PCC, A ; Sets high-speed mode MOV XA.
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CHAPTER 8 STANDBY FUNCTION (2) Application example of HALT mode (when using the µPD754244 at fX = 6.0 MHz) • The standby mode is set at the falling edge of INT0 and released at the rising edge. • In the standby mode, an intermittent operation is performed at intervals of 175 ms (INTBT). • INT0 and INTBT are assigned a lower priority. • The slowest CPU clock is selected in the standby mode.
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CHAPTER 8 STANDBY FUNCTION BTAND4: WAIT: SKTCLR IRQ0 ; INT0 = 1? BR VSUBBT ; NO SKT PORT6.1 ; P61 = 1? BR PDOWN ; Power down SET1 BTM.3 ; Starts BT SKT IRQBT ; Waits for 175 ms BR WAIT SKT PORT6.1 BR PDOWN MOV A, #0011B MOV PCC, A [EI IEn] ; IEn ← 1 MOV A, #0 ; Lowest-speed mode MOV PCC, A [DI IEn] ; High-speed mode RETI PDOWN: ; IEn ← 0 Keeps 46 machine cycles SETHLT: HALT ; HALT mode NOP RETI CLR1 IRQBT ...........................
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CHAPTER 9 RESET FUNCTION 9.1 Configuration and Operation of Reset Function Three types of reset signals are used: the external reset signal (RESET), a reset signal from the basic interval timer/watchdog timer, and a key return reset. When any one of these reset signals is input, the internal reset signal is asserted. Figure 9-1 shows the configuration of the reset circuit. Figure 9-1.
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CHAPTER 9 RESET FUNCTION Figure 9-2. Reset Operation by RESET Signal WaitNote RESET signal Operation mode or standby mode HALT mode Internal reset operation Note µPD754244: The following two times can be selected by the mask option. 217/fX (21.8 ms at 6.0 MHz, 31.3 ms at 4.19 MHz) 215/fX (5.46 ms at 6.0 MHz, 7.81 ms at 4.19 MHz) µPD754144: The wait time is fixed to 56/fCC (56 µs at 1.0 MHz).
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CHAPTER 9 RESET FUNCTION Table 9-1.
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CHAPTER 9 RESET FUNCTION Table 9-1.
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CHAPTER 9 RESET FUNCTION 9.2 Watchdog Flag (WDF), Key Return Flag (KRF) WDF and KRF are mapped to bit 2 and 3 of address FC6H respectively. The contents of WDF and KRF are undefined initially, but they are initialized to “0” by external RESET signal generation. WDF is cleared by a watchdog timer overflow signal, and KRF is set by a reset signal generated by the KRn pin. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal is generated.
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CHAPTER 9 RESET FUNCTION Figure 9-4.
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CHAPTER 10 MASK OPTIONS The µPD754144 and 754244 have the following mask options. Table 10-1. Selection of Mask Options µPD754144 Item µPD754244 P70/KR4 to P73/KR7 On-chip pull-up resistors specifiable in 1-bit units by mask option RESET pin On-chip pull-up resistors specifiable by mask option Oscillation stabilization wait time Fixed to 56/fCC Selectable from 217/fX and 215/fX 10.1 Pin Mask Options 10.1.1 Mask option of P70/KR4 to P73/KR7 On-chip 100 kΩ (typ.
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CHAPTER 11 INSTRUCTION SET The instruction set of the µPD754244 is based on the instruction set of the 75X Series and therefore maintains compatibility with the 75X Series, but with the following improved features.
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CHAPTER 11 INSTRUCTION SET 11.1.2 Bit manipulation instruction The µPD754244 has reinforced bit test, bit transfer, and bit Boolean (AND, OR, and XOR) instructions, in addition to the ordinary bit manipulation (set and clear) instructions. The bit to be manipulated is specified in the bit manipulation addressing mode. Three types of bit manipulation addressing modes can be used. The bits manipulated in each addressing mode are shown in Table 11-1. Table 11-1.
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CHAPTER 11 11.1.4 INSTRUCTION SET Base number adjustment instruction Some applications require that the result of addition or subtraction of 4-bit data (which is carried out in binary) be converted into a decimal number or into a number with a base of 6, such as time. Therefore, the µPD754244 is provided with base number adjustment instructions that adjust the result of addition or subtraction of 4-bit data into a number with any base.
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CHAPTER 11 INSTRUCTION SET 11.1.5 Skip instruction and number of machine cycles required for skipping The instruction set of the µPD754244 configures a program where instructions may be or may not be skipped if a given condition is satisfied. If a skip condition is satisfied when a skip instruction is executed, the instruction next to the skip instruction is skipped and the instruction after next is executed.
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CHAPTER 11 INSTRUCTION SET Representation Description reg X, A, B, C, D, E, H, L reg1 X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 BC, DE, HL rp2 BC, DE rp' XA, BC, DE, HL, XA', BC', DE', HL' rp'1 BC, DE, HL, XA', BC', DE', HL' rpa HL, HL+, HL–, DE, DL rpa1 DE, DL n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or labelNote bit 2-bit immediate data or label fmem Immediate data FB0H to FBFH, FF0H to FFFH or label pmem Immediate data FC0
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CHAPTER 11 INSTRUCTION SET (2) Conventions for explanation of operation A: A register; 4-bit accumulator B: B register C: C register D: D register E: E register H: H register L: L register X: X register XA: Register pair (XA); 8-bit accumulator BC: Register pair (BC) DE: Register pair (DE) HL: Register pair (HL) XA’: Expansion register pair (XA’) BC’: Expansion register pair (BC’) DE’: Expansion register pair (DE’) HL’: Expansion register pair (HL’) PC: Program counter SP
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CHAPTER 11 INSTRUCTION SET (3) Symbols in addressing area field *1 MB = MBE .
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CHAPTER 11 INSTRUCTION SET (4) Explanation of machine cycle field S indicates the number of machine cycles required for an instruction with skip to execute the skip operation. The value of S varies as follows. • When skip is executed .............................................................................. S = 0 • When 1- or 2-byte instruction is skipped ................................................. S = 1 • When 3-byte instructionNote is skipped ..............................................
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CHAPTER 11 Instructions Transfer 242 Machine Operation Addressing Mnemonic Operand MOV A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L + 1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L – 1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, m
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CHAPTER 11 Instructions Table MOVT XA, @PCDE 1 3 XA ← (PC11-8 + DE)ROM XA, @PCXA 1 3 XA ← (PC11-8 + XA)ROM XA, @BCDE 1 3 XA ← (BCDE)ROMNote *6 XA, @BCXA 1 3 XA ← (BCXA)ROMNote *6 CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7-2 + L3-2.bit(L1-0)) *5 CY, @H+mem.bit 2 2 CY ← (H + mem3-0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← CY *5 @H+mem.bit, CY 2 2 (H + mem3-0.
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CHAPTER 11 Machine Mnemonic Operand Accumulator RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An manipulation NOT A 2 2 A←A Increment/ INCS reg 1 1+S reg ← reg + 1 reg = 0 rp1 1 1+S rp1 ← rp1 + 1 rp1 = 00H @HL 2 2+S (HL) ← (HL) + 1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem) + 1 *3 (mem) = 0 reg 1 1+S reg ← reg – 1 reg = FH rp' 2 2+S rp' ← rp' – 1 rp' = FFH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip i
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CHAPTER 11 Instructions INSTRUCTION SET Machine Operand Bytes AND1 CY, fmem.bit 2 2 CY ← CY (fmem.bit) *4 manipula- CY, pmem.@L 2 2 CY ← CY (pmem7-2 + L3-2.bit(L1-0)) *5 tion CY, @H + mem.bit 2 2 CY ← CY (H + mem3-0.bit) *1 CY, fmem.bit 2 2 CY ← CY (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY (pmem7-2 + L3-2.bit(L1-0)) *5 CY, @H + mem.bit 2 2 CY ← CY (H + mem3-0.bit) *1 CY, fmem.bit 2 2 CY ← CY (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY (pmem7-2 + L3-2.
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CHAPTER 11 Instructions Subrou- Mnemonic Operand CALLANote !addr1 Bytes 3 Machine Cycle 3 INSTRUCTION SET Operation (SP–6) (SP–3) (SP–4) ← PC11-0 Addressing Area Skip Condition *11 (SP–5) ← 0, 0, 0, 0 tine/stack (SP–2) ← ×, ×, MBE, RBE control PC11-0 ← addr1, SP ← SP – 6 CALLNote !addr 3 3 (SP–4) (SP–1) (SP–2) ← PC11-0 *6 (SP–3) ← MBE, RBE, 0 PC11-0 ← addr, SP ← SP – 4 4 (SP–6) (SP–3) (SP–4) ← PC11-0 (SP–5) ← 0, 0, 0, 0 (SP–2) ← ×, ×, MBE, RBE PC11-0 ← addr, SP ← SP – 6 CALLFNote !fa
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CHAPTER 11 Instructions Subrou- control Interrupt Machine Addressing Mnemonic Operand PUSH rp 1 1 (SP – 1) (SP – 2) ← rp, SP ← SP – 2 BS 2 2 (SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP–2 rp 1 1 rp ← (SP + 1) (SP), SP ← SP + 2 BS 2 2 MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2 2 2 IME (IPS.3) ← 1 2 2 IE××× ← 1 2 2 IME (IPS.
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CHAPTER 11 INSTRUCTION SET 11.
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CHAPTER 11 INSTRUCTION SET (2) Opcode for bit manipulation addressing *1 in the operand field indicates the following three types. • fmem.bit • pmem.@L • @H+mem.bit The second byte *2 of the opcode corresponding to the above addressing is as follows. *1 fmem. bit 2nd Byte of Opcode Accessible Bit 1 0 B1 B0 F3 F2 F1 F0 Bit of FB0H to FBFH that can be manipulated 1 1 B1 B0 F3 F2 F1 F0 Bit of FF0H to FFFH that can be manipulated pmem.
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CHAPTER 11 INSTRUCTION SET Opcode Instruction Mnemonic Operand B1 Transfer MOV XCH Table MOVT reference Bit transfer MOV1 A, #n4 0 1 1 1 I3 I2 I1 I0 reg1, #n4 1 0 0 1 1 0 1 0 I3 I2 I1 I0 1 R 2 R 1 R 0 rp, #n8 1 0 0 0 1 P2 P1 1 I7 I6 I5 I4 I3 I2 I1 I0 A, @rpa1 1 1 1 0 0 Q2 Q1 Q0 XA, @HL 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 @HL, A 1 1 1 0 1 0 0 0 @HL, XA 1 0 1 0 1 0 1 0 0 0 0 1 0 0 0 0 A, mem 1 0 1 0 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 XA, mem 1 0 1 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 0 mem,
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CHAPTER 11 INSTRUCTION SET Opcode Instruction Mnemonic Operand B1 Operation ADDS A, #n4 0 1 1 0 I3 I2 I1 I0 XA, #n8 1 0 1 1 1 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0 A, @HL 1 1 0 1 0 0 1 0 XA, rp' 1 0 1 0 1 0 1 0 1 1 0 0 1 P2 P1 P0 rp'1, XA 1 0 1 0 1 0 1 0 1 1 0 0 0 P2 P1 P0 A, @HL 1 0 1 0 1 0 0 1 XA, rp' 1 0 1 0 1 0 1 0 1 1 0 1 1 P2 P1 P0 rp'1, XA 1 0 1 0 1 0 1 0 1 1 0 1 0 P2 P1 P0 A, @HL 1 0 1 0 1 0 0 0 XA, rp' 1 0 1 0 1 0 1 0 1 1 1 0 1 P2 P1 P0 rp'1, XA 1 0 1 0 1 0 1 0 1 1 1 0 0 P2 P1 P
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CHAPTER 11 INSTRUCTION SET Opcode Instruction Mnemonic Operand B1 Increment/ INCS reg 1 1 0 0 0 R2 R1 R0 rp1 1 0 0 0 1 P2 P1 P0 @HL 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 mem 1 0 0 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 reg 1 1 0 0 1 R2 R1 R0 rp' 1 0 1 0 1 0 1 0 0 1 1 0 1 P2 P1 P0 reg, #n4 1 0 0 1 1 0 1 0 I3 I2 I1 I0 0 R 2 R 1 R 0 @HL, #n4 1 0 0 1 1 0 0 1 0 1 1 0 I3 I2 I1 I0 A, @HL 1 0 0 0 0 0 0 0 XA, @HL 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 A, reg 1 0 0 1 1 0 0 1 0 0 0 0 1 R2 R1 R0 XA, rp' 1 0
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CHAPTER 11 INSTRUCTION SET Opcode Instruction Mnemonic Operand B1 Branch BR !addr B2 1 0 1 0 1 0 1 1 0 0 B3 addr (+2) (–1) ~ $addr1 ~ (+16) (–15) Subroutine/stack control 1 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 PCXA 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 BCDE 1 0 0 1 1 0 0 1 0 0 0 0 0 1 0 1 BCXA 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 BRA !addr1 1 0 1 1 1 0 1 0 0 BRCB !caddr 0 1 0 1 CALLA !addr1 1 0 1 1 1 0 1 1 0 CALL !addr 1 0 1 0 1 0 1 1 0 1 CALLF !faddr 0 1 0 0 0 RET 1 1 1 0 1 1 1 0 RE
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CHAPTER 11 INSTRUCTION SET 11.4 Instruction Function and Application This section describes the functions and applications of the respective instructions. The instructions that can be used and the functions of the instructions differ between the MkI and MkII modes of the µPD754144, and 754244. Read the descriptions on the following pages according to the following guidance. How to read : This instruction can be used commonly in the MkI and MkII modes of the µPD754144 and 754244.
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CHAPTER 11 INSTRUCTION SET 11.4.1 Transfer instructions MOV A, #n4 Function: A ← n4 n4 = I3-0: 0-FH Transfers 4-bit immediate data n4 to the A register (4-bit accumulator). This instruction has a string effect (group A), and if MOV A, #n4 or MOV XA, #n8 follows this instruction, the string-effect instruction following the instruction executed is processed as NOP.
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CHAPTER 11 INSTRUCTION SET MOV A, @HL Function: A ← (HL) Transfers the contents of the data memory content addressed by register pair HL is transferred to the A register. MOV A, @HL+ Function: A ← (HL), L ← L+1 skip if L = 0H Transfers the contents of the data memory addressed by register pair HL to the A register. Then, the contents of the L register are automatically incremented by one, and if the contents of the L register become 0H as a result, the next instruction is skipped.
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CHAPTER 11 INSTRUCTION SET MOV XA, @HL Function: A ← (HL), X ← (HL+1) Transfers the contents of the data memory addressed by register pair HL to the A register, and the contents of the next memory address to the X register. If the contents of the L register are a odd number, an address whose least significant bit is ignored is transferred.
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CHAPTER 11 INSTRUCTION SET MOV mem, A Function: (mem) ← A mem = D7-0: 00H to FFH Transfers the contents of the A register to the data memory addressed by 8-bit immediate data mem. MOV mem, XA Function: (mem) ← A, (mem+1) ← X mem = D7-0: 00H to FEH Transfers the contents of the A register to the data memory addressed by 8-bit immediate data mem and the contents of the X register to the next memory address. The address that can be specified by mem is an even address.
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CHAPTER 11 INSTRUCTION SET XCH A, @HL Function: A ↔ (HL) Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL. XCH A, @HL+ Function: A ↔ (HL), L ← L+1 skip if L = 0H Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL. Then, the contents of the L register are automatically incremented by one, and if the contents of the L register become 0H as a result, the next instruction is skipped.
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CHAPTER 11 INSTRUCTION SET XCH XA, @HL Function: A ↔ (HL), X ↔ (HL+1) Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL, and the contents of the X register with the contents of the next address. If the contents of the L register are an odd number, however, an address whose least significant bit is ignored is specified.
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CHAPTER 11 INSTRUCTION SET 11.4.2 Table reference instructions MOV XA, @PCDE Function: XA ← ROM (PC11-8+DE) Transfers the lower 4 bits of the table data in the program memory addressed when the lower 8 bits (PC7-0) of the program counter (PC) are replaced with the contents of register pair DE, to the A register, and the higher 4 bits to the X register. The table address is determined by the contents of the program counter (PC) when this instruction is executed.
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CHAPTER 11 INSTRUCTION SET Caution The MOVT XA, @PCDE instruction usually references the table data in page where the instruction exists. If the instruction is at address ××FFH, however, the table data in the next page is referenced instead of the table data in the page where the instruction exists.
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CHAPTER 11 INSTRUCTION SET MOVT XA, @PCXA Function: XA ← ROM (PC11-8+XA) Transfers the lower 4 bits of the table data in the program memory addressed when the lower 8 bits (PC7-0) of the program counter (PC) are replaced with the contents of register pair XA, to the A register, and the higher 4 bits to the X register. The table address is determined by the contents of the PC when this instruction is executed.
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CHAPTER 11 INSTRUCTION SET MOVT XA, @BCXA Function: XA ← ROM (BCXA) Transfers the lower 4 bits of the table data (8-bit) in the program memory addressed by the B register and the contents of registers C, X, and A, to the A register, and the higher 4 bits to the X register. However, on the µPD754244, register B is invalid. Be sure to set register B to 0000B. The necessary data must be programmed to the table area in advance by using an assembler directive (DB instruction).
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CHAPTER 11 INSTRUCTION SET 11.4.3 Bit transfer instructions MOV1 CY, fmem.bit MOV1 CY, pmem.@L MOV1 CY, @H+mem.bit Function: CY ← (bit specified by operand) Transfers the contents of the data memory addressed in the bit manipulating addressing mode (fmem.bit, pmem.@L, or @H+mem.bit) to the carry flag (CY). MOV1 fmem.bit, CY MOV1 pmem.@L, CY MOV1 @H+mem.
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CHAPTER 11 11.4.4 INSTRUCTION SET Operation instructions ADDS A, #n4 Function: A ← A+n4; Skip if carry. n4 = l3-0: 0 to FH Adds 4-bit immediate data n4 to the contents of the A register. If a carry occurs as a result, the next instruction is skipped. The carry flag is not affected. If this instruction is used in combination with ADDC A, @HL or SUBC A, @HL instruction, it can be used as a base number adjustment instruction (refer to 11.1.4 Base number adjustment instruction).
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CHAPTER 11 INSTRUCTION SET ADDC A, @HL Function: A, CY ← A+ (HL) +CY Adds the contents of the data memory addressed by register pair HL to the contents of the A register, including the carry flag. If a carry occurs as a result, the carry flag is set; if not, the carry flag is reset. If the ADDS A, #n4 instruction is placed next to this instruction, and if a carry occurs as a result of executing this instruction, the ADDS A, #n4 instruction is skipped.
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CHAPTER 11 INSTRUCTION SET SUBS XA, rp’ Function: XA ← XA – rp’; Skip if borrow. Subtracts the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) from the contents of register pair XA, and sets the result to register pair XA. If a borrow occurs as a result, the next instruction is skipped. The carry flag is not affected.
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CHAPTER 11 INSTRUCTION SET SUBC rp’1, XA Function: rp’1, CY ← rp’1 – XA – CY Subtracts the contents of register pair XA from the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or BC’), including the carry flag, and sets the result to specified register pair rp’1. If a borrow occurs as a result, the carry flag is set; if not, the carry flag is reset.
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CHAPTER 11 INSTRUCTION SET OR A, #n4 Function: A ← A n4 n4 = l3-0: 0-FH ORs 4-bit immediate data n4 with the contents of the A register, and sets the result to the A register. Application example To set the lower 3 bits of the accumulator to 1 OR A, #0111B OR A, @HL Function: A ← A (HL) ORs the contents of the data memory addressed by register pair HL with the contents of the A register, and sets the result to the A register.
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CHAPTER 11 INSTRUCTION SET XOR A, @HL Function: A ← A (HL) Exclusive-ORs the contents of the data memory addressed by register pair HL with the contents of the A register, and sets the result to the A register. XOR XA, rp’ Function: XA ← XA rp’ Exclusive-ORs the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) with the contents of register pair XA, and sets the result to register pair XA.
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CHAPTER 11 INSTRUCTION SET 11.4.5 Accumulator manipulation instructions RORC A Function: CY ← A0, An-1 ← An, A3 ← CY (n = 1-3) Rotates the contents of the A register (4-bit accumulator) 1 bit to the left with the carry flag. A .. .. Before execution CY 3 2 1 0 0 0 1 0 1 1 0 0 1 0 RORC A After execution NOT A Function: A ← A Takes 1’s complement of the A register (4-bit accumulator) (inverts the bits of the accumulator).
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CHAPTER 11 INSTRUCTION SET 11.4.6 Increment/decrement instructions INCS reg Function: reg ← reg+1; Skip if reg = 0 Increments the contents of register reg (X, A, H, L, D, E, B, or C). If reg = 0 as a result, the next instruction is skipped. INCS rp1 Function: rp1 ← rp1+1; Skip if rp1 = 00H Increments the contents of register pair rp1 (HL, DE, or BC). If rp1 = 00H as a result, the next instruction is skipped.
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CHAPTER 11 INSTRUCTION SET 11.4.7 Compare instructions SKE reg, #n4 Function: Skip if reg = n4 n4 = I3-0: 0-FH Skips the next instruction if the contents of register reg (X, A, H, L, D, E, B, or C) are equal to 4-bit immediate data n4. SKE @HL, #n4 Function: Skip if (HL) = n4 n4 = I3-0: 0-FH Skips the next instruction if the contents of the data memory addressed by register pair HL are equal to 4-bit immediate data n4.
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CHAPTER 11 11.4.8 INSTRUCTION SET Carry flag manipulation instructions SET1 CY Function: CY ← 1 Sets the carry flag. CLR1 CY Function: CY ← 0 Clears the carry flag. SKT CY Function: Skip if CY = 1 Skips the next instruction if the carry flag is 1. NOT1 CY Function: CY ← CY Inverts the carry flag. Therefore, sets the carry flag to 1 if it is 0, and clears the flag to 0 if it is 1.
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CHAPTER 11 INSTRUCTION SET 11.4.9 Memory bit manipulation instructions SET1 mem.bit Function: (mem.bit) ← 1 mem = D7-0: 00H to FFH, bit = B1-0: 0-3 Sets the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem. SET1 fmem.bit SET1 pmem.@L SET1 @H+mem.bit Function: (bit specified by operand) ← 1 Sets the bit of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@L, or @H+mem.bit). CLR1 mem.bit Function: (mem.
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CHAPTER 11 INSTRUCTION SET SKT fmem.bit SKT pmem.@L SKT @H+mem.bit Function: Skip if (bit specified by operand) = 1 Skips the next instruction if the bit of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@L, or @H+mem.bit) is 1. SKF mem.bit Function: Skip if (mem.bit) = 0 mem = D7-0: 00H to FFH, bit = B1-0: 0-3 Skips the next instruction if the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem is 0. SKF fmem.bit SKF pmem.
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CHAPTER 11 INSTRUCTION SET AND1 CY, fmem.bit AND1 CY, pmem.@L AND1 CY, @H+mem.bit Function: CY ← CY (bit specified by operand) ANDs the content of the carry flag with the contents of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@L, or @H+mem.bit), and sets the result to the carry flag. OR1 CY, fmem.bit OR1 CY, pmem.@L OR1 CY, @H+mem.
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CHAPTER 11 11.4.10 INSTRUCTION SET Branch instructions I BR addr Function: PC11-0 ← addr addr = 0000H to 0FFFH Branches to an address specified by immediate data addr. This instruction is an assembler directive and is replaced by the assembler at assembly time with the optimum instruction from the BR !addr, BRCB !caddr, and BR $addr instructions. II BR addr1 Function: PC11-0 ← addr1 addr1 = 0000H to 0FFFH Branches to an address specified by immediate data addr1.
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CHAPTER 11 II Function: INSTRUCTION SET BR $addr1 PC11-0 ← addr1 addr1 = (PC–15) to (PC–1), (PC+2) to (PC+16) This is a relative branch instruction that has a branch range of (–15 to –1) and (+2 to +16) from the current address. It is not affected by a page boundary or block boundary. BRCB !caddr Function: PC11-0 ← caddr11-0 caddr = 0000H to 0FFFH Branches to an address specified by the program counter (PC11-0) replaced with 12-bit immediate data caddr.
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CHAPTER 11 INSTRUCTION SET BR PCDE Function: PC11-0 ← PC11-8 + DE PC7-4 ← D, PC3-0 ← E Branches to an address specified by the lower 8 bits of the program counter (PC7-0) replaced with the contents of register pair DE. The higher bits of the program counter are not affected. Caution The BR PCDE instruction usually branches execution to the page where the instruction exists. If the first byte of the op code is at address ××FE or ××FFH, however, execution does not branch in that page, but to the next page.
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CHAPTER 11 INSTRUCTION SET BR BCDE Function: PC11-0 ← BCDE Example To branch to an address specified by the contents of the program counter replaced by the contents of registers B, C, D, and E However, the PC of the µPD754244 is 12 bits. The contents of PC are replaced by the contents of registers C, D and E. Always set register B to 0000B.
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CHAPTER 11 INSTRUCTION SET 11.4.
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CHAPTER 11 I/II INSTRUCTION SET CALLF !faddr Function: [MkI mode] (SP–1) ← PC7-4, (SP–2) ← PC3-0 (SP–3) ← MBE, RBE, 0, 0 (SP–4) ← PC11-8, SP ← SP–4 PC11-0 ← 0+faddr faddr = 0000H to 07FFH [MkII mode] (SP–2) ← ×, ×, MBE, RBE (SP–3) ← PC7-4, (SP–4) ← PC3-0 (SP–5) ← 0, 0, 0, 0, (SP–6) ← PC11-8 SP ← SP–6 PC11-0 ← 0+faddr faddr = 0000H to 07FFH Saves the contents of the program counter (return address), MBE, and RBE to the data memory (stack) addressed by the stack pointer (SP), decrements the SP, and then b
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CHAPTER 11 I/II INSTRUCTION SET RET Function: [MkI mode] PC11-8 ← (SP), MBE, RBE, 0, 0 ← (SP+1) PC3-0 ← (SP+2) PC7-4 ← (SP+3), SP ← SP+4 [MkII mode] PC11-8 ← (SP), 0, 0, 0, 0 ← (SP+1) PC3-0 ← (SP+2), PC7-4 ← (SP+3) ×, ×, MBE, RBE ← (SP+4), SP ← SP+6 Restores the contents of the data memory (stack) addressed by the stack pointer (SP) to the program counter (PC), memory bank enable flag (MBE), and register bank enable flag (RBE), and then increments the contents of the SP.
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CHAPTER 11 INSTRUCTION SET PUSH rp Function: (SP–1) ←rpH, (SP–2) ← rpL, SP ← SP–2 Saves the contents of register pair rp (XA, HL, DE, or BC) to the data memory (stack) addressed by the stack pointer (SP), and then decrements the contents of the SP. The higher 4 bits of the register pair (rpH, X, H, D, or B) are saved to the stack addressed by (SP–1), and the lower 4 bits (rpL: A, L, E, or C) are saved to the stack addressed by (SP–2).
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CHAPTER 11 INSTRUCTION SET 11.4.12 Interrupt control instructions EI Function: IME (IPS.3) ← 1 Sets the interrupt mask enable flag (bit 3 of the interrupt priority select register) to “1” to enable interrupts. Acknowledging an interrupt is controlled by an interrupt enable flag corresponding to the interrupt. EI IE××× Function: IE××× ← 1 ××× = N5, N2-0 Sets a specified interrupt enable flag (IE×××) to “1” to enable acknowledging the corresponding interrupt (××× = BT, T0, T1, T2, 0, 2, or EE).
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CHAPTER 11 INSTRUCTION SET 11.4.13 Input/output instructions IN A, PORTn Function: A ← PORTn n = N3-0: 3, 6, 7, 8 Transfers the contents of a port specified by PORTn (n = 3, 6, 7, 8) to the A register. Caution When this instruction is executed, it is necessary that MBE = 0 or (MBE = 1, MBS = 15). n can be 3, 6, 7, 8. The data of the output latch is loaded to the A register in the output mode, and the data of the port pins are loaded to the register in the input mode.
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CHAPTER 11 INSTRUCTION SET 11.4.14 CPU control instruction HALT Function: PCC.2 ← 1 Sets the HALT mode (this instruction sets the bit 2 of the processor clock control register). Caution Make sure that a NOP instruction follows the HALT instruction. STOP Function: PCC.3 ← 1 Sets the STOP mode (this instruction sets the bit 3 of the processor clock control register). Caution Make sure that a NOP instruction follows the STOP instruction. NOP Function: Executes nothing but consumes 1 machine cycle.
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CHAPTER 11 INSTRUCTION SET 11.4.15 Special instructions SEL RBn Function: RBS ← n n = N1-0: 0-3 Sets 2-bit immediate data n to the register bank select register (RBS). SEL MBn Function: MBS ← n n = N3-0: 0, 4, 15 Transfers 4-bit immediate data n to the memory bank select register (MBS).
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CHAPTER 11 INSTRUCTION SET References the 2-byte data at the program memory address specified by (taddr), (taddr+1) and executes it as an instruction. The area of the reference table consists of addresses 0020H to 007FH. Data must be written to this area in advance. Write the mnemonic of a 1-byte or 2-byte instruction as the data as is. When a 3-byte call instruction and 3-byte branch instruction is used, data is written by using an assembler directive (TCALL or TBR).
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CHAPTER 11 INSTRUCTION SET Application example MOV HL, #00H MOV XA, #FFH Replaced by GETI CALL SUB1 BR SUB2 ORG 20H HL00: MOV HL, #00H XAFF: MOV XA, #FFH SUB1 BSUB2: TBR SUB2 GETI HL00 ; MOV HL, #00H GETI BSUB2 ; BR SUB2 GETI CSUB1 ; CALL SUB1 GETI XAFF ; MOV XA, #FFH ......... ......... ......... .........
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APPENDIX A DEVELOPMENT TOOLS The following development tools are available to support development of systems using the µPD754244. With the 75XL Series, a relocatable assembler that can be used in common with any model in the series is used in combination with a device file dedicated to the model being used. Language Processor RA75X relocatable Host machine Order code assembler OS MS-DOSTM PC-9800 series 3.5"2HD µS5A13RA75X 5"2HD µS5A10RA75X 3.5" 2HC µS7B13RA75X 5"2HC µS7B10RA75X ~ Ver.3.
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APPENDIX A DEVELOPMENT TOOLS Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are available as the debugging tools for the µPD754244. The following table shows the system configuration of the in-circuit emulators. IE-75000-RNote1 The IE-75000-R is an in-circuit emulator that debugs the hardware and software of an application system using the 75X Series or 75XL Series.
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APPENDIX A DEVELOPMENT TOOLS OS of IBM PC The following OSs are supported as the OS for IBM PCs. OS PC Version DOSTM Ver.5.02 to Ver.6.3 J6.1/VNote to J6.3/VNote MS-DOS Ver.5.0 to Ver.6.22 5.0/VNote to 6.2/VNote IBM DOSTM J5.02/VNote Note Only the English mode is supported. Caution Although Ver.5.00 or above has a task swap function, this function cannot be used with this software.
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Development Tool Configuration In-circuit emulator IE-75000-R or IE-75001-R Emulation probe Centronics l/F RS-232-C EP-754144GS IE control program Note 2 Target system APPENDIX A DEVELOPMENT TOOLS User’s Manual U10676EJ3V0UM Host machine PC-9800 series lBM PC/AT [Symbolic debugging possible] Emulation board Note 1 IE-75300-R-EM Relocatable assembler + Device file Notes 1. The in-circuit emulator is not provided with IE-75300-R-EM (Sold separately). 2.
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APPENDIX B ORDERING MASK ROM After your program has been developed, you can place an order for mask ROM using the following procedure. <1> Reservation for mask ROM ordering Inform NEC Electronics of when you intend to place an order for the mask ROM. (NEC’s response may be delayed if we are not informed in advance.
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APPENDIX C INSTRUCTION INDEX C.1 Instruction Index (By Function) [Transfer instruction] [Table reference instruction] MOV A, #n4 ... 242, 255 MOVT XA, @PCDE ... 243, 261 MOV reg1, #n4 ... 242, 255 MOVT XA, @PCXA ... 243, 263 MOV XA, #n8 ... 242, 255 MOVT XA, @BCDE ... 243, 263 MOV HL, #n8 ... 242, 255 MOVT XA, @BCXA ... 243, 264 MOV rp2, #n8 ... 242, 255 MOV A, @HL ... 242, 256 [Bit transfer instruction] MOV A, @HL+ ... 242, 256 MOV1 CY, fmem.bit ... 243, 265 MOV A, @HL– ...
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APPENDIX C INSTRUCTION INDEX AND A, @HL ... 243, 269 [Memory bit manipulation instruction] AND XA, rp' ... 243, 269 SET1 mem.bit ... 244, 276 AND rp'1, XA ... 243, 269 SET1 fmem.bit ... 244, 276 OR A, #n4 ... 243, 270 SET1 pmem.@L ... 244, 276 OR A, @HL ... 243, 270 SET1 @H+mem.bit ... 244, 276 OR XA, rp' ... 243, 270 CLR1 mem.bit ... 244, 276 OR rp'1, XA ... 243, 270 CLR1 fmem.bit ... 244, 276 XOR A, #n4 ... 243, 270 CLR1 pmem.@L ... 244, 276 XOR A, @HL ...
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APPENDIX C INSTRUCTION INDEX BR PCXA ... 245, 281 SEL MBn ... 247, 290 BR BCDE ... 245, 282 GETI taddr ... 247, 290 BR BCXA ... 245, 282 BRA !addr1 ... 245, 279 BRCB !caddr ... 245, 280 TBR addr ... 247, 282 [Subroutine/stack control instruction] CALLA !addr1 ... 246, 283 CALL !addr ... 246, 283 CALLF !faddr ... 246, 284 TCALL !addr ... 247, 284 RET ... 246, 285 RETS ... 246, 285 RETI ... 246, 285 PUSH tp ... 247, 286 PUSH BS ... 247, 286 POP rp ... 247, 286 POP BS ...
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APPENDIX C C.2 INSTRUCTION INDEX Instruction Index (Alphabetical Order) [A] CLR1 fmem.bit ... 244, 276 ADDC A, @HL ... 243, 267 CLR1 mem.bit ... 244, 276 ADDC rp'1, XA ... 243, 267 CLR1 pmem.@L ... 244, 276 ADDC XA, rp' ... 243, 267 CLR1 @H+mem.bit ... 244, 276 ADDS A, #n4 ... 243, 266 ADDS A, @HL ... 243, 266 [D] ADDS rp'1, XA ... 243, 266 DECS reg ... 244, 273 ADDS XA, rp' ... 243, 266 DECS rp' ... 244, 273 ADDS XA, #n8 ... 243, 266 DI ... 247, 287 AND A, #n4 ...
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APPENDIX C INSTRUCTION INDEX MOV A, @rpa1 ... 242, 256 OR1 CY, @H+mem.bit ... 245, 278 MOV HL, #n8 ... 242, 255 OUT PORTn, A ... 247, 288 MOV mem, A ... 242, 258 MOV mem, XA ... 242, 258 [P] MOV reg1, A ... 242, 258 POP BS ... 247, 286 MOV reg1, #n4 ... 242, 255 POP rp ... 247, 286 MOV rp'1, XA ... 242, 258 PUSH BS ... 247, 286 MOV rp2, #n8 ... 242, 255 PUSH rp ... 247, 286 MOV XA, mem ... 242, 257 MOV XA, rp' ... 242, 258 [R] MOV XA, #n8 ... 242, 255 RET ...
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APPENDIX C SKT INSTRUCTION INDEX @H+mem.bit ... 244, 277 SKTCLR fmem.bit ... 244, 277 SKTCLR pmem.@L ... 244, 277 SKTCLR @H+mem.bit ... 244, 277 STOP ... 247, 289 SUBC A, @HL ... 243, 268 SUBC rp'1, XA ... 243, 268 SUBC XA, rp' ... 243, 268 SUBS A, @HL ... 243, 267 SUBS rp'1, XA ... 243, 268 SUBS XA, rp' ... 243, 268 [T] TBR addr ... 247, 282 TCALL !addr ... 247, 284 [X] XCH A, mem ... 242, 260 XCH A, reg1 ... 242, 260 XCH A, @HL ... 242, 259 XCH A, @HL+ ...
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APPENDIX D HARDWARE INDEX [B] IRQ2 ... 212 BS ... 78 IRQBT ... 190 BSB0 to BSB3 ... 184 IRQEE ... 82, 190 BT ... 114 IRQT0 ... 190 BTM ... 115 IRQT1 ... 190 IRQT2 ... 190 [C] IST0, IST1 ... 76, 196 CY ... 74 [K] [E] KR4 to KR7 ... 212 ERE ... 81 KRF ... 231 EWC ... 81 KRREN ... 214, 227 EWE ... 81 EWST ... 81 [M] EWTC4 to EWTC6 ... 81 MBE ... 76 MBS ... 78 [I] IE0 ... 190 [N] IE2 ... 212 NRZ ... 133 IEBT ... 190 NRZB ... 133 IEEE ... 82, 190 IET0 ... 190 [P] IET1 ... 190 PC .
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APPENDIX D HARDWARE INDEX [S] SBS ... 61, 70 SK0 to SK2 ... 75 SP ... 70 [T] T0, T1 ... 54 T2 ... 53 TC2 ... 133, 138 TM0 ... 127 TM1 ... 128 TM2 ... 130 TMOD0, TMOD1 ... 54 TMOD2 ... 53 TMOD2H ... 52 TOE0, TOE1 ... 132 TOE2 ... 133 [W] WDF ... 231 WDTM ...
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APPENDIX E REVISION HISTORY The revision history is shown below. “Location” indicates the corresponding chapters in the preceding edition.