Electronics America Network Cables User Manual

CHAPTER 2 V
R
4120A
Preliminary User’s Manual S15543EJ1V0UM
85
Figure 2-10. Instruction Execution in the Pipeline
(Five stages)
Current CPU cycle
PCycle
IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
2.3.1.2 Pipeline activities
(1) MIPS III instruction
Figure 2-11 shows the activities that can occur during each pipeline stage in MIPS III Instruction mode. Table 2-22
describes these pipeline activities.
Figure 2-11. Pipeline Activities (MIPS III)
IF1
I Fetch
and
Decode
Branch
Load/Store
ALU
Cycle
Phase
PCycle
PClock
IF2
Φ
2
Φ
1
Φ
2
Φ
1
Φ
2
Φ
1
Φ
2
Φ
1
Φ
2
Φ
1
RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
ITLB
IDC
ITC
ICA
IDEC
WB
WB
DCWDTDSA
DVA
EX
BAC
RF
DCA
DTLB