Electronics America Network Cables User Manual

APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
579
TLBWR
Write Random TLB Entry
TLBWR
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COP0
0 1 0 0 0 0
TLBWR
0 0 0 1 1 0
31 26 25 6 5 0
6196
CO
1
1
24
Format:
TLBWR
Description:
The TLB entry pointed at by the contents of the TLB Random register is loaded with the contents of the EntryHi
and EntryLo registers.
The
G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers.
Operation:
32, 64 T: TLB [Random
5...0
] ←
PageMask || (EntryHi and not PageMask) || EntryLo1 || EntryLo0
Exceptions:
Coprocessor unusable exception