Electronics America Network Cables User Manual

APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
577
TLBR
Read Indexed TLB Entry
TLBR
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COP0
0 1 0 0 0 0
TLBR
0 0 0 0 0 1
31 26 25 6 5 0
6196
CO
1
1
24
Format:
TLBR
Description:
The EntryHi and EntryLo registers are loaded with the contents of the TLB entry pointed at by the contents of the
TLB Index register.
The
G bit (which controls ASID matching) read from the TLB is written into both of the EntryLo0 and EntryLo1
registers. The operation is invalid (and the results are unspecified) if the contents of the TLB Index register are
greater than the number of TLB entries in the processor.
Operation:
32 T:
PageMask ← TLB [Index
5...0
]
127...96
EntryHi ← TLB [Index
5...0
]
95...64
and not TLB [Index
5...0
]
127...96
EntryLo1 ←
TLB [Index
5...0
]
63...33
|| TLB [Index
5...0
]
76
EntryLo0 ← TLB [Index
5...0
]
31...1
|| TLB [Index
5...0
]
76
64 T:
PageMask ← TLB [Index
5...0
]
255...192
EntryHi ← TLB [Index
5...0
]
191...128
and not TLB [Index
5...0
]
255...192
EntryLo1 ← TLB [Index
5...0
]
127...65
|| TLB [Index
5...0
]
140
EntryLo0 ← TLB [Index
5...0
]
63...1
|| TLB [Index
5...0
]
140
Exceptions:
Coprocessor unusable exception