Electronics America Network Cables User Manual

APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
563
SWL
Store Word Left (2/3)
SWL
Operation:
32 T:
vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ←
pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
if BigEndianMem = 0 then
pAddr ← pAddr
PSIZE - 1...2
|| 0
2
endif
byte ← vAddr
1...0
xor BigEndianCPU
2
if (vAddr
2
xor BigEndianCPU) = 0 then
data ← 0
32
|| 0
24 – 8 * byte
|| GPR [rt]
31...24 – 8 * byte
else
data ← 0
24 – 8 * byte
|| GPR
[
rt
]
31...24 – 8 * byte
|| 0
32
endif
StoreMemory (uncached, byte, data, pAddr, vAddr, DATA)
64 T:
vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DAT
A)
pAddr ← pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
if BigEndianMem = 0 then
pAddr ← pAddr
PSIZE - 1...2
|| 0
2
endif
byte ← vAddr
1...0
xor BigEndianCPU
2
if (vAddr2 xor BigEndianCPU) = 0 then
data ← 0
32
|| 0
24 – 8 * byte
|| GPR [rt]
31...24 – 8 * byte
else
data ← 0
24 – 8 * byte
|| GPR [rt]
31...24 – 8 * byte
|| 0
32
endif
StoreMemory (uncached, byte, data, pAddr, vAddr, DATA)