Electronics America Network Cables User Manual

APPENDIX A MIPS III INSTRUCTION SET DETAILS
506
Preliminary User’s Manual S15543EJ1V0UM
LDL
Load Doubleword Left (2/3)
LDL
The contents of general register rt are internally bypassed within the processor so that no NOP is needed between
an immediately preceding load instruction which specifies register
rt and a following LDL (or LDR) instruction which
also specifies register rt .
No address error exceptions due to alignment are possible.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
64 T:
vAddr ← ((offset
15
)
48
|| offset
15..0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← p
Addr
PSIZE - 1..3
|| (pAddr
2..0
xor ReverseEndian
3
)
if BigEndianMem = 0 then
pAddr ← pAddr
PSIZE - 1..3
|| 0
3
endif
byte ← vAddr
2..0
xor BigEndianCPU
3
mem ← LoadMemory (uncached, byte, pAddr, vAddr, DATA)
GPR [rt] ← mem7 + 8 * byte..0
|| GPR [rt]
55 – 8 * byte..0