Electronics America Network Cables User Manual

APPENDIX A MIPS III INSTRUCTION SET DETAILS

Preliminary User’s Manual S15543EJ1V0UM

487

DSRA

Doubleword Shift Right Arithmetic

DSRA

0 0 0 0 0

SPECIAL

0 0 0 0 0 0

rt rd sa

DSRA

1 1 1 0 1 1

31 26 25 21 20 16 15 11 10 6 5 0

6 5555 6

Format:

DSRA rd, rt, sa

Description:

The contents of general register

are shifted right by

bits, sign-extending the high-order bits. The result is

placed in register

This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or

supervisor mode causes a reserved instruction exception.

Operation:

64 T:

s ← 0 || sa

GPR [rd] ← (GPR [rt]

)

|| GPR [rt]

63..s

Exceptions:

Reserved instruction exception (32-bit user mode/supervisor mode)