Electronics America Network Cables User Manual

APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
443
BC0FL
Branch On Co
p
rocessor 0 False Likel
y
(
1/2
)
BC0FL
BC
0 1 0 0 0
COPz
0 1 0 0 X X
N
ote
BCFL
0 0 0 1 0
offset
31 26 25 21 20 16 15 0
655 16
Format:
BC0FL offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset , shifted left two bits and sign-extended. If the contents of CP0's condition (CpCond) line, as sampled during
the previous instruction, is false, the target address is branched to with a delay of one instruction.
If the conditional branch is not taken, the instruction in the branch delay slot is nullified.
Because the condition line is sampled during the previous instruction, there must be at least one instruction
between this instruction and a coprocessor instruction that changes the condition line.
Operation:
32 T-1:
condition ← not SR
18
T:
target ← (offset
15
)
14
|| offset || 0
2
T+1: if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
64 T-1:
condition ← not SR
T:
target ← (offset15
)
46
|| offset || 0
2
T+1: if condition then
PC ← PC + target
else
NullifyCurrentlnstruction
endif
Exceptions:
Coprocessor unusable exception
Note See the opcode table below, or A.6 CPU Instruction Opcode Bit Encoding.