Preliminary User’s Manual µPD98502 Network Controller Document No.
[MEMO] 2 Preliminary User’s Manual S15543EJ1V0UM
SUMMARY OF CONTENTS CHAPTER 1 INTRODUCTION .................................................................................................................. 23 CHAPTER 2 VR4120A ............................................................................................................................... 57 CHAPTER 3 SYSTEM CONTROLLER ................................................................................................... 185 CHAPTER 4 ATM CELL PROCESSOR.........................................
NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity.
VR4100, VR4102, VR4111, VR4120A, VR4300, VR4305, VR4310, VR4400, VR5000, VR10000, VR Series, VR4000 Series, VR4100 Series, and EEPROM are trademarks of NEC Corporation. Micro Wire is a trademark of National Semiconductor Corp. iAPX is a trademark of Intel Corp. DEC VAX is a trademark of Digital Equipment Corp. UNIX is a registered trademark in the United States and other countries, licensed exclusively through X/Open Company, Ltd. Ethernet is a trademark of Xerox Corp.
PREFACE Readers This manual is intended for engineers who need to be familiar with the capability of the µPD98502 in order to develop application systems based on it. Purpose The purpose of this manual is to help users understand the hardware capabilities (listed below) of the µPD98502.
CONTENTS CHAPTER 1 INTRODUCTION ............................................................................................................... 23 1.1 Features ...................................................................................................................................... 23 1.2 Ordering Information ................................................................................................................. 23 1.3 System Configuration...............................................
2.1.6 Floating-point unit (FPU)................................................................................................................64 2.1.7 CPU core memory management system (MMU) ...........................................................................65 2.1.8 Translation lookaside buffer (TLB) .................................................................................................65 2.1.9 Operating modes ........................................................................
CHAPTER 3 SYSTEM CONTROLLER............................................................................................... 185 3.1 Overview ................................................................................................................................... 185 3.1.1 CPU interface ..............................................................................................................................185 3.1.2 Memory interface ............................................................
3.4.15 SDRAM refresh............................................................................................................................219 3.4.16 Memory-to-CPU prefetch FIFO ....................................................................................................219 3.4.17 CPU-to-memory write FIFO .........................................................................................................219 3.4.18 SDRAM memory initialization .................................................
4.4.18 A_T1R (T1 Time Register)...........................................................................................................245 4.4.19 A_TSR (Time Stamp Register) ....................................................................................................245 4.4.20 A_IBBAR (IBUS Base Address Register) ....................................................................................245 4.4.21 A_INBAR (Instruction Base Address Register).................................................
5.2.20 En_HT1 (Hash Table Register 1).................................................................................................290 5.2.21 En_HT2 (Hash Table Register 2).................................................................................................290 5.2.22 En_CAR1 (Carry Register 1) .......................................................................................................291 5.2.23 En_CAR2 (Carry Register 2) .............................................................
6.2.20 U_RP1IR (USB Rx Pool1 Information Register) ..........................................................................327 6.2.21 U_RP1AR (USB Rx Pool1 Address Register) .............................................................................327 6.2.22 U_RP2IR (USB Rx Pool2 Information Register) ..........................................................................328 6.2.23 U_RP2AR (USB Rx Pool2 Address Register) .............................................................................
CHAPTER 7 PCI CONTROLLER .........................................................................................................370 7.1 Overview ...................................................................................................................................370 7.2 Bus Bridge Functions..............................................................................................................371 7.2.1 7.3 7.4 7.5 Internal bus to PCI transaction.......................................
8.3.4 UARTIER (UART Interrupt Enable Register) ...............................................................................416 8.3.5 UARTDLL (UART Divisor Latch LSB Register) ...........................................................................416 8.3.6 UARTDLM (UART Divisor Latch MSB Register) .........................................................................417 8.3.7 UARTIIR (UART Interrupt ID Register) ................................................................................
LIST OF FIGURES (1/5) Figure No. 1-1 Title Page Examples of the µPD98502 System Configuration ........................................................................................24 1-2 Block Diagram of the µPD98502....................................................................................................................25 1-3 Block Diagram of VR4120A RISC Processor..................................................................................................
LIST OF FIGURES (2/5) Figure No. Title Page 2-29 Supervisor Mode Address Space ................................................................................................................108 2-30 Kernel Mode Address Space .......................................................................................................................111 2-31 µPD98502 Physical Address Space ............................................................................................................
LIST OF FIGURES (3/5) Figure No. Title Page 2-71 Instruction Cache State Diagram .................................................................................................................173 2-72 Data Check Flow on Instruction Fetch .........................................................................................................174 2-73 Data Check Flow on Load Operations .........................................................................................................
LIST OF FIGURES (4/5) Figure No. Title Page 4-19 Open_Channel Command and Indication....................................................................................................258 4-20 Close_Channel Command and Indication ...................................................................................................259 4-21 Tx_Ready Command and Indication............................................................................................................
LIST OF FIGURES (5/5) Figure No. Title Page 6-16 Data Receiving in EndPoint0, EndPoint6 .....................................................................................................349 6-17 EndPoint2, EndPoint4 Receive Normal Mode..............................................................................................349 6-18 EndPoint2, EndPoint4 Receive Assemble Mode .........................................................................................
LIST OF TABLES (1/2) Table No. 2-1 Title Page System Control Coprocessor (CP0) Register Definitions...............................................................................64 2-2 Number of Delay Slot Cycles Necessary for Load and Store Instructions .....................................................67 2-3 Byte Specification Related to Load and Store Instructions ............................................................................68 2-4 Load/Store Instruction........................
LIST OF TABLES (2/2) Table No. 3-1 Title Page Endian Configuration Table..........................................................................................................................202 3-2 Endian Translation Table in Endian Converter.............................................................................................202 3-3 External Pin Mapping...................................................................................................................................
CHAPTER 1 INTRODUCTION The µPD98502 is a high performance controller, which can perform the protocol conversion between IP Packets and ATM Cells, which is especially suitable for ADSL router. It includes high performance MIPS based 64-bit RISC processor VR4120A CPU core, ATM Cell Processor, Ethernet Controller, USB Controller Block, PCI Controller Block, UTOPIA2 interface and SDRAM interface. 1.
CHAPTER 1 INTRODUCTION 1.3 System Configuration The µPD98502 can perform bridging and routing function between ADSL/ATM interface and USB/Ethernet interface and provides this function in a single chip. By selecting user interface, examples of system configuration will be realized as shown below. USB and Ethernet functions will exclusively operate each other. Figure 1-1.
CHAPTER 1 INTRODUCTION 1.4 Block Diagram (Summary) Figure 1-2. Block Diagram of the µPD98502 IBUS USB Full-Speed USB Controller VR4120A RISC Processor Core PROM/Flash 3.3V MII SDRAM Ethernet Controller #1, #2 System Controller RS-232C/ Micro Wire 16.
CHAPTER 1 INTRODUCTION 1.5 Block Diagram (Detail) 1.5.1 VR4120A RISC processor core We will support real-time OS running on high performance RISC processor VR4120A core and can perform network protocols (TCP/IP, PPP, SNMP, HTTP etc) to realize ADSL router and modem. Middleware including RTOS will be loaded to SDRAM from external PROM and Flash ROM and by setting write protected area for such an area, high speed processing will be realized together with large size instruction cache.
CHAPTER 1 INTRODUCTION 1.5.2 IBUS The IBUS is a 32-bit, 66-MHz high-speed on-chip bus, which enables interconnection each controller blocks. The IBUS supports the following bus protocols; • Single read/write transfer • Burst read/write transfer • Slave lock • Retry and disconnect • Bus parking Figure 1-4.
CHAPTER 1 INTRODUCTION 1.5.3 System controller System Controller is µPD98502’s internal system controller. System Controller provides bridging function among the VR4120A System Bus “SysAD”, NEC original high-speed on-chip bus “IBUS” and memory bus for SDRAM/PROM/Flash.
CHAPTER 1 INTRODUCTION 1.5.4 ATM cell processor By using NEC proprietary 32-bit controller, we will realize ATM Cell processor Unit. ATM Cell processing by firmware realizes more flexibility than before.
CHAPTER 1 INTRODUCTION 1.5.5 Ethernet controller Ethernet Controller supports 2-channel 10 Mbps/100 Mbps Ethernet MAC (Media Access Control) function and MII (Media Independent Interface) function. Features of Ethernet Controller are as follows; • Supports 10 M/100 M Ethernet MAC function compliant to IEEE802.3 and IEEE802.3u • Supports 3.3 V MII compliant to IEEE802.3u • Supports full duplex operation for both 100 Mbps and 10 Mbps • Supports flow control function compliant to IEEE802.3x/D3.
CHAPTER 1 INTRODUCTION 1.5.6 USB controller USB Controller provides Full Speed Function device function defined in Universal Serial Bus. Features of USB Controller are as follows; • Compliant to Universal Serial Bus Specification Rev. 1.1 • Supports Device class function by software running on VR4120A • Performs 12 Mbps Full Speed USB function device (Hub function will be not supported) • Can handle Suspend, Resume and Wake-up management signaling • Supports Remote Wake-up.
CHAPTER 1 INTRODUCTION 1.5.7 PCI controller PCI Controller provides PCI Bus function defined by PCI SIG. This block is bridging between IBUS and PCI. Features of PCI Controller are as follows; • 32-bit PCI Interface (up to 33 MHz) • 32-bit IBUS Interface (up to 33 MHz) • Supports PCI Dual Address Cycle as master • 33-MHz-PCI-frequency capable • Compliant to PCI Local Bus Specification Rev. 2.2 • Compliant to PCI Bus Power Management Interface Rev. 1.
CHAPTER 1 INTRODUCTION 1.
CHAPTER 1 INTRODUCTION Pin Name (1/3) Pin No. A1 Pin Name SMA13 Pin No. B10 Pin Name Pin No. URSDO C19 Pin Name NJTRST Pin No. D28 Pin Name PGTO2_B Pin No.
CHAPTER 1 INTRODUCTION (2/3) Pin No. K26 Pin Name GND Pin No. P5 Pin Name GND Pin No. V4 Pin Name IVDD Pin No. AB3 Pin Name IC-PUp Pin No.
CHAPTER 1 INTRODUCTION (3/3) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
CHAPTER 1 INTRODUCTION 1.7 Pin Function Symbol of I/O column indicates following status in this section. I : Input O : Output I/O : Bidirection I/OZ : Bidirection (Include Hi-Z state) I/OD : Bidirection (Open drain output) OZ : Output (Include Hi-Z state) OD : Output (Open drain) 1.7.1 Power supply Pin Name Pin No.
CHAPTER 1 INTRODUCTION 1.7.4 System control interface Pin Name Pin No.
CHAPTER 1 INTRODUCTION 1.7.5 Memory interface (1/2) Pin Name Pin No.
CHAPTER 1 INTRODUCTION (2/2) Pin Name Pin No.
CHAPTER 1 INTRODUCTION 1.7.6 PCI interface (1/2) Pin Name PSCLK Pin No.
CHAPTER 1 INTRODUCTION (2/2) Pin Name Pin No.
CHAPTER 1 INTRODUCTION 1.7.7 ATM interface 1.7.7.1 UTOPIA management interface Pin Name Pin No.
CHAPTER 1 INTRODUCTION 1.7.7.2 UTOPIA data interface Pin Name Pin No. I/O Active Level Function CLKUSL0 T4 I UTOPIA clock select CLKUSL1 T3 I (CLKUSL1/0 = L/L: 33 MHz, H/L: 25 MHz, L/H: 16.
CHAPTER 1 INTRODUCTION 1.7.8 Ethernet interface 1.7.8.1 Ethernet interface (Channel 1) Pin Name Pin No. I/O Active Level Function MIMCLK AF3 O MII management clock MIMD AG1 I/O MII management MICOL AH3 I Collision MICRS AF2 I Carrier sense MIRCLK AD3 I Receive clock (2.
CHAPTER 1 INTRODUCTION 1.7.8.2 Ethernet interface (Channel 2) Pin Name Pin No. I/O Active Level Function MI2MCLK AJ2 O MII management clock MI2MD AH5 I/O MII management MI2COL AG5 I Collision MI2CRS AG7 I Carrier sense MI2RCLK AK3 I Receive clock (2.5/25 MHz) MI2RDV AK4 I Receive data valid MI2RER AJ5 I Receive error MI2RD0 AH4 I Receive data MI2RD1 AJ3 I Receive data MI2RD2 AK2 I Receive data MI2RD3 AK1 I Receive data MI2TCLK AK5 I Transmit clock (2.
CHAPTER 1 INTRODUCTION 1.7.10 UART interface Pin Name Pin No. I/O URCLK D9 I URCTS_B B8 I Active Level Function UART external clock L UART clear to send URDCD_B A9 I L UART data carrier detect URDSR_B A8 I L UART data set ready URDTR_B A10 O L UART data terminal ready URRTS_B C10 O L UART data request to send URSDI B9 I UART serial data input URSDO B10 O UART serial data output 1.7.11 Micro Wire interface Pin Name Pin No.
CHAPTER 1 INTRODUCTION 1.7.14 I.C. – open Pin Name IC-OPEN Pin No. A17, A19, A20, A28, B16, B17, B18, B19, B26, C20, C24, D18, D20, E18, Y1, AA1, AB1, AB27, AB28, AC28, AC29, AD29, AH12, AJ12 I/O Active Level Function Active Level Function Active Level Function Active Level Function O 1.7.15 I.C.– pull down Pin Name IC-PDn Pin No. A21, B21, E20, AB4 I/O I 1.7.16 I.C. – pull down with resistor Pin Name IC-PDnR Pin No. A18, D15, AE30, AD28, AE27, AE28, AE29, AF28, AF29, AF30 I/O I/O 1.7.
CHAPTER 1 INTRODUCTION 1.
CHAPTER 1 INTRODUCTION Core PCI PCI PCI PCI PCI PCI PCI 048H-04CH 050H 054H 058H 05CH 060H-0FFH 100H-1FFH Register Length (Byte) 4 4 4 4 4 4 4 Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether 00H 04H 08H 0CH
CHAPTER 1 INTRODUCTION Core Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether Ether SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT Offset 1D0H 1D4H 1D8H 1DCH 1E0H 1E4H 1E8H 1
CHAPTER 1 INTRODUCTION Core SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT SYSCNT USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB Offset D8H DCH E0H E4H-FFH 100H 104H 108H 10CH 110H 114H 118H 11CH 120H 124H 128H-FFFH 00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H 84H 88H
CHAPTER 1 INTRODUCTION 1.9 Memory Map Using a 32-bit address, the processor physical address space encompasses 4 Gbytes. VR4120A uses this 4-Gbyte physical address space as shown in the following figure. Figure 1-10. Memory Map FFFF_FFFFH M irror of 0000_0000H - 1FFF_FFFF 2000_0000H 1FFF_FFFFH A ctual size of P R O M /Flash is m ax. 8 M B .
CHAPTER 1 INTRODUCTION 1.10 Reset Configuration The falling edge of Clock Control Unit (CCU)’s reset line (RST_B) serves as the µPD98502's internal reset. The System Controller generates the IBUS reset signal using RST_B for the global reset of the µPD98502. After 4 IBUS clock (SDCLK), the System Controller deasserts the IBUS reset signal synchronously with IBUS clock (66 MHz).
CHAPTER 1 INTRODUCTION 1.11 Interrupts The controller supports maskable interrupts and Non-Maskable to the CPU. Figure 1-12.
CHAPTER 1 INTRODUCTION 1.12 Clock Control Unit This section describe µPD98502’s internal clock is supplied by Clock Control Unit (CCU) with following figure. Figure 1-13. Block Diagram of Clock Control Unit C C U (C L O C K C O N T R O L U N IT ) 1/2 1/4 1/8 CLOCK E N AB L E R 33/25/16.
CHAPTER 2 VR4120A Caution The µPD98502 doesn’t support MIPS16 instructions. This chapter describes an VR4120A RISC Processor Core operation (MIPS instruction, Pipeline, etc.). Following in this Document, it is call for VR4120A RISC Processor Core with “VR4120A” or “VR4120A Core” simply. 2.1 Overview for VR4120A Figure 2-1 shows the internal block diagram of the VR4120A core.
CHAPTER 2 VR4120A 2.1.1 Internal block configuration 2.1.1.1 CPU CPU has hardware resources to process an integer instruction. They are the 64-bit register file, 64-bit integer data bus, and multiply-and-accumulate operation unit. 2.1.1.2 Coprocessor 0 (CP0) CP0 incorporates a memory management unit (MMU) and exception handling function. MMU checks whether there is an access between different memory segments (user, supervisor, and kernel) by executing address conversion.
CHAPTER 2 VR4120A 2.1.2 VR4120A registers The VR4120A has the following registers.
CHAPTER 2 VR4120A 2.1.3 VR4120A instruction set overview For CPU instructions, there are only one type of instructions – 32-bit length instruction (MIPS III). 2.1.3.1 MIPS III instruction All the CPU instructions are 32-bit length when executing MIPS III instructions, and they are classified into three instruction formats as shown in Figure 2-3: immediate (I-type), jump (J-type), and register (R-type). The field of each instruction format is described in Section 2.2 MIPS III Instruction Set Summary.
CHAPTER 2 VR4120A 2.1.4 Data formats and addressing The VR4120A uses following four data formats: ✧ ✧ ✧ ✧ Doubleword (64 bits) Word (32 bits) Halfword (16 bits) Byte (8 bits) For the µPD98502, byte ordering within all of the larger data formats - halfword, word, doubleword - can be configured in either big-endian or little-endian order. Endianness refers to the location of byte 0 within the multi-byte data structure.
CHAPTER 2 VR4120A The following special instructions to load and store data that are not aligned on 4-byte (word) or 8-byte (doubleword) boundaries: LWL LWR SWL SWR LDL LDR SDL SDR These instructions are used in pairs to provide an access to misaligned data. Accessing misaligned data incurs one additional instruction cycle over that required for accessing aligned data. Figure 2-6 shows the access of a misaligned word that has byte address 3 for the little-endian conventions. Figure 2-6.
CHAPTER 2 VR4120A 2.1.5 Coprocessors (CP0) MIPS ISA defines 4 types of coprocessors (CP0 to CP3). • • • • CP0 translates virtual addresses to physical addresses, switches the operating mode (kernel, supervisor, or user mode), and manages exceptions. It also controls the cache subsystem to analyze a cause and to return from the error state. CP1 is reserved for floating-point instructions. CP2 is reserved for future definition by MIPS. CP3 is no longer defined.
CHAPTER 2 VR4120A Table 2-1.
CHAPTER 2 VR4120A 2.1.7 CPU core memory management system (MMU) The VR4120A has a 32-bit physical addressing range of 4 Gbytes. However, since it is rare for systems to implement a physical memory space as large as that memory space, the CPU provides a logical expansion of memory space by translating addresses composed in the large virtual address space into available physical memory addresses.
CHAPTER 2 VR4120A 2.1.11 Instruction pipeline The VR4120A has a 6-stage instruction pipeline. Under normal circumstances, one instruction is issued each cycle. A detailed description of pipeline is provided in Section 2.3 Pipeline. 2.2 MIPS III Instruction Set Summary This section is an overview of the MIPS III ISA central processing unit (CPU) instruction set; refer to APPENDIX A MIPS III INSTRUCTION SET DETAILS for detailed descriptions of individual CPU instructions. 2.2.
CHAPTER 2 VR4120A 2.2.2 Instruction classes The CPU instructions are classified into five classes. 2.2.2.1 Load and store instructions Load and store are immediate (I-type) instructions that move data between memory and general registers. The only addressing mode that load and store instructions directly support is base register plus 16-bit signed immediate offset.
CHAPTER 2 VR4120A Table 2-3.
CHAPTER 2 VR4120A Table 2-4. Load/Store Instruction Instruction Format and Description op base rt offset Load Byte LB rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The bytes of the memory location specified by the address are sign extended and loaded into register rt. Load Byte Unsigned LBU rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address.
CHAPTER 2 VR4120A Table 2-5. Load/Store Instruction (Extended ISA) Instruction Format and Description op base rt offset Store Word Left SWL rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. Shifts to the right the contents of register rt so that the left-most byte of the word is in the position of the address-specified byte. The result is stored to the lower word in memory.
CHAPTER 2 VR4120A 2.2.2.2 Computational instructions Computational instructions perform arithmetic, logical, and shift operations on values in registers. Computational instructions can be either in register (R-type) format, in which both operands are registers, or in immediate (I-type) format, in which one operand is a 16-bit immediate.
CHAPTER 2 VR4120A Table 2-7. ALU Immediate Instruction (Extended ISA) Instruction Format and Description op rs rt immediate Doubleword Add Immediate DADDI rt, rs, immediate The 16-bit immediate is sign extended to 64 bits and then added to the contents of register rs to form a 64-bit result. The result is stored into register rt. An exception occurs on the generation of integer overflow.
CHAPTER 2 VR4120A Table 2-9. Three-Operand Type Instruction (Extended ISA) Instruction Format and Description op rs rt rd sa funct Doubleword Add DADD rd, rt, rs The contents of register rs are added to that of register rt. The 64-bit result is stored into register rd. An exception occurs on the generation of integer overflow. Doubleword Add Unsigned DADDU rd, rt, rs The contents of register rs are added to that of register rt. The 64-bit result is stored into register rd.
CHAPTER 2 VR4120A Table 2-11. Shift Instruction (Extended ISA) Instruction Format and Description op rs rt rd sa funct Doubleword Shift Left Logical DSLL rd, rt, sa The contents of register rt are shifted left by sa bits and zeros are inserted into the emptied lower bits. The 64-bit result is stored into register rd. Doubleword Shift Right Logical DSRL rd, rt, sa The contents of register rt are shifted right by sa bits and zeros are inserted into the emptied higher bits.
CHAPTER 2 VR4120A Table 2-12. Multiply/Divide Instructions Instruction Format and Description op rs rt rd sa funct Multiply MULT rs, rt The contents of registers rt and rs are multiplied, treating both operands as 32-bit signed integers. The 64-bit result is stored into special registers HI and LO. In the 64-bit mode, the operand must be sign extended. Multiply Unsigned MULTU rs, rt The contents of registers rt and rs are multiplied, treating both operands as 32-bit unsigned integers.
CHAPTER 2 VR4120A Table 2-13. Multiply/Divide Instructions (Extended ISA) Instruction Format and Description op rs rt rd sa funct Doubleword Multiply DMULT rs, rt The contents of registers rt and rs are multiplied, treating both operands as signed integers. The 128-bit result is stored into special registers HI and LO. Doubleword Multiply Unsigned DMULTU rs, rt The contents of registers rt and rs are multiplied, treating both operands as unsigned integers.
CHAPTER 2 VR4120A Table 2-14. Number of Stall Cycles in Multiply and Divide Instructions Instruction Number of Instruction Cycles MULT 1 MULTU 1 DIV 36 DIVU 36 DMULT 3 DMULTU 3 DDIV 68 DDIVU 68 MACC 0 DMACC 0 2.2.2.3 Jump and branch instructions Jump and branch instructions change the control flow of a program.
CHAPTER 2 VR4120A Table 2-16. Jump Instruction Instruction Format and Description target op Jump JAL target The contents of 26-bit target address is shifted left by two bits and combined with the high-order four bits of the PC. The program jumps to this calculated address with a delay of one instruction. Jump And Link J target The contents of 26-bit target address is shifted left by two bits and combined with the high-order four bits of the PC.
CHAPTER 2 VR4120A There are special symbols used in the instruction formats of Tables 2-17 through 2-21. REGIMM Sub CO BC br op : Opcode : Sub-operation code : Sub-operation identifier : BC sub-operation code : Branch condition identifier : Operation code Table 2-17. Branch Instructions Instruction Format and Description op rs rt offset Branch On Equal BEQ rs, rt, offset If the contents of register rs are equal to that of register rt, the program branches to the target address.
CHAPTER 2 VR4120A Table 2-18. Branch Instructions (Extended ISA) Instruction Format and Description op rs rt offset Branch On Equal Likely BEQL rs, rt, offset If the contents of register rs are equal to that of register rt, the program branches to the target address. If the branch condition is not met, the instruction in the delay slot is discarded.
CHAPTER 2 VR4120A 2.2.2.4 Special instructions Special instructions generate software exceptions. Their formats are R-type (Syscall, Break). The Trap instruction is available only for the VR4000 Series. All the other instructions are available for all VR Series. Table 2-19. Special Instructions Instruction Format and Description SPECIAL rs rt rd sa Synchronize SYNC Completes the load/store instruction executing in the current pipeline before the next load/store instruction starts execution.
CHAPTER 2 VR4120A Table 2-20. Special Instructions (Extended ISA) (2/2) Instruction Format and Description REGIMM rs sub immediate Trap If Greater Than Or Equal Immediate TGEI rs, immediate The contents of register rs are compared with 16-bit sign-extended immediate data, treating both operands as signed integers. If the contents of register rs are greater than or equal to 16-bit signextended immediate data, an exception occurs.
CHAPTER 2 VR4120A Table 2-21. System Control Coprocessor (CP0) Instructions (2/2) Instruction Format and Description COP0 funct CO Read Indexed TLB Entry TLBR The TLB entry indexed by the index register is loaded into the entryHi, entryLo0, entryLo1, or page mask register. Write Indexed TLB Entry TLBWI The contents of the entryHi, entryLo0, entryLo1, or page mask register are loaded into the TLB entry indexed by the index register.
CHAPTER 2 VR4120A 2.3 Pipeline This section describes the basic operation of the VR4120A Core pipeline, which includes descriptions of the delay slots (instructions that follow a branch or load instruction in the pipeline), interrupts to the pipeline flow caused by interlocks and exceptions, and CP0 hazards. 2.3.1 Pipeline stages The pipeline is controlled by PClock(one cycle of PClock which runs at 4-times frequency of MasterClock) and one cycle of this PClock is called PCycle.
CHAPTER 2 VR4120A Figure 2-10. Instruction Execution in the Pipeline (Five stages) PCycle IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 Current CPU cycle 2.3.1.2 Pipeline activities (1) MIPS III instruction Figure 2-11 shows the activities that can occur during each pipeline stage in MIPS III Instruction mode.
CHAPTER 2 VR4120A Table 2-22.
CHAPTER 2 VR4120A 2.3.2 Branch delay During a VR4120A's pipeline operation, a one-cycle branch delay occurs when: • • Target address is calculated by a Jump instruction Branch condition of branch instruction is met and then logical operation starts for branch-destination comparison The instruction location following the Jump/Branch instruction is called a branch delay slot.
CHAPTER 2 VR4120A 2.3.4 Pipeline operation The operation of the pipeline is illustrated by the following examples that describe how typical instructions are executed. The instructions described are six: ADD, JALR, BEQ, TLT, LW, and SW. Each instruction is taken through the pipeline and the operations that occur in each relevant stage are described. 2.3.4.
CHAPTER 2 VR4120A 2.3.4.2 Jump and link register instruction (JALR rd, rs) IF stage Same as the IF stage for the ADD instruction. IT stage Same as the IT stage for the ADD instruction. RF stage A register specified in the rs field is read from the file during Φ2 at the RF stage, and the value read from the rs register is input to the virtual PC latch synchronously. This value is used to fetch an instruction at the jump destination.
CHAPTER 2 VR4120A 2.3.4.3 Branch on equal instruction (BEQ rs, rt, offset) IF stage Same as the IF stage for the ADD instruction. IT stage Same as the IT stage for the ADD instruction. RF stage During Φ2, the register file is addressed with the rs and rt fields. A check is performed to determine if each corresponding bit position of these two operands has equal values. If they are equal, the PC is set to PC + target, where target is the sign-extended offset field.
CHAPTER 2 VR4120A 2.3.4.4 Trap if less than instruction (TLT rs, rt) IF stage Same as the IF stage for the ADD instruction. RF stage Same as the RF stage for the ADD instruction. EX stage ALU controls are set to do an A - B operation. The operands flow into the ALU inputs, and the ALU operation is started. The result of the ALU operation is latched into the ALU output latch during Φ1. The sign bits of operands and of the ALU output latch are checked to determine if a less than condition is true.
CHAPTER 2 VR4120A 2.3.4.5 Load word instruction (LW rt, offset (base)) IF stage Same as the IF stage for the ADD instruction. IT stage Same as the IT stage for the ADD instruction. RF stage Same as the RF stage for the ADD instruction. Note that the base field is in the same position as the rs field. EX stage Refer to the EX stage for the ADD instruction. For LW, the inputs to the ALU come from GPR[base] through the bypass multiplexer and from the sign-extended offset field.
CHAPTER 2 VR4120A 2.3.4.6 Store word instruction (SW rt, offset (base)) IF stage Same as the IF stage for the ADD instruction. IT stage Same as the IT stage for the ADD instruction. RF stage Same as the RF stage for the LW instruction. EX stage Refer to the LW instruction for a calculation of the effective address. From the RF output latch, the GPR[rt] is sent through the bypass multiplexer and into the main shifter, where the shifter performs the byte-alignment operation for the operand.
CHAPTER 2 VR4120A 2.3.5 Interlock and exception handling Smooth pipeline flow is interrupted when cache misses or exceptions occur, or when data dependencies are detected. Interruptions handled using hardware, such as cache misses, are referred to as interlocks, while those that are handled using software are called exceptions. As shown in Figure 2-19, all interlock and exception conditions are collectively referred to as faults. Figure 2-19.
CHAPTER 2 VR4120A Table 2-24. Pipeline Interlock Interlock Description ITM Instruction TLB Miss ICM Instruction Cache Miss LDI Load Data Interlock MDI MD Busy Interlock SLI Store-Load Interlock CP0 Coprocessor 0 Interlock DTM Data TLB Miss DCM Data Cache Miss DCB Data Cache Busy Table 2-25.
CHAPTER 2 VR4120A 2.3.5.1 Exception conditions When an exception condition occurs, the relevant instruction and all those that follow it in the pipeline are cancelled. Accordingly, any stall conditions and any later exception conditions that may have referenced this instruction are inhibited; there is no benefit in servicing stalls for a cancelled instruction. When an exceptional conditions is detected for an instruction, the VR4120A will discard it and all following instructions.
CHAPTER 2 VR4120A 2.3.5.2 Stall conditions Stalls are used to stop the pipeline for conditions detected after the RF stage. When a stall occurs, the processor will resolve the condition and then the pipeline will continue. Figure 2-21 shows a data cache miss stall, and Figure 222 shows a CACHE instruction stall. Figure 2-21.
CHAPTER 2 VR4120A 2.3.5.3 Slip conditions During Φ2 of the RF stage and Φ1 of the EX stage, internal logic will determine whether it is possible to start the current instruction in this cycle. If all of the source operands are available (either from the register file or via the internal bypass logic) and all the hardware resources necessary to complete the instruction will be available whenever required, then the instruction “run”; otherwise, the instruction will “slip”.
CHAPTER 2 VR4120A Figure 2-24. MD Busy Interlock IF RF EX DC WB Bypass MFLO/MFHI IF RF RF 1 2 IF EX DC WB RF EX DC WB 1 Detect MD busy interlock 2 Get target data MD Busy Interlock is detected in the RF stage as shown in Figure 2-24 and also the pipeline slips in the stage. MD Busy Interlock occurs when HI/LO register is required by MFHI/MFLO instruction before finishing Mult/Div execution. The pipeline begins running again the clock after finishing Mult/Div execution.
CHAPTER 2 VR4120A 2.3.6 Program compatibility The VR4120A core is designed taking into consideration program compatibility with other VR-Series processors. However, because the VR4120A differs from other processors in its architecture, it may not be able to run some programs that run on other processors. Likewise, programs that run on the VR4120A will not necessarily run on other processors.
CHAPTER 2 VR4120A 2.4 Memory Management System The VR4120A Core provides a memory management unit (MMU) which uses a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. This chapter describes the virtual and physical address spaces, the virtual-to-physical address translation, the operation of the TLB in making these translations, and the CP0 registers that provide the software interface to the TLB. 2.4.
CHAPTER 2 VR4120A 2.4.2 Virtual address space This section describes the virtual/physical address space and the manner in which virtual addresses are converted or “translated” into physical addresses in the TLB. The VR4120A virtual address can be either 32 or 64 bits wide, depending on whether the processor is operating in 32-bit or 64-bit mode. 31 In 32-bit mode, addresses are 32 bits wide. The maximum user process size is 2 Gbytes (2 ). 40 In 64-bit mode, addresses are 64 bits wide.
CHAPTER 2 VR4120A 2.4.2.1 Virtual-to-physical address translation Converting a virtual address to a physical address begins by comparing the virtual address from the processor with the virtual addresses in the TLB; there is a match when the virtual page number (VPN) of the address is the same as the VPN field of the entry, and either: the Global (G) bit of the TLB entry is set to 1 the ASID field of the virtual address is the same as the ASID field of the TLB entry.
CHAPTER 2 VR4120A 2.4.2.2 32-bit mode address translation Figure 2-26 shows the virtual-to-physical-address translation of a 32-bit mode address. The pages can have five different sizes between 1 Kbyte (10 bits) and 256 Kbytes (18 bits), each being 4 times as large as the preceding one in ascending order, that is 1 K, 4 K, 16 K, 64 K, and 256 K. Shown at the top of Figure 2-26 is the virtual address space in which the page size is 1 Kbyte and the offset is 10 bits.
CHAPTER 2 VR4120A 2.4.2.3 64-bit mode address translation Figure 2-27 shows the virtual-to-physical-address translation of a 64-bit mode address. This figure illustrates the two possible page size; a 1-Kbyte page (10 bits) and a 256-Kbyte page (18 bits). Shown at the top of Figure 2-27 is the virtual address space in which the page size is 1 Kbyte and the offset is 10 bits. The 30 bits excluding the ASID field represents the virtual page number (VPN), enabling selecting a page table of 1 G entry.
CHAPTER 2 VR4120A 2.4.2.4 Operating modes The processor has three operating modes that function in both 32- and 64-bit operations: User mode Supervisor mode Kernel mode User and Kernel modes are common to all VR-Series processors. Generally, Kernel mode is used to execute the operating system, while User mode is used to run application programs. The VR4000 Series processors have a third mode, which is called Supervisor mode and categorized in between User and Kernel modes.
CHAPTER 2 VR4120A The User segment starts at address 0 and the current active user process resides in either useg (in 32-bit mode) or xuseg (in 64-bit mode). The TLB identically maps all references to useg/xuseg from all modes, and controls cache accessibility.
CHAPTER 2 VR4120A 2.4.2.6 Supervisor-mode virtual addressing Supervisor mode shown in Figure 2-29 is designed for layered operating systems in which a true kernel runs in Kernel mode, and the rest of the operating system runs in Supervisor mode.
CHAPTER 2 VR4120A Table 2-28.
CHAPTER 2 VR4120A 2.4.2.7 Kernel-mode virtual addressing If the Status register satisfies any of the following conditions, the processor runs in Kernel mode. KSU = 00 EXL = 1 ERL = 1 The addressing width in Kernel mode varies according to the state of the KX bit of the Status register, as follows: When KX = 0: 32-bit kernel space is selected. When KX = 1: 64-bit kernel space is selected.
CHAPTER 2 VR4120A Figure 2-30. Kernel Mode Address Space 32-bit mode Note 1 64-bit mode FFFF_ FFFFH FFFF_ FFFF_ FFFF_ FFFFH 0.5 Gbytes with TLB mapping kseg3 E000_ 0000H DFFF_ FFFFH 0.5 Gbytes with TLB mapping C000_ 0000H BFFF_FFFFH A000_ 0000H 9FFF_FFFFH 8000_ 0000H 7FFF_FFFFH ksseg 0.5 Gbytes without TLB mapping uncacheable kseg1 0.
CHAPTER 2 VR4120A Table 2-29.
CHAPTER 2 VR4120A (5) kseg3 (32-bit kernel mode, kernel space 3) When KX = 0 in the Status register and the most-significant three bits of the virtual address space are 111, the 29 kseg3 virtual address space is selected; it is the current 512-Mbyte (2 -byte) kernel virtual space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. Table 2-30.
CHAPTER 2 VR4120A (7) xksseg (64-bit kernel mode, current supervisor space) When KX = 1 in the Status register and bits 63 and 62 of the virtual address space are 01, the xksseg address 40 space is selected; it is the 1-Tbyte (2 bytes) current supervisor address space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address.
CHAPTER 2 VR4120A (9) xkseg (64-bit kernel mode, physical spaces) When the KX = 1 in the Status register and bits 63 and 62 of the virtual address space are 11, the virtual address space is called xkseg and selected as either of the following: • • Kernel virtual space xkseg, the current kernel virtual space; the virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address This space is referenced via TLB.
CHAPTER 2 VR4120A 2.4.3 Physical address space So VR4120A core uses a 32-bit address, that the processor physical address space encompasses 4 Gbytes. The VR4120A uses this 4-Gbyte physical address space as shown in Figure 2-31. Figure 2-31. µPD98502 Physical Address Space FFFF_FFFFH M irror of 0000_0000H - 1FFF_FFFF 2000_0000H 1FFF_FFFFH A ctual size of P R O M /Flash is m ax. 8 M B .
CHAPTER 2 VR4120A 2.4.4 System control coprocessor The System Control Coprocessor (CP0) is implemented as an integral part of the CPU, and supports memory management, address translation, exception processing, and other privileged operations. The CP0 contains the registers and a 32-entry TLB shown in Figure 2-32. The sections that follow describe how the processor uses each of the memory management-related registers.
CHAPTER 2 VR4120A 2.4.4.1 Format of a TLB entry Figure 2-33 shows the TLB entry formats for both 32- and 64-bit modes. Each field of an entry has a corresponding field in the EntryHi, EntryLo0, EntryLo1, or PageMask registers. Figure 2-33.
CHAPTER 2 VR4120A 2.4.5 CP0 registers The CP0 registers explained below are accessed by the memory management system and software. The parenthesized number that follows each register name is the register number. 2.4.5.1 Index register (0) The Index register is a 32-bit, read/write register containing five low-order bits to index an entry in the TLB. The most-significant bit of the register shows the success or failure of a TLB probe (TLBP) instruction.
CHAPTER 2 VR4120A 2.4.5.3 EntryLo0 (2) and EntryLo1 (3) registers The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible. They are used to access the on-chip TLB.
CHAPTER 2 VR4120A Table 2-32. Cache Algorithm C Bit Value Cache Algorithm 0 Cached 1 Cached 2 Uncached 3 Cached 4 Cached 5 Cached 6 Cached 7 Cached 2.4.5.4 PageMask register (5) The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison mask that sets the page size for each TLB entry, as shown in Table 2-33. Page sizes must be from 1 Kbyte to 256 Kbytes.
CHAPTER 2 VR4120A 2.4.5.5 Wired register (6) The Wired register is a read/write register that specifies the lower boundary of the random entry of the TLB as shown in Figure 2-38. Wired entries cannot be overwritten by a TLBWR instruction. They can, however, be overwritten by a TLBWI instruction. Random entries can be overwritten by both instructions. Figure 2-38.
CHAPTER 2 VR4120A 2.4.5.6 EntryHi register (10) The EntryHi register is write-accessible. It is used to access the on-chip TLB. The EntryHi register holds the highorder bits of a TLB entry for TLB read and write operations. If a TLB Mismatch, TLB Invalid, or TLB Modified exception occurs, the EntryHi register holds the high-order bit of the TLB entry. The EntryHi register is also set with the virtual page number (VPN2) for a virtual address where an exception occurred and the ASID. See Section 2.
CHAPTER 2 VR4120A 2.4.5.8 Config register (16) The Config register specifies various configuration options selected on VR4120A processors. Some configuration options, as defined by the EC and BE fields, are set by the hardware during Cold Reset and are included in the Config register as read-only status bits for the software to access. Other configuration options are read/write (AD, EP, and K0 fields) and controlled by software; on Cold Reset these fields are undefined.
CHAPTER 2 VR4120A 2.4.5.9 Load linked address (LLAddr) register (17) The read/write Load Linked Address (LLAddr) register is not used with the VR4120A processor except for diagnostic purpose, and serves no function during normal operation. LLAddr register is implemented just for compatibility between the VR4120A and VR4000/VR4400. Figure 2-43. LLAddr Register 31 0 PAddr 32 PAddr: 32-bit physical address 2.4.5.
CHAPTER 2 VR4120A 2.4.5.11 Virtual-to-physical address translation During virtual-to-physical address translation, the CPU compares the 8-bit ASID (when the Global bit, G, is not set to 1) of the virtual address to the ASID of the TLB entry to see if there is a match. One of the following comparisons are also made: Note 1 of the 32-bit virtual address are compared to the contents of the In 32-bit mode, the high-order bits VPN2 (virtual page number divided by two) of each TLB entry.
CHAPTER 2 VR4120A Figure 2-46.
CHAPTER 2 VR4120A 2.4.5.13 TLB instructions The instructions used for TLB control are described below. (1) Translation lookaside buffer probe (TLBP) The translation lookaside buffer probe (TLBP) instruction loads the Index register with a TLB number that matches the content of the EntryHi register. If there is no TLB number that matches the TLB entry, the highest-order bit of the Index register is set.
CHAPTER 2 VR4120A 2.5 Exception Processing This chapter describes VR4120A CPU exception processing, including an explanation of hardware that processes exceptions. 2.5.1 Exception processing operation The processor receives exceptions from a number of sources, including translation lookaside buffer (TLB) misses, arithmetic overflows, I/O interrupts, and system calls.
CHAPTER 2 VR4120A 2.5.2 Precision of exceptions VR4120A CPU exceptions are logically precise; the instruction that causes an exception and all those that follow it are aborted and can be re-executed after servicing the exception. When succeeding instructions are discarded, exceptions associated with those instructions are also discarded. Exceptions are not taken in the order detected, but in instruction fetch order. The exception handler can determine the cause of an exception and the address.
CHAPTER 2 VR4120A 2.5.3.1 Context register (4) The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array on the memory; this array is a table that stores virtual-to-physical address translations. When there is a TLB miss, the operating system loads the unsuccessfully translated entry from the PTE array to the TLB. The Context register is used by the TLB Refill exception handler for loading TLB entries.
CHAPTER 2 VR4120A 2.5.3.2 BadVAddr register (8) The Bad Virtual Address (BadVAddr) register is a read-only register that saves the most recent virtual address that failed to have a valid translation, or that had an addressing error. Figure 2-48 shows the format of the BadVAddr register. Caution This register saves no information after a bus error exception, because it is not an address error exception. Figure 2-48.
CHAPTER 2 VR4120A 2.5.3.4 Compare register (11) The Compare register causes a timer interrupt; it maintains a stable value that does not change on its own. When the value of the Count register (see Section 2.5.3.3 Count register (9)) equals the value of the Compare register, the IP7 bit in the Cause register is set. This causes an interrupt as soon as the interrupt is enabled. Writing a value to the Compare register, as a side effect, clears the timer interrupt request.
CHAPTER 2 VR4120A 2.5.3.5 Status register (12) The Status register is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the processor. Figure 2-51 shows the format of the Status register. Figure 2-51. Status Register Format 29 28 27 26 25 24 31 CU0 RE 16 15 8 0 CU0 0 RE DS IM 3 1 2 1 9 8 7 6 5 KX SX UX 1 1 1 4 3 KSU 2 2 1 ERL EXL 1 1 0 IE 1 : Enables/disables the use of the coprocessor (1 → Enabled, 0 → Disabled).
CHAPTER 2 VR4120A Figure 2-52. Status Register Diagnostic Status Field 24 23 22 21 20 19 18 17 16 0 BEV TS SR 0 CH CE DE 2 1 1 1 1 1 1 1 : Specifies the base address of a TLB Refill exception vector and common exception vector (0 → Normal, 1 → Bootstrap). TS : Occurs the TLB to be shut down (read-only) (0 → Not shut down, 1 → Shut down). This bit is used to avoid any problems that may occur when multiple TLB entries match the same virtual address.
CHAPTER 2 VR4120A (7) Status after reset The contents of the Status register are undefined after Cold resets, except for the following bits in the diagnostic status field. • • • TS and SR are cleared to 0. ERL and BEV are set to 1. SR is 0 after Cold reset, and is 1 after Soft reset or NMI interrupt. Remark Cold reset and Soft reset are CPU core reset (see Section 2.6 Initialization Interface). 2.5.3.
CHAPTER 2 VR4120A Table 2-35.
CHAPTER 2 VR4120A 2.5.3.7 Exception program counter (EPC) register (14) The Exception Program Counter (EPC) is a read/write register that contains the address at which processing resumes after an exception has been serviced. Because the µPD98502 does not support the MIPS16 instruction mode, the EPC register contains either: • • Virtual address of the instruction that caused the exception.
CHAPTER 2 VR4120A 2.5.3.8 WatchLo (18) and WatchHi (19) registers The VR4120A processor provides a debugging feature to detect references to a selected physical address; load and store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception. Figures 2-55 and 2-56 show the format of the WatchLo and WatchHi registers. Figure 2-55.
CHAPTER 2 VR4120A 2.5.3.9 XContext register (20) The read/write XContext register contains a pointer to an entry in the page table entry (PTE) array, an operating system data structure that stores virtual-to-physical address translations. If a TLB miss occurs, the operating system loads the untranslated data from the PTE into the TLB to handle the software error. The XContext register is used by the XTLB Refill exception handler to load TLB entries in 64-bit addressing mode.
CHAPTER 2 VR4120A 2.5.3.11 Cache error register (27) The Cache Error register is a readable/writeable register. This register is defined to maintain software-compatibility with the VR4100, and is not used in hardware because the VR4120A CPU has no parity. Figure 2-59 shows the format of the Cache Error register. Figure 2-59. Cache Error Register Format 31 0 0 32 0 : RFU. Write 0 in a write operation. When this field is read, 0 is read. 2.5.3.
CHAPTER 2 VR4120A 2.5.4 Details of exceptions This section describes causes, processes, and services of the VR4120A's exceptions. 2.5.4.1 Exception types This section gives sample exception handler operations for the following exception types: Cold Reset Soft Reset NMI Remaining processor exceptions When the EXL and ERL bits in the Status register are 0, either User, Supervisor, or Kernel operating mode is specified by the KSU bits in the Status register.
CHAPTER 2 VR4120A Table 2-37. 32-Bit Mode Exception Vector Base Addresses Vector Base Address (Virtual) Vector Offset Cold Reset Soft Reset NMI BFC0_0000H (BEV bit is automatically set to 1) 0000H TLB Refill (EXL = 0) 8000_0000H (BEV = 0) BFC0_0200H (BEV = 1) 0000H XTLB Refill (EXL = 0) Other exceptions 0080H 0180H (1) TLB refill exception vector When BEV bit = 0, the vector base address (virtual) for the TLB Refill exception is in kseg0 (unmapped) space.
CHAPTER 2 VR4120A 2.5.4.3 Priority of exceptions While more than one exception can occur for a single instruction, only the exception with the highest priority is reported. Table 2-38 lists the priorities. Table 2-38.
CHAPTER 2 VR4120A 2.5.4.4 Cold reset exception (1) Cause The Cold Reset exception occurs when the ColdReset_B signal (internal) is asserted and then deasserted. This exception is not maskable. The Reset_B signal (internal) must be asserted along with the ColdReset_B signal (for details, see Section 2.6 Initialization Interface).
CHAPTER 2 VR4120A 2.5.4.5 Soft reset exception (1) Cause A Soft Reset (sometimes called Warm Reset) occurs when the ColdReset_B signal (internal) remains deasserted while the Reset_B signal (internal) goes from assertion to deassertion (for details, see Section 2.6 Initialization Interface). A Soft Reset immediately resets all state machines, and sets the SR bit of the Status register. Execution begins at the reset vector when the reset is deasserted. This exception is not maskable.
CHAPTER 2 VR4120A 2.5.4.6 NMI exception (1) Cause The Nonmaskable Interrupt (NMI) exception occurs when the NMI signal (internal) becomes active. This interrupt is not maskable; it occurs regardless of the settings of the EXL, ERL, and IE bits in the Status register (for details, see Section 2.8 CPU Core Interrupts).
CHAPTER 2 VR4120A 2.5.4.7 Address error exception (1) Cause The Address Error exception occurs when an attempt is made to execute one of the following. This exception is not maskable.
CHAPTER 2 VR4120A 2.5.4.8 TLB exceptions Three types of TLB exceptions can occur: • • • TLB Refill exception occurs when there is no TLB entry that matches a referenced address. A TLB Invalid exception occurs when a TLB entry that matches a referenced virtual address is marked as being invalid (with the V bit set to 0). The TLB Modified exception occurs when a TLB entry that matches a virtual address referenced by the store instruction is marked as being valid (with the V bit set to 1).
CHAPTER 2 VR4120A (2) TLB invalid exception (a) Cause The TLB Invalid exception occurs when the TLB entry that matches with the virtual address to be referenced is invalid (the V bit is set to 0). This exception is not maskable. (b) Processing The common exception vector is used for this exception. The TLBL or TLBS code in the ExcCode field of the Cause register is set. If this exception has been caused by an instruction reference or load operation, TLBL is set.
CHAPTER 2 VR4120A (3) TLB modified exception (a) Cause The TLB Modified exception occurs when the TLB entry that matches with the virtual address referenced by the store instruction is valid (V bit is 1) but is not writeable (D bit is 0). This exception is not maskable. (b) Processing The common exception vector is used for this exception, and the Mod code in the ExcCode field of the Cause register is set.
CHAPTER 2 VR4120A 2.5.4.9 Bus error exception (1) Cause A Bus Error exception is raised by board-level circuitry for events such as bus time-out, local bus parity errors, and invalid physical memory addresses or access types. This exception is not maskable. A Bus Error exception occurs only when a cache miss refill, uncached reference, or unbuffered write occurs simultaneously. In other words, it occurs when an illegal access is detected during BCU read. For details of illegal accesses.
CHAPTER 2 VR4120A 2.5.4.10 System call exception (1) Cause A System Call exception occurs during an attempt to execute the SYSCALL instruction. This exception is not maskable. (2) Processing The common exception vector is used for this exception, and the Sys code in the ExcCode field of the Cause register is set. The EPC register contains the address of the SYSCALL instruction unless it is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction.
CHAPTER 2 VR4120A 2.5.4.12 Coprocessor unusable exception (1) Cause The Coprocessor Unusable exception occurs when an attempt is made to execute a coprocessor instruction for either: a corresponding coprocessor unit that has not been marked usable (Status register bit, CU0 = 0), or CP0 instructions, when the unit has not been marked usable (Status register bit, CU0 = 0) and the process executes in User or Supervisor mode. This exception is not maskable.
CHAPTER 2 VR4120A 2.5.4.
CHAPTER 2 VR4120A 2.5.4.14 Trap exception (1) Cause The Trap exception occurs when a TGE, TGEU, TLT, TLTU, TEQ, TNE, TGEI, TGEUI, TLTI, TLTUI, TEQI, or TNEI instruction results in a TRUE condition. This exception is not maskable. (2) Processing The common exception vector is used for this exception, and the Tr code in the ExcCode field of the Cause register is set.
CHAPTER 2 VR4120A 2.5.4.16 Watch exception (1) Cause A Watch exception occurs when a load or store instruction references the physical address specified by the WatchLo/WatchHi registers. The WatchLo/WatchHi registers specify whether a load or store or both could have initiated this exception.
CHAPTER 2 VR4120A 2.5.4.17 Interrupt exception (1) Cause The Interrupt exception occurs when one of the eight interrupt conditions Note is asserted. In the VR4120A CPU, interrupt requests from internal peripheral units first enter the ICU and are then notified to the CPU core via one of four interrupt sources (Int(3:0)) or NMI.
CHAPTER 2 VR4120A Figure 2-61. Common Exception Handling (1/2) (a) Handling Exceptions other than Cold Reset, Soft Reset, NMI, and TLB/XTLB Refill (Hardware) Start Entry Hi←VPN2, ASID X/Context←VPN2 Set Cause register (ExcCode, CE) ) • EntryHi and X/Context registers are set only when a TLB Refill, TLB Invalid, or TLB Modified exception occurs.
CHAPTER 2 VR4120A Figure 2-61. Common Exception Handling (2/2) (b) Servicing Common Exceptions (Software) • The occurrence of TLB Refill, TLB Invalid, and TLB Modified exceptions is disabled by using an unmapped space. • The occurrence of the Watch and Interrupt exceptions is disabled by setting EXL = 1. • Other exceptions are avoided in the OS programs. • However, the Cold Reset, Soft Reset, and NMI exceptions are enabled.
CHAPTER 2 VR4120A Figure 2-62.
CHAPTER 2 VR4120A Figure 2-62. TLB/XTLB Refill Exception Handling (2/2) (b) Servicing TLB/XTLB Refill Exceptions (Software) Execute MFC0 instruction X/Context register Servicing by each exception routine ERET 162 • The occurrence of TLB Refill, TLB Invalid, and TLB Modified exceptions is disabled by using an unmapped space. • The occurrence of the Watch and Interrupt exceptions is disabled by setting EXL= 1. • Other exceptions are avoided in the OS programs.
CHAPTER 2 VR4120A Figure 2-63.
CHAPTER 2 VR4120A Figure 2-64.
CHAPTER 2 VR4120A 2.6 Initialization Interface This section describes the reset sequence of the VR4120A Core. For details about factors of reset or reset of the whole VR4120A Core. 2.6.1 Cold reset In the VR4120A Core, a cold reset sequence is executed in the CPU core in the following cases: • • • • Hardware reset Deadman’s SW shutdown Software shutdown HAL Timer shutdown A Cold Reset completely initializes the CPU core, except for the following register bits.
CHAPTER 2 VR4120A 2.6.3.1 Power modes The VR4120A supports four power modes: Fullspeed mode, Standby mode, Suspend mode, and Hibernate mode. (1) Fullspeed mode This is the normal operation mode. The VR4120A’s default status sets operation under Fullspeed mode. After the processor is reset, the VR4120A returns to Fullspeed mode. (2) Standby mode When a STANDBY instruction has been executed, the processor can be set to Standby mode.
CHAPTER 2 VR4120A 2.6.3.2 Privilege mode The VR4120A supports three system modes: kernel expanded addressing mode, supervisor expanded addressing mode, and user expanded addressing mode. These three modes are described below. (1) Kernel expanded addressing mode When the Status register’s KX bit has been set, an expanded TLB miss exception vector is used when a TLB miss occurs for the kernel address. While in kernel mode, the MIPS III operation code can always be used, regardless of the KX bit.
CHAPTER 2 VR4120A 2.7 Cache Memory This section describes in detail the cache memory: its place in the VR4120A Core memory organization, and individual organization of the caches. 2.7.1 Memory organization Figure 2-65 shows the VR4120A Core system memory hierarchy. In the logical memory hierarchy, the caches lie between the CPU and main memory. They are designed to make the speedup of memory accesses transparent to the user.
CHAPTER 2 VR4120A 2.7.2 Cache organization This section describes the organization of the on-chip data and instruction caches. Figure 2-66 provides a block diagram of the VR4120A Core cache and memory model. Figure 2-66.
CHAPTER 2 VR4120A Figure 2-67. Instruction Cache Line Format 22 21 0 V PTag 1 22 31 0 Data Data Data Data PTag : Physical tag (bits 31 to 10 of physical address) V : Valid bit Data : Cache data 2.7.2.2 Organization of the data cache (D-cache) Each line of D-cache data has an associated 25-bit tag that contains a 22-bit physical address, a Valid bit, a Dirty bit, and a Write-back bit.
CHAPTER 2 VR4120A 2.7.2.3 Accessing the caches Figure 2-69 shows the virtual address (VA) index into the caches. The number of virtual address bits used to index the instruction and data caches depends on the cache size. (1) Data cache addressing Using VA (12:4). The most-significant bit is VA12 because the cache size is 8 Kbytes. The least-significant bit is VA4 because the line size is 4 words (16 bytes). (2) Instruction cache addressing Using VA (13:4).
CHAPTER 2 VR4120A 2.7.3.1 Cache write policy The VR4120A Core manages its data cache by using a write-back policy; that is, it stores write data into the cache, instead of writing it directly to memory Note . Some time later this data is independently written into memory. In the VR4120A implementation, a modified cache line is not written back to memory until the cache line is to be replaced either in the course of satisfying a cache miss, or during the execution of a write-back CACHE instruction.
CHAPTER 2 VR4120A 2.7.5 Cache state transition diagrams The following section describes the cache state diagrams for the data and instruction cache lines. These state diagrams do not cover the initial state of the system, since the initial state is system-dependent. 2.7.5.1 Data cache state transition The following diagram illustrates the data cache state transition sequence.
CHAPTER 2 VR4120A 2.7.6 Cache data integrity Figures 2-72 to 2-86 shows checking operations for various cache accesses. Figure 2-72. Data Check Flow on Instruction Fetch Start Hit Tag Check Miss Refill (See Figure 2-85) Data Fetch END Figure 2-73.
CHAPTER 2 VR4120A Figure 2-74. Data Check Flow on Store Operations Start Hit Tag Check Miss V bit, W bit V = 1 (valid) and W = 1 (dirty) Write-back and Refill (see Figure 2-86) V = 0 (invalid) or W = 0 (clean) Refill (see Figure 2-85) Data Write to Data Cache END Figure 2-75.
CHAPTER 2 VR4120A Figure 2-76. Data Check Flow on Index_Writeback_Invalidate Operations Start V bit = 0 (Invalid) = 1 (Valid) W bit = 0 (Clean) = 1 (dirty) Write-back (see Figure 2-84) Valid bit and W bit Clear END Figure 2-77.
CHAPTER 2 VR4120A Figure 2-78. Data Check Flow on Index_Store_Tag Operations Start Tag Write from TagLo END Figure 2-79.
CHAPTER 2 VR4120A Figure 2-80. Data Check Flow on Hit_Invalidate Operations Start Tag Check Miss or Invalid Hit Valid bit Clear END Figure 2-81.
CHAPTER 2 VR4120A Figure 2-82. Data Check Flow on Fill Operations Start Refill (see Figure 2-85) END Figure 2-83.
CHAPTER 2 VR4120A Figure 2-84. Writeback Flow Write-back to memory No EOD ? Yes Figure 2-85.
CHAPTER 2 VR4120A Figure 2-86. Writeback & Refill Flow Write-back to memory EOD ? No Yes Refill Start Error bit Write data to cache EOD ? OK No Error Cache line Invalid Bus Error Exception Yes Remark Write-back Procedure: On a store miss write-back, data tag is checked and data is transferred to the write buffer. If an error is detected in the data field, the write back is not terminated; the erroneous data is still written out to main memory.
CHAPTER 2 VR4120A 2.8 CPU Core Interrupts Four types of interrupt are available on the CPU core. These are: one non-maskable interrupt, NMI five ordinary interrupts two software interrupts one timer interrupt For the interrupt request input to the CPU core. 2.8.1 Non-maskable interrupt (NMI) The non-maskable interrupt is acknowledged by asserting the NMI signal (internal), forcing the processor to branch to the Reset Exception vector.
CHAPTER 2 VR4120A 2.8.5 Asserting interrupts 2.8.5.1 Detecting hardware interrupts Figure 2-88 shows how the hardware interrupts are readable through the Cause register. The timer interrupt signal, IP7, is directly readable as bit 15 of the Cause register. Bits 4 to 0 of the Interrupt register are bit-wise ORed with the current value of the Int4 to 0 signals and the result is directly readable as bits 14 to 10 of the Cause register. IP1 and IP0 of the Cause register, which are described in Section 2.
CHAPTER 2 VR4120A 2.8.5.2 Masking interrupt signals Figure 2-89 shows the masking of the CPU core interrupt signals. Cause register bits 15 to 8 (IP7 to IP0) are AND-ORed with Status register interrupt mask bits 15 to 8 (IM7 to IM0) to mask individual interrupts. Status register bit 0 is a global Interrupt Enable (IE). It is ANDed with the output of the AND-OR logic shown in Figure 2-89 to produce the CPU core interrupt signal. The EXL bit in the Status register also enables these interrupts.
CHAPTER 3 SYSTEM CONTROLLER 3.1 Overview Register map This block is an internal system controller for the µPD98502. System controller provides bridging function among the CPU system bus “SysAD”, NEC original high-speed on-chip bus “IBUS” and memory bus for SDRAM/PROM/flash. Features of system controller are as follows.
CHAPTER 3 SYSTEM CONTROLLER • 66-MHz IBUS clock rate • Supports 266-MB/sec (32 bits @66 MHz) bursts on IBUS. • Support endian conversion between memory and IBUS slave I/F • Support endian conversion between SyaAD bus and IBUS master I/F 3.1.4 UART • Universal Asynchronous Receiver/Transmitter • Modem control functions • Even, odd or no parity bit generation • Fully prioritized interrupt control 3.1.5 EEPROM • 165/250-kHz clock rate (Depend on CPU clock rate ; 66/100 MHz) • Support only 3.
CHAPTER 3 SYSTEM CONTROLLER 3.1.
CHAPTER 3 SYSTEM CONTROLLER 3.1.
CHAPTER 3 SYSTEM CONTROLLER 3.2 Registers 3.2.1 Register map Following Table summarizes the controller’s register set. The base address for the set is 1000_0000H in the physical address space.
CHAPTER 3 SYSTEM CONTROLLER Offset Address 1000_00D8H Register Name MACAR1 R/W R Access W/H/B Description MAC Address Register 1 1000_00DCH MACAR2 R W/H/B MAC Address Register 2 1000_00E0H MACAR3 R W/H/B MAC Address Register 3 1000_00E4H: 1000_00FCH N/A - - Reserved for future use 1000_0100H RMMDR R/W W Boot ROM Mode Register 1000_0104H RMATR R/W W Boot ROM Access Timing Register 1000_0108H SDMDR R/W W SDRAM Mode Register 1000_010CH SDTSR R/W W SDRAM Type Selection Re
CHAPTER 3 SYSTEM CONTROLLER 3.2.2 S_GMR (General Mode Register) The general mode register “S_GMR” is a read-write and 32-bit word-aligned register. After initializing, VR4120A sets the IAEN bit to enable the IBUS arbiter. S_GMR is initialized to 0 at reset and contains the following fields: Bits Field R/W Default Description 31:10 Reserved R/W 0 Hardwired to 0.
CHAPTER 3 SYSTEM CONTROLLER 3.2.4 S_ISR (Interrupt Status Register) The interrupt status register “S_ISR” is a read-clear and 32-bit word-aligned register. S_ISR indicates the interruption status from SysAD/IBUS interfaces, timer, UART and so on. If corresponding bit in S_IMR (Interrupt Mask Register) is set and the interrupt is not masked, system controller interrupts to VR4120A using interrupt signal. The bit in S_ISR is reset after being read by the VR4120A.
CHAPTER 3 SYSTEM CONTROLLER 3.2.5 S_IMR (Interrupt Mask Register) The interrupt mask register “S_IMR” is a read-write and 32-bit word-aligned register. S_IMR masks interruption for each corresponding incident. A mask bit, which locates in the same bit location to a corresponding bit in S_ISR, controls interruption triggered by the incident. If a bit of this register is reset to 0, the corresponding bit of the S_ISR is masked. If it is set to 1, the corresponding bit is unmasked.
CHAPTER 3 SYSTEM CONTROLLER 3.2.6 S_NSR (NMI Status Register) The interrupt status register “S_NSR” is a read-clear and 32-bit word-aligned register. S_NSR indicates the nonmaskable interruption “NMI” status from SysAD/IBUS interfaces, external NMI, memory interface and so on. If corresponding bit in S_NER (NMI Enable Register) is set and the NMI is enabled, system controller interrupts to VR4120A using non-maskable interrupt signal. The bit in S_NSR is reset after being read by the VR4120A.
CHAPTER 3 SYSTEM CONTROLLER 3.2.7 S_NER (NMI Enable Register) The NMI enable register “S_NER” is a read-write and 32-bit word-aligned register. S_NER enables NMI for each corresponding incident. A enable bit, which locates in the same bit location to a corresponding bit in S_NSR, controls interruption triggered by the incident. If a bit of this register is reset to 0, the corresponding bit of the S_NSR is disabled. If it is set to 1, the corresponding bit is enabled.
CHAPTER 3 SYSTEM CONTROLLER 3.2.9 S_IOR (IO Port Register) The IO port register “S_IOR” is a read-write and 32-bit word-aligned register. IO port register is used to indicate the status of software. Each bit of the following POM_OUT fields is connected to the external IO port (POM[7:0]) directly. S_IOR is initialized to 0 at reset and contains the following fields: Bits Field R/W Default Description 31:8 Reserved R/W 0 Hardwired to 0.
CHAPTER 3 SYSTEM CONTROLLER 3.2.10 S_WRCR (Warm Reset Control Register) The warm reset control register “S_WRCR” is a write-only and 32-bit word-aligned register. S_WRCR generates warm-reset request to USB Controller, Ethernet Controller, ATM Cell Processor, UART, and PCI Controller independently. S_WRCR is initialized to 0 at reset and contains the following fields: Bits Field R/W Default Description 31:6 Reserved W 0 Hardwired to 0.
CHAPTER 3 SYSTEM CONTROLLER 3.2.11 S_WRSR (Warm Reset Status Register) The warm reset status register “S_WRSR” is a read-only and 32-bit word-aligned register. S_WRSR indicates the response from USB Controller, Ethernet Controller, ATM Cell Processor, UART, and PCI Controller independently. S_WRSR is initialized to 0 at reset and contains the following fields: Bits Field R/W Default Description 31:6 Reserved R 0 Hardwired to 0.
CHAPTER 3 SYSTEM CONTROLLER 3.2.12 S_PWCR (Power Control Register) The power control register “S_PWCR” is a read-write and 32-bit word-aligned register. S_PWCR requests to keep the idle state for USB Controller, Ethernet Controller, ATM Cell Processor, and PCI Controller by setting following IDRQ fields. VR4120A must request these blocks to keep the idle state and check their acknowledgement by reading the power status register “S_PWSR” prior to perform suspend by setting following STOP fields.
CHAPTER 3 SYSTEM CONTROLLER 3.2.13 S_PWSR (Power Status Register) The power status register “S_PWSR” is a read-only and 32-bit word-aligned register. The IDLE field in S_PWSR indicates the status that it is ready to suspend. The WKUP filed in S_PWSR indicates the wakeup request. When a bit of IDLE fields gets 1, VR4120A can disable the system clock for the corresponding device by setting the STOP field in S_PWCR.
CHAPTER 3 SYSTEM CONTROLLER 3.3 CPU Interface The system controller provides the direct interface for the VR4120A using the 32-bit SysAD bus operated at 100 MHz or 66 MHz. 3.3.1 Overview • Connects to the VR4120A CPU bus “SysAD bus” directly. • Supports all VR4120A bus cycles at 66 MHz or 100 MHz. • Supports data rate D only. • Supports sequential ordering only. • 4-word (16-byte) x 4-entry write command buffer. • Little-endian or big-endian byte order. • Not support 8-word burst R/W on SysAD bus 3.3.
CHAPTER 3 SYSTEM CONTROLLER Table 3-1. Endian Configuration Table BIG pin ENDCEN pin Status register RE field in VR4120A Endian in VR4120A Endian in system controller Endian converter operation 0 0 0 LITTLE LITTLE Transparent 0 1 0 LITTLE LITTLE Transparent 1 0 0 BIG LITTLE Data swap mode 1 1 0 BIG LITTLE Address swap mode Remark VR4120A does not support reverse endian mode. Table 3-2.
CHAPTER 3 SYSTEM CONTROLLER 3.3.6 I/O performance The following table indicates the I/O performance accessing from the VR4120A through the system controller.
CHAPTER 3 SYSTEM CONTROLLER 3.4 Memory Interface The VR4120A accesses memory attached to the controller in the normal way, by addressing the memory space. 3.4.
CHAPTER 3 SYSTEM CONTROLLER 3.4.3 Memory signal connections ADDRESS SMA[20:0] DATA D[31:0] CS_B OE_B WE_B SMD[31:0] A[20:0] SRMCS_B SRMOE_B SMA[20:0] SMA[20:0] SMD[31:0] SMD[31:0] Flash PROM µPD98502 A[13:0] SDWE_B DQ[31:0] WE_B CS_B RAS_B CAS_B SDCS_B SDRAS_B SDCAS_B SDCKE[1:0] CKE CLK[1:0] DQM[3:0] SDCLK[1:0] SDQM[3:0] (SDQM=SMA[17:14]) SDRAM Table 3-3.
CHAPTER 3 SYSTEM CONTROLLER 3.4.4 Memory performance The latency of memory accesses is determined by memory type, speed and prefetch scheme. Following lists some examples of access latencies. 66-MHz or 100-MHz memory-bus clock is required for each transfer of a 4-word (16byte) CPU instruction-cache line fill. The first number in the “SysAD clocks” column is for the first word; the remaining numbers are for the subsequent words. The most common combinations are shown. Table 3-4.
CHAPTER 3 SYSTEM CONTROLLER 3.4.5 RMMDR (ROM Mode Register) The ROM mode register “RMMDR” is a read-write and 32-bit word-aligned register. RMMDR is used to setup the PROM/flash memory interface. RMMDR is initialized to 0 at reset and contains the following fields: Bits Field R/W Default Description 31:9 Reserved R/W 0 Hardwired to 0. 8 WM R/W 0 Write mask: 0 = masked. Flash data is protected from unintentional write. 1 = not masked. Flash data is not protected.
CHAPTER 3 SYSTEM CONTROLLER N o rm a l R O M R e a d C yc le T0 T1 T2 T3 F L A S H M e m o ry W rite C yc le T4 T0 T1 T2 T3 F A T (= 4) T4 T5 T6 F A T (= 6) SDC LK V alid R ead Ad d ress SM A V alid W rite Ad d ress SRM CS_B H SRM OE_B H S D W E _B H i-Z SM D R ead D ata W rite D ata R O M B u rs t R e a d C yc le T0 T1 T2 T3 T4 T5 T6 T7 F A T (= 4) T8 T9 T 10 T 11 F A T (= 4) SDC LK SM A V alid R ead Ad d ress in v alid V alid R ead Ad d ress SRM CS_B SRM OE_B
CHAPTER 3 SYSTEM CONTROLLER 3.4.7 SDMDR (SDRAM Mode Register) The SDRAM mode register “SDMDR” is a read-write and 32-bit word-aligned register. SDMDR is used to setup the SDRAM interface. SDMDR is initialized to 330H at reset and contains the following fields: Bits Field R/W Default Description 31:10 Reserved R/W 0 Hardwired to 0. 9:8 RCD R/W 11 SDRAM RAS-CAS delay: 00 = reserved 01 = 2 clocks 10 = 3 clocks 11 = 4 clocks (default) 7 Reserved R/W 0 Hardwired to 0.
CHAPTER 3 SYSTEM CONTROLLER 3.4.8 SDTSR (SDRAM Type Selection Register) The SDRAM type selection register “SDTSR” is a read-write and 32-bit word-aligned register. SDTSR is used to setup the type of SDRAM. SDTSR is initialized to 0 at reset and contains the following fields: Bits Field R/W Default Description 31:10 Reserved R/W 0 Hardwired to 0.
CHAPTER 3 SYSTEM CONTROLLER 3.4.9 SDPTR (SDRAM Precharge Timing Register) The SDRAM precharge timing register “SDPTR” is a read-write and 32-bit word-aligned register. SDPTR is used to set the precharge timing for the SDRAM controller. SDPTR is initialized to 142H at reset and contains the following fields: Bits Field R/W Default Description 31:9 Reserved R/W 0 Hardwired to 0. 8 DPL R/W 1 Input data -> precharge command timing (tDPL): 0 = 1 clock 1 = 2 clocks (default) 66 MHz: 15.
CHAPTER 3 SYSTEM CONTROLLER 3.4.11 SDRCR (SDRAM Refresh Timer Count Register) The SDRAM refresh timer count register “SDRCR” is a read-only and 32-bit word-aligned register. SDRCR is a 16bit timer that causes an SDRAM refresh when it expires. The SDRAM refresh controller automatically reloads this free-running timer. SDRCR is initialized to 200H at reset and contains the following fields: Bits Field R/W Default Description 31:16 Reserved R 0 Hardwired to 0.
CHAPTER 3 SYSTEM CONTROLLER 3.4.13 Boot ROM The system controller supports up to 8 MB of boot memory. This memory must be populated with either of the following two types of memory devices: PROM/flash memory. 3.4.13.1 Boot ROM configuration and address ranges Boot ROM can be populated with PROM or 85-ns flash chips, and it must have an access time of 200 ns or less. The system controller supports 8, 16 and 32-bit boot ROM at locations 1F80_0000H through 1FFF_FFFFH in the physical memory space on VR4120A.
CHAPTER 3 SYSTEM CONTROLLER Table 3-7.
CHAPTER 3 SYSTEM CONTROLLER 3.4.1.
CHAPTER 3 SYSTEM CONTROLLER 3.4.14 SDRAM 3.4.14.1 SDRAM address range System memory can be populated with SDRAM chips, and it must have an access time of 10 ns or less. The system controller supports 16-Mbit or 64-Mbit and 128-Mbit SDRAM at locations 0000_0000H through 01FF_FFFFH in the physical memory space on VR4120A. The SDRAM supports VR4120A cache operations. Table 3-8. SDRAM Size Configuration at Reset SDMDR.
CHAPTER 3 SYSTEM CONTROLLER 3.4.1.4 SDRAM word ordering Following table indicates the word-address order for a 4-word instruction-cache line fill from SDRAM. This order is determined by the SDRAM chips’ burst type, which is programmed during the memory initialization procedure. The memory controller programs the burst type and word order the same for all SDRAM chips connected to it (in the system memory ranges). The term “sequential” in this table refers to the SDRAM burst type.
CHAPTER 3 SYSTEM CONTROLLER S D R A M C onfiguration 4 MB S M D [15:0] S M D [31:0] µ P D98502 (S ystem Controller) S M D[31:16] DQ [15:0] DQ [15:0] S M A [11:0] S M A [11:0] S M A [13:0] A [11:0] A [11:0] S D W E _B W E _B W E _B S D C A S _B C A S _B R A S _B S D R A S _B S D C S _B S DC LK [1:0] S D C K E [1:0] S DQ M [2][0] R A S _B SDRAM 1 M x 16 SDRAM C S _B C S _B S D C LK [0] S D C LK [1] CLK CLK S D C K E [0] S D C K E [1] CKE CKE S D Q M [0] S D Q M [2] LDQ M LDQ M S D
CHAPTER 3 SYSTEM CONTROLLER 3.4.15 SDRAM refresh The system controller supports CAS-Before-RAS (CBR) DRAM refresh to all SDRAM address ranges. The refresh clock is derived from the system clock; its rate is determined by programming the RCR filed in the SDRAM Refresh Mode Register “SDRMR”. The refresh logic requests access to SDRAM each time the counter reaches 0. The refresh logic can accumulate up to a maximum of 15 refresh requests while it is waiting for the bus.
CHAPTER 3 SYSTEM CONTROLLER 3.4.18 SDRAM memory initialization The following sections describe the configuration sequence used in this initialization. 3.4.1.1 Power-on initialization sequence by memory controller The following sequence to configure memory is done automatically after reset: 1. Waits for 100 µs after power-on. 2. Performs all bank precharges. 3. Performs eight sequential auto refreshes (CBR). 3.4.1.
CHAPTER 3 SYSTEM CONTROLLER 3.5 IBUS Interface 3.5.
CHAPTER 3 SYSTEM CONTROLLER Outline figure of Endian converter 1 byte 2 bytes 31 0 12 34 56 78 31 56 34 0 12 0 78 word 31 34 56 78 31 12 31 12 0 56 78 12 0 34 56 78 31 34 0 12 34 56 78 3 bytes 31 0 12 34 31 0 56 34 56 Big Endian: offset 0H · · Little Endian: 0H 78 Big Endian: offset 1H · · Little Endian: 1H 31 0 12 34 31 56 0 34 56 78 3.5.
CHAPTER 3 SYSTEM CONTROLLER 3.5.4 ITCNTR (IBUS Timeout Timer Control Register) The IBUS Timeout Timer control register “ITCNTR” is a read-write and word-aligned 32-bit register. ITCNTR is used to enable use of the IBUS Timeout Timer. ITCNTR is initialized to 0H at reset and contains the following field: Bits Field R/W Default Description 31:1 Reserved R/W 0 Hardwired to 0. 0 ITWEN R/W 0 IBUS Timeout Timer enable 1 = Enable 0 = Disable 3.5.
CHAPTER 3 SYSTEM CONTROLLER 3.6 DSU (Deadman’s SW Unit) 3.6.1 Overview The DSU detects when the VR4120A is in runaway (endless loop) state and resets the VR4120A. The use of the DSU to minimize runaway time effectively minimizes data loss that can occur due to software-related runaway states. 3.6.2 DSUCNTR (DSU Control Register) This register is used to enable use of the Deadman’s Switch functions. DSUCNTR is a 32-bit word-aligned register. Default is 0H.
CHAPTER 3 SYSTEM CONTROLLER 3.6.5 DSUTIMR (DSU Elapsed Time Register) This register indicates the elapsed time for the current Deadman’s Switch timer. DSUTIMR is a read-only and 32-bit word-aligned register. Default is 0H.
CHAPTER 3 SYSTEM CONTROLLER 3.7 Endian Mode Software Issues 3.7.1 Overview The native endian mode for MIPS processors, like Motorola and IBM 370 processors, is big endian. However, the native mode for Intel (which developed the PCI standard) and VAX processors is little endian. For PCI-compatibility reasons, most PCI peripheral chips operate natively in little-endian mode. While the µPD98502 is natively little-endian, it supports either big- or little-endian mode on the SysAD bus.
CHAPTER 3 SYSTEM CONTROLLER Figure 3-1. Bit and Byte Order of Endian Modes Big End Little End Big-Endian 4 31 BYTE4 0 BYTE5 BYTE6 BYTE7 0 BYTE0 BYTE1 BYTE2 BYTE3 MSB LSB LSB = Least Significant Byte MSB = Most Significant Byte Big End Little End Little-Endian 4 31 BYTE7 0 BYTE6 BYTE5 BYTE4 0 BYTE3 BYTE2 BYTE1 BYTE0 MSB LSB If the access type matches the data item type, no swapping of data sub-items is necessary.
CHAPTER 3 SYSTEM CONTROLLER However, when making half-word accesses into a data array consisting of word data, access to the moresignificant half word requires the address corresponding to the less significant half word (and vice versa). Such code is not endian-independent. A super-group access (for example, accessing two half words simultaneously as a word from a half-word data array) causes the same problem.
CHAPTER 4 ATM CELL PROCESSOR 4.1 Overview This section describes functional specifications of ATM cell processor unit. 4.1.1 Function features Features of ATM Cell Processor with out Firmware (F/W) is as follows: • Data Transmission Capacity Aggregated transmission capacity is 50 Mbps, 25 Mbps for downstream and 25 Mbps for upstream. • Supports ATM Adaptation Layers (AAL) AAL-0 (raw cells), AAL-2 and AAL-5 are supported. • Supports Service Classes CBR, VBR and UBR.
CHAPTER 4 ATM CELL PROCESSOR 4.1.2 Block diagram of ATM cell processor Figure 4-1. Block Diagram of ATM Cell Processor VR4120A RISC Processor Ethernet Controller #1, #2 USB Controller IBUS IBUS I/F Peripherals SAR REGS System Controller Work RAM UTOPIA BUS Controller Data RAM RISC Core I cache IRAM SDRAM I/F ATM Cell Processor SDRAM UTOPIA Level2 UTOPIA MGR This block is an ATM cell processor.
CHAPTER 4 ATM CELL PROCESSOR 4.1.2.3 UTOPIA bus controller This block has some H/W resources – DMA controller, FIFOs, CRC calculators/checkers. Its features are as follows: • Scatter/Gather-DMA controller that can operate the distributed data according to descriptor tables, without F/W help. The DMA controller is used for each transmission and reception. Normal DMA mode is also supported. Furthermore, this DMA controller updates the information related to the DMA operations in the VC table in Work RAM.
CHAPTER 4 ATM CELL PROCESSOR 4.1.2.4 Other blocks Work-RAM is 12 K-byte memory. Tables and Pool Descriptors are located in this RAM. It is shared between MCU and UTOPIA Bus Controller block. It also can be accessed by VR4120A RISC Processor, using Indirect-Access. 4.1.3 ATM cell processing operation overview In this section, only overview is described. Please refer to section 4.7 for more detailed information. ATM Cell Processor supports AAL-5 SAR sublayer and ATM layer functions.
CHAPTER 4 ATM CELL PROCESSOR 4.1.3.1 AAL-5 SAR sublayer function When ATM Cell Processor transmits a cell in AAL-5 mode, it adds a trailer to the variable-length data, as well as padding, so that its overall length becomes a multiple of 48 bytes, thereby generating an AAL-5 PDU. When ATM Cell Processor receives cells, it stores them in the SDRAM in order to assemble a CPCS PDU. ATM Cell Processor verifies the trailer of the assembled CPCS PDU.
CHAPTER 4 ATM CELL PROCESSOR Figure 4-4. ATM Cell CLP 1 VCI 4 GFC 48 byte VPI 5 6 Segment HEC 3 PTI VPI 2 7 8 bit header The function of each field in the header is as follows: (a) GFC (General Flow Control) field: Used for flow control. At transmission, the value set in the packet descriptor is written into this field. At reception, this field is ignored. (b) VPI/VCI fields: VPI (Virtual Path Identifier), VCI (Virtual Channel Identifier) are routing fields which indicate the routing path.
CHAPTER 4 ATM CELL PROCESSOR (3) Cell scheduling ATM Cell Processor uses Scheduling Table, Cell Timer and Tx VC table for the cell scheduling. Before the VR4120A starts transmitting a packet, it sets the rate information in Tx VC table. ATM Cell Processor calculates cell transmission interval from the rate information, and put the next transmission time in Scheduling Table. When the Cell Timer and the next transmission time of certain VC becomes equal, a cell belongs to the VC is transmitted.
CHAPTER 4 ATM CELL PROCESSOR 4.2 Memory Space Although the RISC Core in the ATM Cell Processor is a 32-bit MPU, its physical memory space is 24-bit width. Figure 4-6.
CHAPTER 4 ATM CELL PROCESSOR 4.2.1 Work RAM and register space Work RAM and Register Space are shown in Figure 4-7. The capacity of Work RAM is 16 KB max. In order to access Work RAM, the user has to use “Indirect Access Command”. In register space, A_GMR (general mode register), A_GSR (general status register), A_CMR (command register), A_CER (command extension register) and other registers will be mapped. In PHY space, PHY devices can be accessed through UTOPIA management I/F. Figure 4-7.
CHAPTER 4 ATM CELL PROCESSOR 4.4 Registers for ATM Cell Processing Registers in ATM Cell Processor block can be classified into 3 groups: SAR registers, DMA registers and FIFO Control registers. These registers can be accessed both VR4120A and RISC Core in ATM Cell Processor. 4.4.1 Register map Registers are used for SAR functions. VR4120A writes to these registers to control SAR functions and reads from these registers to know the status.
CHAPTER 4 ATM CELL PROCESSOR Offset Address Register Name R/W Access Description 1001_F0C8H A_TSR R/W W Time Stamp Register 1001_F0CCH: 1001_F1FCH N/A - - Reserved for future use 1001_F200H: 1001_F2FCH N/A - - Can not access from VR4120A RISC Core. This area is used for an internal function.
CHAPTER 4 ATM CELL PROCESSOR 4.4.2 A_GMR (General Mode Register) A_GMR is used to select operation mode of this block, enables/disables ATM SAR operations. After reset, VR4120A must write this register for initialization. Modification of A_GMR after starting Tx/Rx operations is prohibited. All bits of this register are writeable, but the bits 31-15, 13-2 are reserved for future use. Initial value is all zero. Bits Field R/W Default Description 31:15 Reserved R/W 0 Reserved for future use.
CHAPTER 4 ATM CELL PROCESSOR 4.4.4 A_IMR (Interrupt Mask Register) A_IMR masks interruption for each corresponding event. A Mask bit, which locates in the same bit location to a corresponding bit in A_GSR, masks interruption. If a bit of this register is reset to a ‘0’, the corresponding bit of the A_GSR is masked. If it is set to a ‘1’, the corresponding bit is unmasked. When the mask bit is reset and the bit in A_GSR is set, an interruption is issued to VR4120A.
CHAPTER 4 ATM CELL PROCESSOR 4.4.5 A_RQU (Receiving Queue Underrun Register) A_RQU shows the status of each pool. When a pool has no free buffers, the corresponding bit is set. ATM Cell Processor detects a pool empty when it receives a cell and try to send the cell to buffer. Whenever one of A_RQU bits is set, A_RQU bit in A_GSR will be set. In this block, only pool7 to pool0 will be used. If a bit is set to ‘1’, corresponding pool has no free buffers. Initial value is all zero.
CHAPTER 4 ATM CELL PROCESSOR 4.4.10 A_MSA0 to A_MSA3 (Mailbox Start Address Register) A_MSA0 to A_MSA3 shows start address of Receive Mailbox (Mailbox0 and Mailbox1) and Transmit Mailbox (Mailbox2 and Mailbox3) respectively. Initial value is all zero.
CHAPTER 4 ATM CELL PROCESSOR 4.4.13 A_MWA0 to A_MWA3 (Mailbox Write Address Register) A_MWA0 to A_MWA3 shows write address of Receive Mailbox (Mailbox0 and Mailbox1) and Transmit Mailbox (Mailbox2 and Mailbox3) respectively. Initial value is zero.
CHAPTER 4 ATM CELL PROCESSOR 4.4.18 A_T1R (T1 Time Register) A_T1R shows time which user allows ATM Cell Processor to spend to receive a whole of one packet. Initial value is “0000_FFFFH”. Bits Field R/W Default Description 31 Reserved R/W 0 Reserved for future use. Write ‘0’s. 30:0 A_T1R R/W FFFFH Allowable time to receive a whole of one packet 4.4.19 A_TSR (Time Stamp Register) A_TSR shows a value of the 32-bit counter that ATM Cell Processor counts its system clock.
CHAPTER 4 ATM CELL PROCESSOR 4.4.22 A_UMCMD (UTOPIA Management Interface Command Register) A_UMCMD selects operation mode of UTOPIA Management Interface. After reset, RISC Core must write this register to configure UTOPIA Management Interface. When BM bit is set to ‘0’, it means 8-bit mode and UMD [7:0] pins are valid. When BM bit is set to ‘1’, it means 16-bit mode. In this case, only half-word-aligned access is accepted. EM bit is set to ‘1’ only in 16-bit transfer mode.
CHAPTER 4 ATM CELL PROCESSOR 4.5 Data Structure ATM Cell Processor has Tx/Rx buffer structure similar to that of Ethernet Controller and USB Controller. 4.5.1 Tx buffer structure The following figure shows Tx buffer structure used by ATM Cell Processor. It consists of a packet descriptor, some buffer directories, and data buffers. A Rx buffer structure and a Tx buffer structure are similar, so that reconstructing buffer structure is not needed when sending out a received packet. Figure 4-8.
CHAPTER 4 ATM CELL PROCESSOR Figure 4-9. Tx Buffer Elements - T x packet descriptor 31 0 16 15 Attribute CPCS-U U CPI Tx buffer directory Address - T x buffer directory 31 0 Tx buffer desciptor 0 Tx buffer desciptor 1 Tx buffer desciptor 2 Tx buffer desciptor 3 Tx buffer desciptor 4 | Tx buffer desciptor N Tx link pointer - T x buffer descriptor 16 15 31 L DL 0 Size 0 Buffer A ddress - T x link pointer 0 31 0 DL 0 Tx buffer directory Address Figure 4-9 shows Tx buffer elements.
CHAPTER 4 ATM CELL PROCESSOR 4.5.1.1 Packet descriptor A packet descriptor contains two words shown as Figure 4-10. Its address is word aligned. Figure 4-10. Tx Packet Descriptor -Tx packet descriptor 31 87 16 15 Attribute 31 1 30 29 ENC 0 CPCS-UU 28 27 CLPM 26 24 23 CPI 20 PTI GFC 19 IM 31 18 17 C10 AAL 16 MB 0 Directory Address Table 4-1 is a list of Tx packet attributes. Detail will be given in Operation chapter. Table 4-1.
CHAPTER 4 ATM CELL PROCESSOR 4.5.1.2 Tx buffer directory Tx buffer directory contains some buffer descriptors, up to 255, and a link pointer. Its address is word aligned. The end of buffer directory must be a link pointer. Buffer descriptors must be read and served from the top in a sequential manner. 4.5.1.3 Tx buffer descriptor Both a Tx buffer descriptor and a Tx link pointer consist of 2 words.
CHAPTER 4 ATM CELL PROCESSOR Figure 4-12. Rx Pool Structure R x buffer directory R x pool0 descriptor R x buffer desc. R x pool1 descriptor R x buffer desc. D ata Buffer Size 1 to 64 kBytes D ata Buffer R x buffer desc. R x pool7 descriptor R x link pointer D ata Buffer R x buffer dir. R x buffer desc. R x buffer desc. D ata Buffer R x buffer desc. D ata Buffer R x link pointer D ata Buffer R x buffer dir. R x buffer desc. R x buffer desc. D ata Buffer R x buffer desc.
CHAPTER 4 ATM CELL PROCESSOR Figure 4-13.
CHAPTER 4 ATM CELL PROCESSOR 4.5.2.1 Rx pool descriptor A pool descriptor contains two words shown as Figure 4-14. Its address is word aligned. Figure 4-14. Rx Pool Descriptor -R x pool descrip tor 31 30 0 24 23 28 27 A lert le vel all 0 16 15 dir. size in a pool 0 R em aining # of dir. in the pool 31 0 R x buffer directory Address Table 4-2.
CHAPTER 4 ATM CELL PROCESSOR Figure 4-15. Rx Buffer Descriptor/ Link Pointer -Rx buffer descriptor 31 30 L 1 16 15 Attribute 0 Size 31 0 Buffer Address -Rx link pointer 31 30 0 0 16 15 Reserved 31 0 0 Directory Address 4.5.2.4 Rx data buffer Rx Data buffer contains actual received cell data. Size of a buffer can vary from 1 byte to 64 kbytes. Its address is byte aligned.
CHAPTER 4 ATM CELL PROCESSOR 4.6 Initialization This ATM Cell Processor is initialized by firmware that is based RISC instruction. 4.6.1 Before starting RISC core RISC Core has 1 MB of Instruction space and 8 KB of physical Instruction RAM and 8 KB of instruction cache. The Instruction space will be mapped to the external system memory space. Address of instruction space will be translated by adding content of A_INBAR. VR4120A will set A_INBAR during initialization.
CHAPTER 4 ATM CELL PROCESSOR 4.6.2 After RISC core’s F/W is starting RISC Core starts its operation from address xx00_0000H. When it starts fetching an instruction located in address xx00_0000H, a dedicated H/W will stop RISC Core and will copy a block of instructions. This copy operation will be handled in the same manner as I-cache replacement. Lower 8 KB of Instruction space in RISC Core will be copied on Instruction RAM because it will contain interruption vector table.
CHAPTER 4 ATM CELL PROCESSOR 4.7 Commands Here, basic commands used in AAL-5 operation are described. Other commands used in AAL-2, OAM and cell switching functions are described in µPD98502 Application Note (to be planned). ATM Cell Processor provides VR4120A with the following basic commands. Table 4-3. Commands Command What this block does Set_Link_Rate Set PHY Link Rate Open_Channel Reserves VC table area in Work RAM. Close_Channel Releases VC table area. Tx_Ready Starts transmission process.
CHAPTER 4 ATM CELL PROCESSOR 4.7.1 Set_Link_Rate command This command is used to set the link rate of ATM PHY interface. After initializing ATM Cell Processor, this command has to be issued once, before any packet is transmitted. Figure 4-18. Set_Link_Rate Command [Set_Link_Rate command] CMR 0 1 1 31 30 2 1 0 PHY No. 28 27 26 20 19 Link Rate 16 15 0 9 PHY No. PHY Number. Link Rate Actual Link Rate is inserted in this field. The format of the rate is following.
CHAPTER 4 ATM CELL PROCESSOR 4.7.3 Close_Channel command The Close_Channel command is used to close a send or receive channel. Upon accepting this command, ATM Cell Processor returns the VC table to VC Table pool. The indication that ATM Cell Processor returns for this command has the following format: Figure 4-20.
CHAPTER 4 ATM CELL PROCESSOR 4.7.4 Tx_Ready command The Tx_Ready command is used by the VR4120A to notify ATM Cell Processor that a transmit packet has been added for a specified channel (a new packet descriptor has been set in system memory queue). Upon receiving this command, ATM Cell Processor makes the scheduling table active to perform scheduling. In this command, when it detects some errors, writes E bit in A_CMR. This command has the following format: Figure 4-21.
CHAPTER 4 ATM CELL PROCESSOR 4.7.5 Add_Buffers command The Add_Buffers command is used to add unused buffer directories to a single receive free buffer pool. In this command, when ATM Cell Processor detects some errors, it writes E bit in A_CMR. This command has the following format: Figure 4-22. Add_Buffers Command [Add_Buffers command] CMR 0 1 1 0 1 0 Pool No.
CHAPTER 4 ATM CELL PROCESSOR 4.7.6 Indirect_Access command The Indirect_Access command is used to perform read/write access to Work RAM. Figure 4-23. Indirect_Access Command [Indirect_Access command] CMR R/W B3 B2 B1 B0 0 31 Address 29 28 27 26 25 24 23 0 2 1 0 CER Data 31 0 Indirect_Access command R/W Specifies whether access to the target is a read or a write access. 1: Read 0: Write B0, B1, B2, B3 For write access, used to select bytes.
CHAPTER 4 ATM CELL PROCESSOR Figure 4-24. Work RAM Usage W o rk R A M (1 0 K b yte s ) xx80_3F FF H T em porary D ata xx80_1840H Pack et Info Structure Pool (4 W ords x 64) 1024 bytes Flow T able P ool (4 W ords x 64) 1024 bytes Free Block Pool /for VC T able/ (16 W ords x 64) 4096 bytes Pool D escriptor (2 W ords x 8) 64 bytes xx80_1440H xx80_1040H xx80_0040H xx80_0000H 4.8.
CHAPTER 4 ATM CELL PROCESSOR 4.8.2.1 Transmission procedure (a) Setting transmitting data Before transmitting a packet, VR4120A places a packet data to be sent in system memory and sets the packet descriptor. (b) Opening the send channel If VR4120A needs a new channel for transmitting of the packet data, VR4120A issues Open_Channel command. When VR4120A issues the command, ATM Cell Processor assigns a new VC Table pool block in Work RAM and reports its start address to VR4120A using a command indication.
CHAPTER 4 ATM CELL PROCESSOR 4.8.2.2 Transmit queue Tx_Ready command has to be issued in order to transmit a packet. However, VR4120A doesn’t have to wait Tx indication before issuing next Tx_Ready command for the same VC. When VR4120A issues Tx_Ready command before completing transmission process for the previous packet, ATM Cell Processor builds Tx Queue for that VC. Figure 4-25.
CHAPTER 4 ATM CELL PROCESSOR (2) Packet descriptor Figure 4-27. Transmit Queue Packet Descriptor 1 0 ENC CLPM PTI 31 30 29 28 27 26 GFC 24 23 IM C10 AAL MB CPCS-UU 20 19 18 17 16 15 CPI 8 7 0 Buffer Directory Address 31 ENC CLPM PTI GFC IM C10 0 Encapsulation mode is indicated. 1 LLC encapsulation 0 No encapsulation CLP bit in the packet header is indicated. 00 Sets CLP bit in all cells as 0. 11 Sets CLP bit in all cells as 1.
CHAPTER 4 ATM CELL PROCESSOR (3) Tx VC table Figure 4-28. Tx VC Table Word 0 V ENC CLPM PTI 31 30 29 28 27 26 Word 1 L 0 24 23 IM C10 AAL MB 27 26 CPSS-UU 20 19 18 17 16 15 PRIORITY 31 30 Word 2 GFC CPI 8 7 0 VPI/VCI 24 23 0 No. OF BYTES TRANSMITTED IN THIS PACKET REMAINING BYTES IN CURRENT BUFFER 31 16 15 Word 3 0 CRC-32 COUNT 31 0 Word 4 BUFFER READ ADDRESS 31 0 Word 5 NEXT BUFFER ADDRESS 31 0 Word 6 MBS0 MBS RESERVED PHY No.
CHAPTER 4 ATM CELL PROCESSOR Word0 Identical to the contents of Word0 in the packet descriptor in system memory. The initial value must be all zeros. ATM Cell copies the Word0 in the packet descriptor into this field. L This bit is used internally for SAR processing. The initial value must always be a 1. PRIORITY Specifies send priority. 111: CBR 110: VBR 010: UBR VPI/VCI VPI/VCI values to be contained in the cell header No.
CHAPTER 4 ATM CELL PROCESSOR (2) Raw cell transmission When host sends the non AAL-5 traffic packet which is not OAM F5 cell, host sets “AAL” bit in the packet descriptor to a 0 and “PTI” field “0xx” which indicates user data. In this case, ATM Cell Processor doesn’t calculate or add AAL-5 trailer. If host sets “C10” bit in packet descriptor to a 1, ATM Cell Processor calculates and adds CRC-10 to each cell to be transmitted. Figure 4-29.
CHAPTER 4 ATM CELL PROCESSOR 4.8.2.6 LLC encapsulation If LLC encapsulation is indicated in Tx VC table, ATM Cell Processor adds the LLC header to the top of the IP packet. ATM Cell Processor always encapsulates CPCS-PDU as Internet IP PDU. Figure 4-31. LLC Encapsulation Format LLC AAH-AAH-03H 3 bytes OUI 00H-00H-00H 3 bytes EtherType 08H-00H 2 bytes IP PDU 4.8.3 Receiving function Receiving data structure is described in Section 4.5.2 Rx pool structure. 4.8.3.
CHAPTER 4 ATM CELL PROCESSOR (1) Rx VC table Figure 4-32. Receive VC Table Word 0 CLP BFA 0 RID DD DP 0 CI OD A/R MB POOL No. 31 30 29 28 27 26 25 24 23 22 21 20 Word 1 UINFO 16 15 0 T1 TIME STAMP MAX. No.
CHAPTER 4 ATM CELL PROCESSOR CLP Set to a 1 if the CLP in the header of at least one cell of the packets being received is equal to a 1. BFA Set to a 1 if the free buffer assigned to this VC exists. RID Set to a 1 if an error occurs while a packet is being received. Then, the subsequent cells of the packet, including the last cell, are discarded. DD If a free buffer is not assigned, the cell is discarded and this field is set to a 1. DP Always a 0 because it is not used by ATM Cell Processor.
CHAPTER 4 ATM CELL PROCESSOR Figure 4-33. Raw Cell Data Format WORD0 CELL HEADER WORD1 BYTE2 BYTE1 BYTE0 HEC BYTE46 BYTE45 BYTE44 BYTE43 0 BYTE47 : : : WORD12 WORD13 UINFO WORD14 WORD15 TIME STAMP 1 VC NUMBER CE 0 Cell Header Header of the cell except HEC. HEC HEC field pattern of the cell. BYTE0 – BYTE47 Payload data of the cell. UINFO User information. The pattern which user set in UINFO field in VC table.
CHAPTER 4 ATM CELL PROCESSOR Figure 4-34. Receive Indication Format UINFO PACKET SIZE 31 16 15 0 TIME STAMP 31 0 PACKET START ADDRESS 31 0 1 VC Number ERR CI C LP 0 31 30 UINFO ERR STATUS 16 15 14 13 12 11 7 POOL No.
CHAPTER 4 ATM CELL PROCESSOR (2) Max No. of bytes violation This error occurs if the last cell of a packet has not been received when the number of cells received has reached the user-specified "Max. No. of bytes" When the next cell is received, the RID bit is set and a receive indication is issued. The subsequent cells of the packet, including the last cell, are discarded.
CHAPTER 4 ATM CELL PROCESSOR 4.8.4 Mailbox ATM Cell Processor uses mailboxes as ring buffers in system memory. The structure of a mailbox and the defined addresses are as follows.
CHAPTER 5 ETHERNET CONTROLLER 5.1 Overview This section describes Ethernet Controller block. This Ethernet Controller block comprises of a 10/100 Mbps Ethernet MAC (Media Access Control), data transmit/receive FIFOs, DMA and internal bus interface. The µPD98502 implements 2-channel Ethernet Controller. 5.1.1 Features • IEEE802.3/802.3u/802.
CHAPTER 5 ETHERNET CONTROLLER Figure 5-1. Block Diagram of Ethernet Controller Ethernet Controller Block TPI+ TPI– MAC Core Rx FIFO FIFO Cont.
CHAPTER 5 ETHERNET CONTROLLER 5.2 Registers Registers of this block are categorized following four categories as shown in Table 5-1. VR4120A controls following registers. The µPD98502 has 2-channel Ethernet Controller, #1 controller’s base address is 1000_2000H, #2 controller’s base address is 1000_3000H. Table 5-1.
CHAPTER 5 ETHERNET CONTROLLER Offset Address 1000_m0A8H: 1000_m0C4H Register Name N/A R/W - Access - Description Reserved for future use 1000_m0C8H En_AFR R/W W Address Filtering Register 1000_m0CCH En_HT1 R/W W Hash Table Register 1 1000_m0D0H En_HT2 R/W W Hash Table Register 2 1000_m0D4H: 1000_m0D8H N/A - - Reserved for future use 1000_m0DCH En_CAR1 R/W W Carry Register 1 1000_m0E0H En_CAR2 R/W W Carry Register 2 1000_m0E4H: 1000_m012CH N/A - - Reserved for future u
CHAPTER 5 ETHERNET CONTROLLER Table 5-3.
CHAPTER 5 ETHERNET CONTROLLER Offset Address Register Name R/W Access Description 1000_m1C4H En_TPCT R/W W Transmit Packet Counter 1000_m1C8H En_TFCS R/W W Transmit CRC Error Packet Counter 1000_m1CCH En_TMCA R/W W Transmit Multicast Packet Counter 1000_m1D0H En_TBCA R/W W Transmit Broadcast Packet Counter 1000_m1D4H En_TUCA R/W W Transmit Unicast Packet Counter 1000_m1D8H En_TXPF R/W W Transmit PAUSE control Frame Counter 1000_m1DCH En_TDFR R/W W Transmit Single Defe
CHAPTER 5 ETHERNET CONTROLLER 5.2.1.3 DMA and FIFO management registers These registers control to transfer receive and transmit data by internal DMAC of this block. Table 5-4.
CHAPTER 5 ETHERNET CONTROLLER 5.2.1.4 Interrupt and configuration registers These register control interrupt occur and configuration for this block. Table 5-5. Interrupt and Configuration Registers Map Offset Address 1000_m234H Register Name En_CCR R/W R/W Access W Description Configuration Register 1000_m238H En_ISR RC W Interrupt Service Register 1000_m23CH En_MSR R/W W Mask Serves Register Remarks 1.
CHAPTER 5 ETHERNET CONTROLLER 5.2.2 En_MACC1 (MAC Configuration Register 1) Bits Field R/W Default Description 31:12 Reserved R/W 0 Reserved for future use. Write 0s. 11 TXFC R/W 0 Transmit flow control enable: Setting this bit to a ‘1’ enables to transmit the pause control frame. 10 RXFC R/W 0 Receive flow control enable: Setting this bit to a ‘1’ enables MAC Control Block to execute PAUSE operation for the pause time on the setting of the pause timer.
CHAPTER 5 ETHERNET CONTROLLER 5.2.3 En_MACC2 (MAC Configuration Register 2) Bits Field R/W Default Description 31:11 Reserved R/W 0 Reserved for future use. Write 0s. 10 MCRST R/W 0 MAC Control Block software reset: Setting this bit to a ‘1’ forces MAC Control Block to a software reset operation. In order to complete the software reset state, this bit needs to be cleared.
CHAPTER 5 ETHERNET CONTROLLER 5.2.6 En_CLRT (Collision Register) Bits Field R/W Default Description 31:14 Reserved R/W 0 Reserved for future use. Write 0s. 13:8 LCOL R/W 38H Late collision window: This field sets collision window size. The formula for the collision window size is: collision window size = (LCOL + 8) × 8 bits time 7:4 Reserved R/W 0 Reserved for future use. Write 0s.
CHAPTER 5 ETHERNET CONTROLLER 5.2.11 En_PTVR (Pause Timer Value Read Register) Bits Field R/W Default Description 31:16 Reserved R 0 Reserved for future use. 15:0 PTCT R 0 Pause timer counter: This field indicates the current pause timer value. 5.2.12 En_VLTP (VLAN Type Register) Bits Field R/W Default Description 31:16 Reserved R/W 0 Reserved for future use. Write 0s. 15:0 VLTP R/W 0 VLAN type: This field sets ETPID value.
CHAPTER 5 ETHERNET CONTROLLER 5.2.15 En_MADR (MII Address Register) Bits Field R/W Default Description 31:13 Reserved R/W 0 Reserved for future use. Write 0s. 12:8 FIAD R/W 0 MII PHY address: This field sets PHY address to be selected during the management access. 7:5 Reserved R/W 0 Reserved for future use. Write 0s. 4:0 RGAD R/W 0 MII register address: This field sets register address to be accessed during the management access. 5.2.
CHAPTER 5 ETHERNET CONTROLLER 5.2.19 En_AFR (Address Filtering Register) Bits Field R/W Default Description 31:4 Reserved R/W 0 Reserved for future use. Write 0s. 3 PRO R/W 0 Promiscuous mode: When this bit is set to a ‘1’, all receive packets are accepted. Please refer to 5.3.6. 2 PRM R/W 0 Accept Multicast: When this bit is set to a ‘1’, all multicast packets are accepted. Please refer to 5.3.6.
CHAPTER 5 ETHERNET CONTROLLER 5.2.22 En_CAR1 (Carry Register 1) The bits of this register indicate that an overflow event has occurred in statistics counters. Each bit corresponds to a counter, and the bit is set to a ‘1’ when the corresponding statistics counter overflow event occurs. Bits 31:16 Field Reserved R/W R/W Default 0 Description Reserved for future use. Write 0s.
CHAPTER 5 ETHERNET CONTROLLER 5.2.23 En_CAR2 (Carry Register 2) The bits of this register indicate that an overflow event has occurred in statistics counters. Each bit corresponds to a counter, and the bit is set to a ‘1’ when the corresponding statistics counter overflow event occurs. Bits Field R/W Default Description 31 C2XD R/W 0 Status vector overrun bit 30:23 Reserved R/W 0 Reserved for future use. Write 0s.
CHAPTER 5 ETHERNET CONTROLLER 5.2.24 En_CAM1 (Carry Register 1 Mask Register) This register masks the Interrupt that is generated from the setting of the bits in the En_CAR1 register. Each mask bit can be enabled independently. Bits 31:16 Field R/W Default 0 Description Reserved R/W Reserved for future use. Write 0s.
CHAPTER 5 ETHERNET CONTROLLER 5.2.25 En_CAM2 (Carry Register 2 Mask Register) This register masks the Interrupt that is generated from the setting of the bits in the En_CAR2 register. Each mask bit can be enabled independently. Bits Field R/W Default Description 31 M2XD R/W 0 Status vector overrun mask bit 30:23 Reserved R/W 0 Reserved for future use. Write 0s.
CHAPTER 5 ETHERNET CONTROLLER 5.2.27 En_TXFCR (Transmit FIFO Control Register) Bits Field R/W Default Description 31:16 TPTV R/W FFFFH Transmit Pause Timer Value: 15:10 TX_DRTH R/W 10H Transmit Drain Threshold Level: This threshold is enable to the transmit data to the MAC Control Block form the Tx-FIFO. If the transfer data is not completed by DMAC and the buffer empty pointer exceed this pointer, this MAC Control Block sends an Abort Packet. Please see the Figure 5-2.
CHAPTER 5 ETHERNET CONTROLLER 5.2.28 En_TXDPR (Transmit Descriptor Pointer) Bits Field R/W Default Description 31:2 XMTDP R/W 0 Transmit Descriptor Please see the Section 5.3.4 1:0 Reserved R/W 0 Reserved for future use. Write 0s. 5.2.29 En_RXCR (Receive Configuration Register) Bits 31 Field R/W Default RXE R/W 30:19 Reserved R/W 0 Reserved for future use. Write 0s.
CHAPTER 5 ETHERNET CONTROLLER 5.2.30 En_RXFCR (Receive FIFO Control Register) Bits Field R/W Default Description 31:26 UWM [7:2] R/W 30H Upper Water Mark: This pointer is used with Auto Flow Control Enable bit in En_TXCR. When the receiving data fill level exceeds this pointer, the transmit module generates a flow control frame automatically. 25:24 Reserved R/W 0 Reserved for future use. Write 0s. 23:18 LWN [7:2] R/W 10H Lower Water Mark: 17:8 Reserved R/W 0 Reserved for future use.
CHAPTER 5 ETHERNET CONTROLLER 5.2.32 En_RXPDR (Receive Pool Descriptor Pointer) Bits 31 Field Reserved R/W Default Description R/W 0 Reserved for future use. Write a 0. 30:28 AL[2:0] R/W 0 Alert Level 27:16 Reserved R/W 0 Reserved for future use. Write 0s. 15:0 RNOD [15:0] R/W 0 Remaining Number of Descriptor 5.2.33 En_CCR (Configuration Register) Bits Field R/W Default Description 31:1 Reserved R/W 0 Reserved for future use. Write 0s. 0 SRT R/W 0 Software Reset 5.2.
CHAPTER 5 ETHERNET CONTROLLER 5.2.35 En_MSR (Mask Serves Register) Each interrupt source is maskable. En_MSR register shows which interrupts are enable. Default value is all “0” which means all interrupt sources are disable. Bits 31:16 Field Reserved R/W Default Description R/W 0 Reserved for future use. Write 0s.
CHAPTER 5 ETHERNET CONTROLLER 5.3 Operation 5.3.1 Initialization After a power on reset or a software reset, VR4120A has to set the following registers: i) Interrupt Mask Registers ii) Configuration Registers iii) MII Management Registers iv) Pool/Buffer Descriptor Registers 5.3.2 Buffer structure for Ethernet Controller block The data buffer structure for Ethernet Controller is shown in Figure 5-4. Figure 5-4.
CHAPTER 5 ETHERNET CONTROLLER 5.3.3 Buffer descriptor format The Transmit Descriptor format is shown in Figure 5-5 and the description is shown in Table 5-6. Figure 5-5. Transmit Descriptor Format 31 16 Word 0 15 0 Attribute Word 1 Size Buffer Address Pointer Table 5-6.
CHAPTER 5 ETHERNET CONTROLLER Table 5-7. Attribute for Receive Descriptor Attribute & Size Bit Name Status 31 L 30 D/L Data Buffer / Link Pointer 29 OWN Owner bit 1:Ethernet Controller 0: VR4120A Ethernet Controller sets this bit after it began to transfer data into each descriptor.
CHAPTER 5 ETHERNET CONTROLLER Short frames are automatically padded by the transmit logic if PADEN bit in En_MACC1 register is set. If the transmit frame length exceeds 1518 bytes, Ethernet Controller will assert an interrupt. However, the entire frame will be transmitted (no truncation). If the current descriptor does not contain the end of frame, Ethernet Controller reads next buffer descriptor, and then reads the continuous data from the data buffer. After Ethernet Controller sent out the whole packet,.
CHAPTER 5 ETHERNET CONTROLLER Figure 5-7.
CHAPTER 5 ETHERNET CONTROLLER Operation flow for transmit packet i) Prepares transmit data in data buffer ii) Initializes registers (XMDP, TXE) iii) Reads buffer descriptor for transmission from SDRAM iv) Reads transmit data from data buffer by using master DMA burst operation v) Waits for exceeding of transmit drain threshold (TXDRTH) Senses carrier Transmits data (Preamble.
CHAPTER 5 ETHERNET CONTROLLER When the receive frame is complete, Ethernet Controller sets the L-bit in the Receive Descriptor, writes the frame status bits into the Receive Descriptor, and sets the OWN-bit. Ethernet Controller generates a maskable interrupt, indicating that a frame has been received and is in memory. Ethernet Controller then waits for a new frame. Receive procedure is as follows: (Figure 5-8) Figure 5-8.
CHAPTER 5 ETHERNET CONTROLLER Operation flow for receive packet i) Prepares the receive buffer descriptors ii) Initializes registers (RXVDP, RXE) iii) Reads the receive buffer descriptor iv) Waits for exceeding of receive drain threshold (RXDRTH) v) Writes receive data to data buffer by using master DMA burst operation vi) Increments the Receive Descriptor Pointer if the current data buffer is full vii) Check out the RNOD If the remaining number of descriptors is less than four times of the alert level,
CHAPTER 5 ETHERNET CONTROLLER (3) Broadcast address filtering All of received packets with broadcast destination address are received when ABC bit in En_AFR register is set to a ‘1’. (4) Promiscuous mode Setting PRO bit in En_AFR register to a ‘1’ caused all of received packets to be received. Filtering procedure is as follows: At first, SRXEN bit in En_MACC1 register is set to a ‘1’. In this case, the received data interface is disabled. Then, the station address is set in En_LSA1 and En_LSA2 registers.
CHAPTER 6 USB CONTROLLER 6.1 Overview The USB Controller handles the data communication through USB. The following lists the features of USB Controller. 6.1.1 Features • Conforms to Universal Serial Bus Specification Rev 1.
CHAPTER 6 USB CONTROLLER 6.1.2 Internal block diagram USB Controller internal block diagram is as shown below. Figure 6-1. USB Controller Internal Configuration IB U S U S B C O N TR O LLE R MCONT M aster I/F Tx FIFO D+ USB B U S I/F DMAC I/O B uf S IE EPC R x FIFO DS lav e I/F s lave decoder USB Controller's configuration features the following blocks. SIE (Serial Interface Engine): Performs Serial/Parallel conversion, NRZI encoding/decoding, CRC calculation, etc.
CHAPTER 6 USB CONTROLLER 6.2 Registers This section explains the mapping of those registers that can be accessed from IBUS. USB base address is 1000_1000H 6.2.
CHAPTER 6 USB CONTROLLER 2. All internal registers are 32-bit word-aligned registers. 3. The burst access to the internal register is prohibited. If such burst access has been occurred, IRERR bit in NSR is set and NMI will assert to CPU. 4. Read access to the reserved area will set the CBERR bit in the NSR register and the dummy read response data with the data-error bit set on SysCMD [0] is returned. 5.
CHAPTER 6 USB CONTROLLER 6.2.2 U_GMR (USB General Mode Register) This register is used for setting the operation of USB Controller. The low-order sixteen bits except for RR bit can be written only when the device is being initialized. If the values of these bits are changed while transmission or reception is being performed, the operation of USB Controller may become unpredictable. Bits Field R/W Default Description 31:24 Reserved R/W 0 Reserved for future use. Writes ‘0’s.
CHAPTER 6 USB CONTROLLER 6.2.4 U_GSR1 (USB General Status Register 1) This register indicates the current status of USB Controller. Bits Field R/W Default Description 31 GSR2 RC 0 If some bits of General Status Register 2 are set to ‘1’s and the corresponding bits in Interrupt Mask Register 2 are set to ‘1’s, this GSR2 bit will be set to a ‘1’. 30:24 Reserved R 0 Reserved for future use 23 TMF RC 0 Tx MailBox Full: Bit that indicates transmit MailBox area is full.
CHAPTER 6 USB CONTROLLER Bits Field R/W Default Description 8 EP1FU RC 0 EP1 FIFO Error: Bit that indicates that an underrun has occurred for the FIFO of EndPoint1 (Isochronous IN). When the FIFO empties while EndPoint1 is performing a transaction, this bit is set to a ‘1’. This bit is reset to a ‘0’ when the VR4120A reads this register. 7 EP6RF RC 0 EP6 Rx Finished: Bit that indicates that EndPoint6 (Interrupt OUT) has completed the receiving of a data segment and issued the Rx Indication.
CHAPTER 6 USB CONTROLLER 6.2.5 U_IMR1 (USB Interrupt Mask Register 1) This register is used to mask interrupts. When a bit in this register is set to a ‘1’ and the corresponding bit in the USB General Status Register 1 (Address: 10H) is set to a ‘1’, an interrupt is issued. Bits Field R/W Default GSR2 R/W 30:24 Reserved R/W 0 Reserved for future use. Writes ‘0’s. 23 TMF R/W 0 Tx MailBox Full: 1 = unmask. 0 = mask. 22 RMF R/W 0 Rx MailBox Full: 1 = unmask. 0 = mask.
CHAPTER 6 USB CONTROLLER Bits Field R/W Default Description 4 EP3TF R/W 0 EP3 Tx Finished: 1 = unmask. 0 = mask. 3 EP2RF R/W 0 EP2 Rx Finished: 1 = unmask. 0 = mask. 2 EP1TF R/W 0 EP1 Tx Finished: 1 = unmask. 0 = mask. 1 EP0RF R/W 0 EP0 Rx Finished: 1 = unmask. 0 = mask. 0 EP0TF R/W 0 EP0 Tx Finished: 1 = unmask. 0 = mask.
CHAPTER 6 USB CONTROLLER 6.2.6 U_GSR2 (USB General Status Register 2) This register indicates the current status of USB Controller. Reading this register clears all bits in this register. Bits Field R/W Default Description 31:21 Reserved R 0 Reserved for future use 21 FW RC 0 Frame Number Written: This bit is set to a ‘1’ when Frame Number is written to USB Frame Number/Version Register (04H).
CHAPTER 6 USB CONTROLLER 6.2.7 U_IMR2 (USB Interrupt Mask Register 2) This register is used to mask interrupts. When a bit in this register is set to a ‘1’ and the corresponding bit in the USB General Status Register 2 (Address: 18H) is set to a ‘1’, GSR2 bit in the U_GSR1 will be set to a ‘1’. Bits Field R/W Default Description 31:22 Reserved R/W 0 Reserved for future use. Writes ‘0’s. 21 FW R/W 0 Frame Number Written: 1 = unmask. 0 = mask.
CHAPTER 6 USB CONTROLLER 6.2.8 U_EP0CR (USB EP0 Control Register) This register is used for setting the operation of EndPoint0. If the value in the MAXP field is rewritten during transmitting or receiving operation, the operation of USB Controller may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed.
CHAPTER 6 USB CONTROLLER 6.2.9 U_EP1CR (USB EP1 Control Register) This register is used for setting the operation of EndPoint1. If the value in the MAXP field is rewritten during transmitting operation, the operation of USB Controller may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed. Bits Field R/W R/W Default 0 Description 31 EP1EN EndPoint Enable: When the VR4120A sets this bit to a ‘1’, EndPoint1 is enabled to transmit data.
CHAPTER 6 USB CONTROLLER 6.2.11 U_EP3CR (USB EP3 Control Register) This register is used for setting the operation of EndPoint3. If the value in the MAXP field is rewritten during transmitting operation, the operation of USB Controller may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed. Bits Field R/W 0 Description EP3EN 30:20 Reserved R/W 0 Reserved for future use. Writes ‘0’s. 19 TM3 R/W 0 Tx Mode: Bit for setting the transmit mode.
CHAPTER 6 USB CONTROLLER 6.2.12 U_EP4CR (USB EP4 Control Register) This register is used for setting the operation of EndPoint4. If the value in the MAXP field is rewritten during receiving operation, the operation of USB Controller may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed. Bits Field R/W Default Description 31 EP4EN R/W 0 EndPoint Enable: When the VR4120A sets this bit to a ‘1’, EndPoint4 is enabled to receive data.
CHAPTER 6 USB CONTROLLER 6.2.13 U_EP5CR (USB EP5 Control Register) This register is used for setting the operation of EndPoint5. If the value in the MAXP field is rewritten during transmitting operation, the operation of USB Controller may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed. Bits Field R/W R/W Default 0 Description 31 EP5EN EndPoint Enable: When the VR4120A sets this bit to a ‘1’, EndPoint5 is enabled to transmit data.
CHAPTER 6 USB CONTROLLER 6.2.15 U_CMR (USB Command Register) This register is used for issuing Tx request or adding Rx Buffer Directories to Pool. The VR4120A writes commands into this register. Whenever B bit (Bit 31) is set, the value will not change even if the VR4120A writes commands into this register. Bits Field R/W Default Description 31 B R/W 0 Busy: Bit that indicates whether the interpretation of an issued command has terminated.
CHAPTER 6 USB CONTROLLER 6.2.17 U_TEPSR (USB Tx EndPoint Status Register) This register is used for indicate the status of the EndPoint being used for data transmitting. Bits Field R/W Default Description 31:26 Reserved R 0 Reserved for future use 25:24 EP5TS R 0 EP5 Tx Status: Register that indicates the transmit status of EndPoint5 This register is not cleared, even if read.
CHAPTER 6 USB CONTROLLER 6.2.19 U_RP0AR (USB Rx Pool0 Address Register) This register indicates the start address of Buffer Directory which is currently used. The way to set up Rx Pool is described at Section 6.6.3 Receive pool settings. Bits 31:0 Field Address R/W R Default 0 Description Buffer Directory Address: Register that indicates the start address of the first Buffer Directory in Pool0. The VR4120A can only read this register.
CHAPTER 6 USB CONTROLLER 6.2.22 U_RP2IR (USB Rx Pool2 Information Register) This register indicates the information of Receive Pool2. The VR4120A writes to this register only when the device is being initialized. Bits Field R/W Default Description 31 Reserved R/W 0 Reserved for future use. Writes ‘0’s. 30:28 AL R/W 000 Alert Level: Sets the warning level for Pool0.
CHAPTER 6 USB CONTROLLER 6.2.27 U_TMWA (USB Tx MailBox Write Address Register) Bits 31:0 Field Address R/W R Default 0 Description Register that indicates the address in the transmit MailBox area to which USB Controller will write next time. 6.2.28 U_RMSA (USB Rx MailBox Start Address Register) Bits 31:0 Field Address R/W R/W Default 0 Description Register that indicates the start address of the receive MailBox area. The VR4120A must set a value in this field only at initialization. 6.2.
CHAPTER 6 USB CONTROLLER 6.3 USB Attachment Sequence This section describes the sequence that is followed when the µPD98502 is attached to a USB hub. Figure 6-2.
CHAPTER 6 USB CONTROLLER 6.4 Initialization After USB Controller has been reset, the VR4120A must set several USB Controller registers. The initialization sequence is listed below. (1) A desired mode is set into the USB General Mode Register.
CHAPTER 6 USB CONTROLLER 6.4.1 Receive pool settings For details of the receive pool settings, see Section 6.6.3 Receive pool settings. 6.4.2 Transmit/receive MailBox settings After USB Controller transmits a data segment, it indicates the status by writing a transmit indication in ‘MailBox’ in system memory. During the initialization, the VR4120A must set the MailBoxes. USB Controller uses the MailBoxes as a ring buffer. This buffer is set using four registers for each of transmitting and receiving.
CHAPTER 6 USB CONTROLLER Figure 6-3. Mailbox Configuration 31 0 U_TMSA(U_RMSA) U_TMRA(U_RMRA) U_TMWA(U_RMWA) U_TMBA(U_RMBA) When USB Controller writes an indication, the write pointer (U_TMWA or U_RMWA) is incremented. Every time that USB Controller writes an indication, it also sets the transmit/receive finish bit of the corresponding EndPoint and, issues an interrupt if it is not masked.
CHAPTER 6 USB CONTROLLER 6.5 Data Transmit Function This section explains USB Controller's data transmit function. 6.5.1 Overview of transmit processing USB Controller divides the data segments in system memory, into USB packets, then transmits them to the Host PC. The VR4120A sets the size of USB packet in the MAXP field of the EP0 Control Register, the EP1-2 Control Register, the EP3-4 Control Register, and the EP5-6 Control Register (in the example shown below, a value of 64 bytes has been set).
CHAPTER 6 USB CONTROLLER Figure 6-5. Tx Buffer Configuration Tx Packet Buffer Directory Buffer descriptor Buffer descriptor Data Buffer Data Buffer Buffer descriptor Link pointer Buffer descriptor Buffer desc.(L=1) Data Buffer Data Buffer Data Buffer A transmit packet is configured by breaking up multiple data buffers in system memory. These data buffers are bundled together in the buffer directory.
CHAPTER 6 USB CONTROLLER Figure 6-6. Configuration of Transmit Buffer Directory -Tx Buffer D irectory 31 0 B uffer D escriptor 0 B uffer D escriptor 1 B uffer D escriptor 2 B uffer D escriptor 3 B uffer D escriptor 4 | B uffer D escriptor N Link P ointer -Tx Buffer D escriptor 31 30 29 L 1 16 15 R eserved 0 S ize B uffer A ddress -Tx Link Pointer 31 30 29 0 0 0 R eserved D irectory Address Tx Buffer Directory: This is the Tx buffer directory.
CHAPTER 6 USB CONTROLLER 6.5.3 Data transmit modes USB Controller supports two transmit modes. These modes differ only in whether a zero-length USB packet is transmitted after the last USB packet of a data segment. In all other aspects, they are identical. The transmit mode is switched using the TM bit (Bit 19) of the USB EP1 EndPoint Control Register (Address: 1000_1024H) and USB EP3 EndPoint Control Register (Address: 1000_102CH). Cautions 1.
CHAPTER 6 USB CONTROLLER 6.5.4 VR4120A processing at data transmitting This section explains the processing performed by the VR4120A when transmitting data. Figure 6-7. VR4120A Processing at Data Transmitting (1) Prepare Tx data in the memory (2) Reads U SB Command R egister (3) Busy bit = "1" ? Yes No Issue processing of T x comm and (4) Reads U SB Tx EndP oint Status Register (5) EndPoint is B usy ? Yes No (6) Issues transmit comm and US B Controller transmits the data to USB .
CHAPTER 6 USB CONTROLLER (1) First, the VR4120A prepares the data to be transmitted in system memory. (2) The VR4120A reads the USB Command Register. (3) The VR4120A checks whether the Busy bit of the USB Command Register is set. If the Busy bit is set, it indicates that USB Controller is still executing the previous command. Thus the VR4120A can not issue a new command. (4) (5) The VR4120A reads the USB Tx EndPoint Status Register.
CHAPTER 6 USB CONTROLLER Figure 6-9.
CHAPTER 6 USB CONTROLLER 6.5.5 USB controller processing at data transmitting This section presents all of the processing performed by USB Controller at data transmitting. Figure 6-10. USB Controller Transmit Operation Flow Chart (1) T x co m m and is set (2) S et US B Com m and R egister B usy bit to "1".
CHAPTER 6 USB CONTROLLER Numbers (1) to (15) do not indicate the order in which USB Controller must perform processing. Instead, these numbers correspond to those in the following explanation. (1) USB Controller starts transmit processing upon receiving a transmit command from the VR4120A. (2) When the command is written, USB Controller sets the Busy bit in USB Command Register to a ‘1’.
CHAPTER 6 USB CONTROLLER 6.5.6 Tx indication For every data segment to be transmitted, USB Controller writes a Tx indication into the Tx MailBox. After writing a Tx indication, USB Controller sets the transmit completion bit of USB General Status Register1 to 1 and, provided it is not masked, issues an interrupt to the VR4120A. The format of the transmit indication is as shown below. Figure 6-11.
CHAPTER 6 USB CONTROLLER 6.6 Data Receive Function This section explains USB Controller's data receive function. 6.6.1 Overview of receive processing USB Controller receives USB packets from the USB, stores them into system memory, and then assembles a single data segment. The VR4120A sets the size of a single USB packet in the MAXP field of the EP0 Control Register, EP1-2 Control Register, EP3-4 Control Register, and EP5-6 Control Register.
CHAPTER 6 USB CONTROLLER 6.6.2 Rx Buffer configuration Data received from the USB is stored into a receive pool in system memory. USB Controller uses three receive pools. The configuration of the receive pools is shown below. Figure 6-13.
CHAPTER 6 USB CONTROLLER Figure 6-14. Receive Descriptor Configuration -R x Buffer D irectory 31 0 B uffer D esciptor 0 B uffer D esciptor 1 B uffer D esciptor 2 B uffer D esciptor 3 B uffer D esciptor 4 | B uffer D esciptor N Link P ointer -R x Buffer D escriptor 31 30 29 L 1 16 15 R eserved 0 S ize B uffer A ddress -R x Link Pointer 31 30 29 0 16 15 0 0 R eserved B uffer D irectory A ddress Rx Buffer Directory: A Rx Buffer Directory.
CHAPTER 6 USB CONTROLLER 6.6.3 Receive pool settings USB Controller uses three receive pools. Pool0 For EndPoint0 (Control) and EndPoint6 (Interrupt) Pool1 For EndPoint2 (Isochronous) Pool2 For EndPoint4 (Bulk) The data in each of these three pools is written into the corresponding registers.
CHAPTER 6 USB CONTROLLER (a) If any unused Buffer Directories remain in the pool (when the RNOD field in the Pool Information Register is set to grater than 0), USB Controller adds the number in the NOD field of the command to the RNOD field of the Pool Information Register. (b) When the pool is empty (when the RNOD field in the Pool Information Register is 0), USB Controller loads the value set in the NOD field of the command into the RNOD field of the Pool Information Register.
CHAPTER 6 USB CONTROLLER (1) Reception in EndPoint0, EndPoint6 Same processing is executed without relations in receive mode in EndPoint0, EndPoint6 every time. Figure 6-16. Data Receiving in EndPoint0, EndPoint6 B uffer D irectory R x In dicatio n D0 µ P D 98502 R x In dicatio n D0 D3 D2 D1 D0 R x In dicatio n D1 R x In dicatio n D2 D3 When USB Controller receives one USB packet, stores it in Data Buffer and write Rx indication to the Mailbox.
CHAPTER 6 USB CONTROLLER (3) EndPoint2, EndPoint4, assemble mode The processing in EndPoint2, EndPoint4 receive Assemble mode is explained below. Figure 6-18. EndPoint2, EndPoint4 Receive Assemble Mode B uffer D irectory D0 µ P D 98502 D0 D3 D2 D1 D1 D0 R x In dicatio n D1 D2 D2 D3 In this mode USB Controller issues Rx indication after receiving one data segment.
CHAPTER 6 USB CONTROLLER 6.6.5 VR4120A receive processing This section explains the processing that the VR4120A must perform when data is being received. Figure 6-20. VR4120A Receive Processing (1) S ets P ool initialization S ets R x P ool (2) (If necessary) A dds B uffer Directory to P ool Receives the data from US B .
CHAPTER 6 USB CONTROLLER 6.6.6 USB controller receive processing This section presents all of the processing performed by USB Controller at data receiving. 6.6.6.1 Normal mode The following figure illustrates the receive operations performed by USB Controller in Normal Mode. Figure 6-21.
CHAPTER 6 USB CONTROLLER Numbers (1) to (9) do not indicate the order in which USB Controller must perform processing. Instead, these numbers correspond to those in the following explanation. (1) (2) USB Controller is in the status where it waits to receive data (USB Packets) from the USB. USB Controller receives data (USB Packets) from the USB. As it is receiving the data, USB Controller performs NRZI decoding, CRC check, and Bit Stuffing Error check.
CHAPTER 6 USB CONTROLLER 6.6.6.2 Assemble mode The following figure illustrates the receive operations performed by USB Controller in Assemble Mode. Figure 6-22.
CHAPTER 6 USB CONTROLLER Numbers (1) to (11) do not indicate the order in which USB Controller must perform processing. Instead, these numbers correspond to those in the following explanation. (1) (2) USB Controller is in the status where it waits to receive data (USB Packets) from the USB. USB Controller receives data (USB Packets) from the USB. As it is receiving the data, USB Controller performs NRZI decoding, CRC check, and Bit Stuffing Error check.
CHAPTER 6 USB CONTROLLER 6.6.6.3 Separate mode The following figure illustrates the receive operations performed by USB Controller in Separate Mode. Figure 6-23.
CHAPTER 6 USB CONTROLLER Numbers (1) to (12) do not indicate the order in which USB Controller must perform processing. Instead, these numbers correspond to those in the following explanation. (1) (2) USB Controller is in the status where it waits to receive data (USB Packets) from the USB. USB Controller receives data (USB Packets) from the USB. As it is receiving the data, USB Controller performs NRZI decoding, CRC check, and Bit Stuffing Error check.
CHAPTER 6 USB CONTROLLER 6.6.7 Detection of errors on USB USB Controller has some functions which detect some errors on the USB. Errors shown in figure below are related to Isochronous EndPoint and SOF packet. Figure 6-24. USB Timing Errors SOF Correct Loss of Data ISO. SOF ISO. Error Error Loss of SOF Extra Data SOF ISO. SOF ISO. Error Extra SOF SOF Error ISO. (1) If “Loss of Data” error has occurred, EP2ND bit (Bit 5) in USB General Status Register 2 will be set.
CHAPTER 6 USB CONTROLLER data to USB and will set EP1ND bit (Bit 2) in USB General Status Register 2. • Extra Token on EndPoint1: If IN TOKEN packet for EndPoint2 comes which between two SOFs, USB Controller will set EP1ET bit (Bit 3) in USB General Status Register 2. In this case, USB Controller will transmit data only once. • No Token on EndPoint1: If IN TOKEN packet for EndPoint2 does not come between two SOFs, USB Controller will set EP1NT bit (Bit 4) in USB General Status Register 2.
CHAPTER 6 USB CONTROLLER 6.6.8 Rx data corruption on Isochronous EndPoint On Isochronous Rx EndPoint (EP2), one data packet comes per one frame. If any Isochronous data packet doesn’t come between two SOF packet, it is assumed that Isochronous data is corrupted. In the case of corruption, action of USB Controller varies according to Rx Mode. (a) Rx normal mode USB Controller sets EP2ND (EndPoint2 No Data) bit (Bit 6) in USB General Status Register 2. USB Controller doesn’t write any Rx indications.
CHAPTER 6 USB CONTROLLER Figure 6-25. Example of Buffers Including Corrupted Data V alid D ata B uffer D irectory Buffer descriptor V alid Buffer descriptor C orrupted D ata Buffer descriptor M ax Pack et Size V alid Link pointer V alid D ata C orrupted D ata M ax Pack et Size C orrupted D ata Buffer descriptor V alid D ata Buffer descriptor Buffer desc.(L=1) V alid D ata Link pointer V alid D ata 6.6.
CHAPTER 6 USB CONTROLLER (b) Rx assemble mode USB Controller sets EP2FO (EndPoint2 No Data) bit (Bit 9) in USB General Status Register 2. USB Controller writes dummy data to Data Buffer (In fact, USB Controller only increment pointer which addresses Data Buffer by Max Packet Size. No DMA transfer occurs) so that the sum of received data and dummy data becomes equal to Max Packet Size.
CHAPTER 6 USB CONTROLLER When set to a ‘1’, indicates that a buffer overrun occurred. This bit is set only when receiving the data from the EndPoint1. Bit21: Reserved. Bit20: When set to a ‘0’, indicates that a CRC error has not occurred. When set to a ‘1’, indicates that a CRC error has occurred. When this bit is set to 1 when receiving data from the Isochronous EndPoint (EndPoint2), it indicates that the data stored in system memory includes a CRC error.
CHAPTER 6 USB CONTROLLER 6.7 Power Management USB Controller has a built in feature that allows it to use interrupts to inform the VR4120A of its having received Suspend or Resume signaling from a Host PC. When the VR4120A receives a Suspend or a Resume, it must perform the appropriate processing.
CHAPTER 6 USB CONTROLLER The VR4120A is not permitted to write to other than USB Controller's USB General Mode Register and USB Interrupt Mask Register 2 while USB Controller is in the Suspend status. Otherwise, after USB Controller enters the Resume status, its operation will be unpredictable. 6.7.2 Resume The Resume sequence is shown below. Figure 6-28. Resume Sequence H ost P C V R 4120A USB C ontroller (1) S tarts R esum e S ignaling (4) D etects R esum e S ignaling, transits to R esum e state.
CHAPTER 6 USB CONTROLLER 6.7.3 Remote wake up The Remote Wake Up sequence is shown below. Figure 6-29. Remote Wake Up Sequence USB C ontroller V R 4120A H ost P C (1) R eceives the data from other block (2) Sets R R bit (Bit0) in U SB G eneral M ode R egister (4) Starts K-state signaling (3) Sets sending D ata to U SB 10 m s (5) Stops K-state signaling (6) D etects K-state signaling. Starts to broadcast R ESU M E signaling 20 m s (7) Stops R ESUM E signaling.
CHAPTER 6 USB CONTROLLER 6.8 Receiving SOF Packet USB Controller can receive SOF Packets, and check if Frame Number is incremented correctly. In addition, USB Controller can detect the timing skew of SOF Packet. 6.8.1 Receiving SOF Packet and updating the Frame Number After USB Controller receives a SOF Packet, FN field in USB Frame Number/Version Register (Address: 1000_1004H) is updated. After FN field is updated, FW bit (Bit 21) in USB General Status Register 2 (Address: 1000_1018H) is set to a ‘1’. 6.
CHAPTER 6 USB CONTROLLER 6.9 Loopback Mode USB Controller features a built-in loopback function for test purposes. To enable the loopback function, set the LE bit (Bit 1) of the USB General Mode Register to 1. Once the loopback function has been activated, USB Controller gets the data from system memory and places it into the Tx FIFO. The data is returned by the EndPoint Controller. The returned data is written into the Rx FIFO, after it is returned to system memory.
CHAPTER 6 USB CONTROLLER 6.10 Example of Connection USB Controller is connected to the µPD98502 internal USB I/O buffer as shown in the following Figure 6-32. Figure 6-32. Example of Connection +3.3 V D+ B uffer 1.5 k Ω U S B C ontroller Y1 IS E CNA CNB D+ C onnect to HUB OSE A OEN D51 k Ω DB uffer GND µ P D 98502 When designing a PCB, it is necessary to connect a 1.5 kΩ pull-up resistor between the D+ pin and the 3.3 V power supply to indicate the presence of a full-speed device.
CHAPTER 7 PCI CONTROLLER 7.1 Overview The PCI Controller supports both NIC mode and Host mode. With the NIC mode, the PCI Controller does not issue configuration cycle and the arbitration function is not enabled. With the Host mode, the PCI Controller can issue configuration cycle and the arbitration function is enabled. Futures of the PCI Controller are as follows. • 32-bit PCI Interface • 33-MHz PCI frequency capable • Compliant to PCI Local Bus Specification Rev.2.
CHAPTER 7 PCI CONTROLLER 7.2 Bus Bridge Functions 7.2.1 Internal bus to PCI transaction 7.2.1.1 Window size The PCI Controller can have a 2-MB length access window in internal memory space. The VR4120A can access external PCI devices through the access window. The access window can be positioned in the memory range from 1020_0000H to 103F_FFFFH. The base address of the PCI address space is defined by setting of P_PLBA Register. 7.2.1.2 PCI master The PCI Controller can issue memory commands only.
CHAPTER 7 PCI CONTROLLER 7.2.1.3 Write issue from internal bus to PCI (1) Posted write transaction If IPWRD bit in P_BCNT register is ‘0’, the PCI Controller uses “Posted Write Transaction” rule for write transactions from the internal bus-side to PCI-side. The rule is as follows; <1> An internal bus block Note connecting to the internal bus issues the write transaction to PCI target device. <2> The PCI Controller accepts this access and puts the data to be written into the internal FIFO.
CHAPTER 7 PCI CONTROLLER (2) Non posted write transaction If IPWRD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Posted Write Transaction” rule for write transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word. The rule is as follows; <1> An internal bus block Note connecting to the internal bus issues the write transaction to an external PCI target device. The PCI Controller latches the first word of the burst data.
CHAPTER 7 PCI CONTROLLER 7.2.1.4 Read issue from internal bus to PCI (1) Delayed read transaction When IDRTD bit in P_BCNT register is ‘0’, the PCI Controller uses “Delayed Read Transaction” rule for read transactions from internal bus-side to PCI-side. The rule is as follows; <1> An internal bus block connecting to the internal bus issues the read transaction to an external PCI target device. <2> The PCI Controller responds to this access and issues “retry” to internal bus block.
CHAPTER 7 PCI CONTROLLER (2) Non delayed read transaction When IDRTD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Delayed Read Transaction” rule for read transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word. The rule is as follows; <1> An internal bus block connecting to the internal bus issues the read transaction to an external PCI target device.
CHAPTER 7 PCI CONTROLLER 7.2.2 PCI to internal bus transaction 7.2.2.1 Window size The PCI Controller supports a 2-MB address space as the access window from PCI-side to Internal bus-side in PCI memory space. The base address for the window is written to Window Memory Base Address register in configuration space by an external PCI-Host device in NIC mode. In Host-mode, the VR4120A has to write the base address to this register.
CHAPTER 7 PCI CONTROLLER 7.2.2.3 Write issue from PCI to Internal bus (1) Posted write transaction If PPWRD bit in P_BCNT register is ‘0’, the PCI Controller uses “Posted Write Transaction” rule for write transactions from Internal bus-side to PCI-side. The rule is as follows; <1> A PCI master device issues the write transaction to an internal bus target block. <2> The PCI Controller accepts this access and stores the write data into the internal FIFO.
CHAPTER 7 PCI CONTROLLER (2) Non posted write transaction When PPWRD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Posted Write Transaction” rule for write transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word. The rule is as follows; <1> PCI master device issues the write transaction to an internal bus target block. <2> The PCI Controller responds to this access by asserting DEVSEL_B and latches the first word of the burst data.
CHAPTER 7 PCI CONTROLLER 7.2.2.4 Read issue from PCI to internal bus (1) Delayed read transaction When PDRTD bit in P_BCNT register is ‘0’, the PCI Controller uses “Delayed Read Transaction” rule for read transactions from Internal bus-side to PCI-side. The rule is as follows; <1> A PCI master device issues the read transaction to an internal bus target block. <2> The PCI Controller responds to this access and issues “retry” to PCI master device.
CHAPTER 7 PCI CONTROLLER (2) Non delayed read transaction When PDRTD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Delayed Read Transaction” rule for read transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word. The rule is as follows; <1> PCI master device issues the read transaction to internal bus target block.
CHAPTER 7 PCI CONTROLLER 7.2.3 Abnormal Termination 7.2.3.1 On PCI bus (1) Detecting parity error When the access to the PCI Controller is issued on PCI bus and the PCI Controller detects the address parity error as a target, the PCI Controller issues a target abort to terminate the access.
CHAPTER 7 PCI CONTROLLER In the case that the value except for ‘0’ is set to P_RTMR register, the PCI Controller abandons the access when the number of target retry which the PCI Controller is received for the same access goes over the value in P_RTMR register. This function is called as “Retry-Timer”. Setting ‘0’ to P_RTMR register disables this function. 7.2.3.
CHAPTER 7 PCI CONTROLLER 7.3 PCI Power Management Interface The PCI Controller has the mechanism for power management compliant to PCI Power Management Interface (PPMI) Rev.1.1 as a PCI-device. The PCI Controller does not control the power state of the chip, but issues signals of power transition from the VR4120A to an external PCI-Host device, or from the PCI-Host device to the VR4120A. The PCI-Host device and the VR4120A are responsible for the management of the power state.
CHAPTER 7 PCI CONTROLLER 7.3.4 Power state transition 7.3.4.1 Transition by issue from PCI-Host An example of the transition sequence is as follows: 1. When PCI-Host wants to change the power state of the chip, it writes the state code to Power State field in PMCSR register. 2. The PCI Controller resets PMRDY bit in P_PPCR register to a ‘0’. 3. The PCI Controller sets PMRQX bit (PMRQ0, PMRQ1, and PMRQ3) in P_PPCR register, and issues an 4.
CHAPTER 7 PCI CONTROLLER 7.3.4.2 Transition by power management event The sequence is as follows: 1. When Power Management Event occurs, the VR4120A writes a ‘1’ to PMERQ bit in P_PPCR register. 2. The PCI Controller asserts PME_B if PME_En bit in PMCSR register is enabled. 3. An external PCI-Host device writes a ‘1’ to PME_Status bit in PMCSR register or writes a ‘0’ to PME_En bit in 4. The PCI Controller deasserts PME_B. PMCSR register in order to clear PME_B.
CHAPTER 7 PCI CONTROLLER 7.4 Functions in Host-mode The functions described in this section are available when PMODE is set to low. 7.4.1 Generating configuration cycle 7.4.1.
CHAPTER 7 PCI CONTROLLER 7.4.1.3 PCI Configuration Data Register (P_PCDR) When bit31 in the PCAR register is set to ‘1’, access to PCDR register generates Configuration Cycle. Read access to P_PCDR register generates Configuration Read Cycle on PCI bus. Write access to P_PCDR register, also, generates Configuration Write Cycle on PCI bus. 7.4.1.4 IDSEL signals As mentioned above, in address phase of Type0 transaction, the PCI Controller set one bit in AD [31:16] to ‘1’ and all other bit to ‘0’.
CHAPTER 7 PCI CONTROLLER Figure 7-14. An Example How to Connect AD [31:16] Signal Line to IDSEL Port A D [x] ID S E L A D [31 :0 ] P C I de vice Figure 7-15. Address Stepping for IDSEL C lock FR A M E # AD A ddress D a ta ID S E L IR D Y # TRDY# D E V S E L# 7.4.2 PCI bus arbiter The PCI Controller has an arbiter that supports 4 external PCI master devices. This arbiter is enabled only when in Host mode and PARBEN is set to high.
CHAPTER 7 PCI CONTROLLER Figure 7-16. Arbitration in Alternating Mode G N T #0 PCI C ontrolle r A lterna ting G N T #1 R ota tin g G N T #3 G N T #2 7.4.2.2 Rotating mode Priority rotates among all PCI master devices including the PCI Controller in this mode. When all REQ_B input signals to this arbiter go up to high, which means no device issues the acquisition of PCI bus, this arbiter gives the right of use of PCI bus to the device that had acquired PCI bus last as arbitration parking.
CHAPTER 7 PCI CONTROLLER 7.5 Registers 7.5.
CHAPTER 7 PCI CONTROLLER 7.5.2 P_PLBA (PCI Lower Base Address Register) When the PCI Controller issues 32-bit PCI address, this register contains PCI base address. When the access from Internal bus-side to PCI-side comes, the PCI Controller replaces the upper 10 bits of the address on internal bus with the upper 10 bits of this register, and issues as the address on PCI bus.
CHAPTER 7 PCI CONTROLLER 7.5.5 P_PCAR (PCI Configuration Address Register) PCAR register is used to set the information for Configuration Cycle. How to generate Configuration Cycle is described in 7.4.1 Generating configuration cycle. The PCI Controller can executes Configuration Cycle only in Host-mode. Bits Field R/W Internal bus 31 COCEN R/W Default Description PCI R 0 Configuration Cycle Generation Enable.
CHAPTER 7 PCI CONTROLLER 7.5.7 P_IGSR (Internal Bus-side General Status Register) IGSR register shows the interrupt status of the PCI Controller to the VR4120A. When an event that triggers interruption occurs, the PCI Controller sets a bit in this register corresponds to the event. When the corresponding bit in IIMR is set, the PCI Controller asserts an internal interrupt signal to the VR4120A. Reading this register clears all of bits in the register.
CHAPTER 7 PCI CONTROLLER 7.5.8 P_IIMR (Internal Bus Interrupt Mask Register) IIMR register masks the interruption for each corresponding event. A mask bit, which locates in the same bit position to a corresponding bit in IGSR, controls interruption triggered by the event. When a bit of this register is reset to ‘0’, the corresponding bit of the IGSR is masked. If it is set to ‘1’, the corresponding bit is unmasked.
CHAPTER 7 PCI CONTROLLER 7.5.9 P_PGSR (PCI-side General Status Register) PGSR register shows the interrupt status of the PCI Controller to PCI-side (which means PCI-Host). When an event that triggers interruption occurs, the PCI Controller sets a bit in PGSR corresponds to the type of incident. If the interruption is not masked, the PCI Controller interrupts to PCI-Host using the interrupt signal. Reading this register from PCI-side clears all of bits in the register.
CHAPTER 7 PCI CONTROLLER 7.5.10 P_IIMR (Internal Bus Interrupt Mask Register) IIMR register masks the interruption for each corresponding event. A mask bit, which locates in the same bit position to a corresponding bit in IGSR, controls interruption triggered by the event. When a bit of this register is reset to ‘0’, the corresponding bit of the IGSR is masked. If it is set to ‘1’, the corresponding bit is unmasked.
CHAPTER 7 PCI CONTROLLER 7.5.11 P_PIMR (PCI Interrupt Mask Register) PIMR register masks interruptions. A mask bit, which locates in the same bit position to a corresponding bit in PGSR, can mask the interruption. When a bit of this register is reset to ‘0’, the corresponding bit of the PGSR is masked. When it is set to ‘1’, the corresponding bit is unmasked. When the mask bit is reset and the bit in PGSR is set, the PCI Controller sets the interrupt signal to PCI-Host.
CHAPTER 7 PCI CONTROLLER 7.5.12 P_HMCR (Host Mode Control Register) This register is used to control the PCI-Host functions. Bits Field R/W Internal bus Default Description PCI 31 PRSTO R/W R 0 Reset Out. PCI reset output as Host. The PCI Controller asserts PRSTO during this bit is ‘1’. 30:1 Reserved - - 0 Hardwired to ‘0’s. 0 PARBM R/W R/W 0 PCI arbiter mode. The bit defines arbiter mode. 0: Alternating mode 1: Rotating mode 7.5.
CHAPTER 7 PCI CONTROLLER 7.5.15 P_BCNT (Bridge Control Register) This register is used to control the PCI-internal bus bridge function. Bits Field R/W Internal bus Default Description PCI 31 INITD R/W R 0 Initialize done. The VR4120A should set this bit to ‘1’ after the initialization of the chip. The PCI Controller always issues “retry” against the access on PCI to the PCI Controller bus when this bit is set to a ‘0’. 30:6 Reserved - - 0 Hardwired to ‘0’s.
CHAPTER 7 PCI CONTROLLER 7.5.16 P_PPCR (PCI Power Control Register) This register is used to control the power state for PPMI. See 7.6 Information for Software for further details. Bits Field R/W Internal bus Default Description PCI 31 PMRDY R/W R 0 Power Management Ready. ‘1’ indicates that the transition of power state has been done. When PCI-Host writes to PowerState field of PMCSR register in Configuration Space, this bit is reset to ‘0’.
CHAPTER 7 PCI CONTROLLER 7.5.18 P_RTMR (Retry Timer Register) This register is used to set the limitation of the number of retry repetition. ‘0’ disables this function. See 7.2.3.1 (5) Received target retry as PCI-master for further details. Bits Field R/W Internal bus 31:0 RTMR R/W Default Description PCI R/W 0000_ 0000H Sets the number of retry repetition. ‘0000_0000H’ disables this function. 7.5.19 P_CONFIG (PCI Configuration Registers) 7.5.19.
CHAPTER 7 PCI CONTROLLER Offset Address Register Name Size (byte) Internal bus PCI Description 1000_4100H Vendor ID 2 R R 1000_4102H Device ID 2 R R Vendor ID for NEC = 1033H Device Specific ID 1000_4104H Command 2 R/W R/W PCI Command 1000_4106H Status 2 R/W R/W PCI Status 1000_4108H Revision ID 1 R R Revision ID 1000_4109H Class Code 3 R R Class Code 1000_410CH Cache Line Size 1 R/W R/W Cache Line Size 1000_410DH Latency Timer 1 R/W R/W Maximum Latency T
CHAPTER 7 PCI CONTROLLER 7.5.19.2 Vendor ID register This register identifies the manufacturer of the device. The identifier for NEC is ‘1033H”. Bits Field R/W Internal bus 15:0 Vendor ID R Default Description PCI R 1033H Hardwired to ‘1033H’, which means the Vendor ID of NEC 7.5.19.3 Device ID register This register identifies the particular device. The manufacturer of the device allocates this identifier.
CHAPTER 7 PCI CONTROLLER 7.5.19.4 Command register This register provides coarse control over a device’s ability to generate and respond to PCI cycles. This register is valid in Host-mode. The VR4120A should set the register. Bits Field R/W Internal bus Default Description PCI 15:10 Reserved R R 0 Hardwired to ‘0’s. 9 Fast Back-toBack Enable R R 0 Hardwired to a ‘0’, because the PCI Controller cannot generate fast back-to-back transaction.
CHAPTER 7 PCI CONTROLLER 7.5.19.5 Status register This register is used to show PCI bus related events status. These bits are set when events related to the status on PCI bus and reset to ‘0’ by writing ‘1’. In Host-mode, any bit in this register is not set even if corresponding events occur. Bits Field R/W Internal bus Default Description PCI 15 Detected Parity Error R/W R/W 0 This bit is set to a ‘1’ when the PCI Controller detects a parity error.
CHAPTER 7 PCI CONTROLLER 7.5.19.6 Revision ID register This register specifies a device specific revision identifier. Bits Field R/W Internal bus 7:0 Revision ID R Default Description PCI R 01H Hardwired to ‘01H’ that shows the revision number of the chip. 7.5.19.7 Class code register This register is used to identify the generic function of the device.
CHAPTER 7 PCI CONTROLLER 7.5.19.10 Header type register This register identifies the layout of the second part of the predefined header and also whether or not the device contains multiple functions. Bits Field R/W Internal bus 7:0 Header Type R Default Description PCI R 0 Hardwired to ‘00H’, because the PCI Controller is a single function device and not a PCI-PCI bridge. 7.5.19.
CHAPTER 7 PCI CONTROLLER 7.5.19.14 Subsystem ID register This register is used to uniquely identify the expansion board or subsystem where the PCI device resides. Bits Field R/W Internal bus 15:0 Subsystem ID R/W Default Description PCI R 0 The VR4120A should set the identifier to this register. 7.5.19.15 Cap_Ptr register This register is used to show a linked list of new capabilities implemented by The PCI Controller. The PCI Controller has PPMI function as a new capability.
CHAPTER 7 PCI CONTROLLER 7.5.19.19 Max_Lat register This register specifies how often the device needs to get the PCI bus usage. Bits Field R/W Internal bus 7:0 Max_Lat R/W Default Description PCI R 0 The value should be set by the VR4120A. 7.5.19.20 Cap_ID register This register indicates what kind of data structure of the capability is pointed to. The value ‘01H’ means that the data structure is for the PCI Power Management.
CHAPTER 7 PCI CONTROLLER 7.5.19.23 PMCSR register This register is used to manage the PCI function’s power management state as well as to enable/monitor PME. Bits Field R/W Internal bus Default Description PCI 15:10 PME_Staus R R/W 0 This bit is set when the PCI Controller asserts the PME_B signal independent of the PME_En bit. Writing a ‘1’ to this bit will clear it and cause the PCI Controller to stop asserting a PME_B (if enabled). Writing a ‘0’ has no effect.
CHAPTER 7 PCI CONTROLLER 7.6 Information for Software 7.6.1 NIC mode 7.6.1.1 Initialization (1) Initialization by the VR4120A The PCI Controller issues “retry” to all accesses from PCI-side until INITD bit in P_BCNT register is set to ‘1’. Therefore, Initialization of the chip should be done before INITD bit is set to ‘1’. The following sequence shows an example of initialization procedures required for the VR4120A.
CHAPTER 7 PCI CONTROLLER - Sets a ‘1’ to PME_En bit in PMCSR register, if needed Then, the PCI-Host device initializes internal registers. - Sets the value of base address in P_IBBA register, if needed - Enables mask bits in P_PIMR register, if needed - Sets Retry Timer register, if needed (3) Error In the case that Error described in 7.2.
CHAPTER 7 PCI CONTROLLER - Sets a ‘1’ to “Bus Master Enable” bit in command register, if the chip executes transaction as PCI-master - Sets a ‘1’ to “Memory Write and Invalidate Enable” bit in command register, if needed - Sets a ‘1’ to “Parity Error Response” bit in command register, if needed - Sets a ‘1’ to “System Error Response ” bit in command register, if needed - Sets a the cache line size of system to “Cache Line Size” register - Sets a “Latency Timer” register, if needed - Sets base addresses to
CHAPTER 8 UART 8.1 Overview UART is a serial interface that conforms to the RS-232C communication standard and is equipped with two onechannel interfaces, one for transmission and one for reception. This unit is functionally compatible with the NS16550D. 8.
CHAPTER 8 UART 8.3 Registers This controller uses the NEC NA16550L Mega-Function as its internal UART. This UART is functionally identical to the National Semiconductor NS16550D. Refer to the NEC “User’s Manual. Mega FunctionNA16550L” for more information and programming details. 8.3.
CHAPTER 8 UART 8.3.2 UARTRBR (UART Receiver data Buffer Register) This register holds receive data. It is only accessed when the Divisor Latch Access bit (DLAB) is cleared in the UARTLCR. Bits Field R/W Default Description 31:8 Reserved R 0 Hardwired to 0. 7:0 UDATA R - UART receive data (read only) when DLAB = 0. 8.3.3 UARTTHR (UART Transmitter data Holding Register) This register holds transmit data. It is only accessed when the Divisor Latch Access bit (DLAB) is cleared in the UARTLCR.
CHAPTER 8 UART 8.3.6 UARTDLM (UART Divisor Latch MSB Register) This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the lower 8-bit data in UARTDLL register are together handled as 16-bit data. Bits Field R/W Default 31:8 Reserved R/W 0 7:0 DIVLSB R/W - Description Hardwired to 0. UART divisor latch (see Table 8-1): Only accessed when DLAB = 1 in UARTLCR Table 8-1.
CHAPTER 8 UART 8.3.7 UARTIIR (UART Interrupt ID Register) This register indicates priority levels for interrupts and existence of pending interrupt. From highest to lowest priority, these interrupts are receive line status, receive data ready, character timeout, transmit holding register empty, and modem status. The content of UARTIIR [3] bit is valid only in FIFO mode, and it is always 0 in 16550 mode. UARTIIR [2] bit becomes 1 when UARTIIR [3] bit is set to 1.
CHAPTER 8 UART 8.3.8 UARTFCR (UART FIFO Control Register) This register is used to control the FIFOs: enable FIFO, clear FIFO, and set the receive FIFO trigger level. Bits Field R/W Default Description 31:8 Reserved W 0 Hardwired to 0. 7:6 URFTR W 00 UART Receive FIFO Trigger level. When the trigger level is reached, a Receive-buffer-Full interrupt is generated, if enable by the ERBFI bit in the UARTIER. Number of bytes in Receive FIFO is following.
CHAPTER 8 UART 8.3.9 UARTLCR (UART Line Control Register) This register is used to specify the format for asynchronous communication and exchange and to set the divisor latch access bit. Bit 6 is used to send the break status to the receive side’s UART. When bit 6 = 1, the serial output (URSDO) is forcibly set to the spacing (0) state. The setting of bit 5 becomes valid according to settings in bits 4 and 3. Bits Field R/W Default Description 31:8 Reserved R/W 0 Hardwired to 0.
CHAPTER 8 UART 8.3.10 UARTMCR (UART Modem Control Register) This register controls the state of external URDTR_B and URRTS_B modem-control signals and of the loop-back test. Bits Field R/W Default Description 31:5 Reserved R/W 0 Hardwired to 0. 4 LOOP R/W 0 Loop-Back Test. 1 = loop-back. 0 = normal operation. This is an NEC internal test function. 3 OUT2 R/W 0 Out 2 (internal signal). 1 = OUT2_B (internal) state active. 0 = OUT2_B (internal) state inactive (reset value).
CHAPTER 8 UART 8.3.11 UARTLSR (UART Line Status Register) This register reports the current state of the transmitter and receiver logic. Bits Field R/W Default Description 31:8 Reserved R/W 0 Hardwired to 0. 7 RFERR R/W 0 Receiver FIFO Error. 1 = parity, framing, or break error in receiver buffer. 0 = no such error. 6 TEMT R/W 1 Transmitter Empty. 1 = transmitter holding and shift registers empty. 0 = transmitter holding or shift register not empty.
CHAPTER 8 UART 8.3.12 UARTMSR (UART Modem Status Register) This register reports the current state of and changes in various control signals. Bits Field R/W Default Description 31:8 Reserved R/W 0 Hardwired to 0. 7 DCD R/W 0 Data Carrier Detect. 1 =URDCD_B state active. 0 = URDCD_B state inactive. This bit is the complement of the URDCD_B input signal. If the LOOP bit in the UART Modem Control Register (UARTMCR), is set to 1, the DCD bit is equivalent to the OUT2 bit in the UARTMCR.
CHAPTER 9 TIMER 9.1 Overview There are two Timers. The timers are clocked at the system clock rate. All two timers are read/writeable by the CPU. Timers can be read by the CPU while they are counting. They can be automatically reloaded with the “Timer Set Count Register” value and restarted. Two timers issues interrupt to the CPU upon reaching their maximum value, the interrupts can be enabled/disabled.
CHAPTER 9 TIMER 9.3 Registers 9.3.1 Register map Offset Address Register Name R/W Access Description 1000_00B0H TMMR R/W W/H/B Timer Mode Register 1000_00B4H TM0CSR R/W W/H/B Timer CH0 Count Set Register 1000_00B8H TM1CSR R/W W/H/B Timer CH1 Count Set Register 1000_00BCH TM0CCR R W/H/B Timer CH0 Current Count Register 1000_00C0H TM1CCR R W/H/B Timer CH1 Current Count Register Remarks 1.
CHAPTER 9 TIMER 9.3.3 TM0CSR (Timer CH0 Count Set Register) The Timer CH0 Count Set Register “TM0CSR” is a read-write and 32-bit word-aligned register. CPU (VR4120A) loads a value in it and the counter starts counting down from the (TM0CSR –1) value. When it reaches 0000_0000H, it generates an interrupt to the CPU via Interrupt Status Register “ISR” if the TM0IS in ISR is not masked by TM0IM in IMR.
CHAPTER 10 MICRO WIRE 10.1 Overview This EEPROM interface is compatible with the Micro Wire serial interface. Connection to the “NM93C46” serial EEPROM, manufactured by National Semiconductor, is recommended. Serial EEPROM memory area is accessed in-directly throghout Micro Wire-macro registers, that is ECCR and ERDR registers. To access the EEPROM, the VR4120A writes a command into the ECCR register of Micro Wiremacro.
CHAPTER 10 MICRO WIRE 10.2 Operations 10.2.1 Data read at the power up load After reset release, power up load processes starts. In case of the value from EEPROM address 00H is: 1. A5A5H System Controller sets the EEPROM data (address: 01H to 06H) in the internal registers (MACAR1, MACAR2, MACAR3). 2. NOT A5A5H System Controller sets the fix data “0000_0000H” in the internal registers (MACAR1, MACAR2, MACAR3). Table 10-1.
CHAPTER 10 MICRO WIRE 10.3 Registers 10.3.1 Register map Offset Address 1000_00D0H Register Name R/W ECCR W Access W/H/B Description EEPROM Command Control Register 1000_00D4H ERDR R W/H/B EEPROM Read Data Register 1000_00D8H MACAR1 R W/H/B MAC Address Register 1 1000_00DCH MACAR2 R W/H/B MAC Address Register 2 1000_00E0H MACAR3 R W/H/B MAC Address Register 3 10.3.
CHAPTER 10 MICRO WIRE 10.3.6 MACAR3 (MAC Address Register 3) Bits Field R/W Default 31:16 SERIAL EEPROM 06H ADDRESS R 0 15:0 SERIAL EEPROM 05H ADDRESS R 0 430 Description Stored Serial EEPROM data of address 05H, 06H.
APPENDIX A MIPS III INSTRUCTION SET DETAILS This chapter provides a detailed description of the operation of each instruction in both 32- and 64-bit modes. The instructions are listed in alphabetical order. A.1 Instruction Notation Conventions In this chapter, all variable subfields in an instruction format (such as rs, rt, immediate, etc.) are shown in lowercase names. For the sake of clarity, we sometimes use an alias for a variable subfield in the formats of specific instructions.
APPENDIX A MIPS III INSTRUCTION SET DETAILS Table A-1. CPU Instruction Operation Notations Symbol Description ← Assignment || Bit string concatenation x y Replication of bit value x into a y-bit string. x is always a single-bit value xy:z Selection of bits y through z of bit string x. Little-endian bit notation is always used.
APPENDIX A MIPS III INSTRUCTION SET DETAILS (1) Instruction notation examples The following examples illustrate the application of some of the instruction notation conventions: Example 1: GPR [rt] ← immediate || 0 16 Sixteen zero bits are concatenated with an immediate value (typically 16 bits), and the 32-bit string is assigned to general register rt. Example 2: 16 (immediate15) || immediate15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS As shown in Table A-3, the Access Type field indicates the size of the data item to be loaded or stored. Regardless of access type or byte-numbering order (endian), the address specifies the byte that has the smallest byte address in the addressed field. This is the rightmost byte in the VR4120A CPU since it supports the little-endian order only. Table A-3.
APPENDIX A MIPS III INSTRUCTION SET DETAILS A.4 System Control Coprocessor (CP0) Instructions There are some special limitations imposed on operations involving CP0 that is incorporated within the CPU. Although load and store instructions to transfer data to/from coprocessors and to move control to/from coprocessor instructions are generally permitted by the MIPS architecture, CP0 is given a somewhat protected status since it has responsibility for exception handling and memory management.
APPENDIX A MIPS III INSTRUCTION SET DETAILS ADD ADD Add 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 ADD 100000 6 5 5 5 5 6 Format: ADD rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. In 64-bit mode, the operands must be valid sign-extended, 32-bit values.
APPENDIX A MIPS III INSTRUCTION SET DETAILS ADDI ADDI Add Immediate 31 26 25 21 20 16 15 0 ADDI 001000 rs rt immediate 6 5 5 16 Format: ADDI rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. In 64-bit mode, the operand must be valid sign-extended, 32-bit values. An overflow exception occurs if carries out of bits 30 and 31 differ (2’s complement overflow).
APPENDIX A MIPS III INSTRUCTION SET DETAILS ADDIU 31 ADDIU Add Immediate Unsigned 26 25 21 20 16 15 0 ADDIU 001001 rs rt immediate 6 5 5 16 Format: ADDIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. No integer overflow exception occurs under any circumstances. In 64-bit mode, the operand must be valid sign-extended, 32-bit values.
APPENDIX A MIPS III INSTRUCTION SET DETAILS ADDU ADDU Add Unsigned 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 ADDU 100001 6 5 5 5 5 6 Format: ADDU rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. No integer overflow exception occurs under any circumstances. In 64-bit mode, the operands must be valid sign-extended, 32-bit values.
APPENDIX A MIPS III INSTRUCTION SET DETAILS AND AND And 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 AND 100100 6 5 5 5 5 6 Format: AND rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical AND operation. The result is placed into general register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS ANDI ANDI And Immediate 31 26 25 21 20 16 15 0 ANDI 001100 rs rt immediate 6 5 5 16 Format: ANDI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical AND operation. The result is placed into general register rt. Operation: 32 T: GPR [ rt] ← 016 || (immediate and GPR [ rs]15...0) 64 T: GPR [ rt] ← 048 || (immediate and GPR [ rs]15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0F BC0F Branch On Coprocessor 0 False 31 26 25 21 20 16 15 0 COPz Note 0100XX BC 01000 BCF 00000 offset 6 5 5 16 Format: BC0F offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0FL 31 Branch On Coprocessor 0 False Likely (1/2) 26 25 COPz Note 0100XX 21 20 16 15 0 BC 01000 BCFL 00010 offset 5 5 16 6 BC0FL Format: BC0FL offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0FL Branch On Coprocessor 0 False Likely (2/2) BC0FL Opcode Table: BC0FL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 Opcode 444 Coprocessor number BC sub-opcode Branch condition Preliminary User’s Manual S15543EJ1V0UM 0
APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0T BC0T Branch On Coprocessor 0 True 31 26 25 21 20 16 15 0 COPz Note 0100XX BC 01000 BCT 00001 offset 6 5 5 16 Format: BC0T offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0TL 31 Branch On Coprocessor 0 True Likely (1/2) 26 25 21 20 16 15 BC0TL 0 COPz 0 1 0 0 X X Note BC 01000 BCTL 00011 offset 6 5 5 16 Format: BC0TL offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0TL Branch On Coprocessor 0 True Likely (2/2) BC0TL Opcode Table: BC0TL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 Opcode Coprocessor number BC sub-opcode 0 Branch condition Preliminary User’s Manual S15543EJ1V0UM 447
APPENDIX A MIPS III INSTRUCTION SET DETAILS BEQ BEQ Branch On Equal 31 26 25 21 20 16 15 0 BEQ 000100 rs rt offset 6 5 5 16 Format: BEQ rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general register rt are compared.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BEQL BEQL Branch On Equal Likely 31 26 25 21 20 16 15 0 BEQL 010100 rs rt offset 6 5 5 16 Format: BEQL rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general register rt are compared.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BGEZ Branch On Greater Than Or Equal To Zero 31 26 25 21 20 16 15 BGEZ 0 REGIMM 000001 rs BGEZ 00001 offset 6 5 5 16 Format: BGEZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BGEZAL 31 Branch On Greater Than Or Equal To Zero And Link 26 25 21 20 16 15 BGEZAL 0 REGIMM 000001 rs BGEZAL 10001 offset 6 5 5 16 Format: BGEZAL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is placed in the link register, r31.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BGEZALL 31 Branch On Greater Than Or Equal To Zero And Link Likely 26 25 21 20 16 15 BGEZALL 0 REGIMM 000001 rs BGEZALL 10011 offset 6 5 5 16 Format: BGEZALL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is placed in the link register, r31.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BGEZL Branch On Greater Than Or Equal To Zero Likely BGEZL 31 26 25 21 20 16 15 0 REGIMM 000001 rs BGEZL 00011 offset 6 5 5 16 Format: BGEZL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BGTZ BGTZ Branch On Greater Than Zero 31 26 25 21 20 16 15 0 BGTZ 000111 rs 0 00000 offset 6 5 5 16 Format: BGTZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BGTZL 31 Branch On Greater Than Zero Likely 26 25 21 20 BGTZL 16 15 0 BGTZL 010111 rs 0 00000 offset 6 5 5 16 Format: BGTZL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs are compared to zero.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BLEZ Branch On Less Than Or Equal To Zero 31 26 25 21 20 16 15 BLEZ 0 BLEZ 000110 rs 0 00000 offset 6 5 5 16 Format: BLEZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs are compared to zero.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BLEZL 31 Branch On Less Than Or Equal To Zero Likely 26 25 21 20 16 15 BLEZL 0 BLEZL 010110 rs 0 00000 offset 6 5 5 16 Format: BLEZL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs is compared to zero.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BLTZ BLTZ Branch On Less Than Zero 31 26 25 21 20 16 15 0 REGIMM 000001 rs BLTZ 00000 offset 6 5 5 16 Format: BLTZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. If the contents of general register rs are smaller than zero, then the program branches to the target address, with a delay of one instruction.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BLTZAL 31 Branch On Less Than Zero And Link 26 25 21 20 16 15 BLTZAL 0 REGIMM 000001 rs BLTZAL 10000 offset 6 5 5 16 Format: BLTZAL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is placed in the link register, r31.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BLTZALL 31 Branch On Less Than Zero And Link Likely 26 25 21 20 16 15 BLTZALL 0 REGIMM 000001 rs BLTZALL 10010 offset 6 5 5 16 Format: BLTZALL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is placed in the link register, r31.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BLTZL 31 Branch On Less Than Zero Likely 26 25 21 20 BLTZL 16 15 0 REGIMM 000001 rs BLTZL 00010 offset 6 5 5 16 Format: BLTZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BNE BNE Branch On Not Equal 31 26 25 21 20 16 15 0 BNE 000101 rs rt offset 6 5 5 16 Format: BNE rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general register rt are compared.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BNEL BNEL Branch On Not Equal Likely 31 26 25 21 20 16 15 0 BNEL 010101 rs rt offset 6 5 5 16 Format: BNEL rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general register rt are compared.
APPENDIX A MIPS III INSTRUCTION SET DETAILS BREAK 31 BREAK Breakpoint 26 25 6 5 0 SPECIAL 000000 code BREAK 001101 6 20 6 Format: BREAK Description: A breakpoint trap occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.
APPENDIX A MIPS III INSTRUCTION SET DETAILS CACHE 31 CACHE Cache (1/4) 26 25 21 20 16 15 0 CACHE 101111 base op offset 6 5 5 16 Format: CACHE op, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The virtual address is translated to a physical address using the TLB, and the 5-bit sub-opcode specifies a cache operation for that address.
APPENDIX A MIPS III INSTRUCTION SET DETAILS CACHE CACHE Cache (2/4) Write back from a cache goes to main memory. The main memory address to be written is specified by the cache tag and not the physical address translated using TLB. TLB Refill and TLB Invalid exceptions can occur on any operation. For Index operations Note for addresses in the unmapped areas, unmapped addresses may be used to avoid TLB exceptions. Index operations never cause a TLB Modified exception.
APPENDIX A MIPS III INSTRUCTION SET DETAILS CACHE CACHE Cache (3/4) Code Cache Name Operation 0 I Index_Invalidate Set the cache state of the cache block to Invalid. 0 D Index_Write_ Back_Invalidate Examine the cache state and W bit of the primary data cache block at the index specified by the virtual address. If the state is not Invalid and the W bit is set, then write back the block to memory. The address to write is taken from the primary cache tag.
APPENDIX A MIPS III INSTRUCTION SET DETAILS CACHE Cache (4/4) Operation: 32, 64 T: vAddr ← ((offset15) 48 || offset15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS DADD DADD Doubleword Add 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 DADD 101100 6 5 5 5 5 6 Format: DADD rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. An overflow exception occurs if the carries out of bits 62 and 63 differ (2’s complement overflow).
APPENDIX A MIPS III INSTRUCTION SET DETAILS DADDI 31 DADDI Doubleword Add Immediate 26 25 21 20 16 15 0 DADDI 011000 rs rt immediate 6 5 5 16 Format: DADDI rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. An overflow exception occurs if carries out of bits 62 and 63 differ (2’s complement overflow).
APPENDIX A MIPS III INSTRUCTION SET DETAILS DADDIU 31 Doubleword Add Immediate Unsigned 26 25 21 20 DADDIU 16 15 0 DADDIU 011001 rs rt immediate 6 5 5 16 Format: DADDIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. No integer overflow exception occurs under any circumstances.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DADDU 31 DADDU Doubleword Add Unsigned 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 DADDU 101101 6 5 5 5 5 6 Format: DADDU rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. No overflow exception occurs under any circumstances.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DDIV DDIV Doubleword Divide 31 26 25 21 20 16 15 SPECIAL 000000 rs rt 6 5 5 6 5 00 0 0000 0000 10 0 DDIV 011110 6 Format: DDIV rs, rt Description: The contents of general register rs are divided by the contents of general register rt, treating both operands as 2’s complement values. No overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DDIVU 31 DDIVU Doubleword Divide Unsigned 26 25 21 20 16 15 6 5 0 SPECIAL 000000 rs rt 0 00 0000 0000 DDIVU 011111 6 5 5 10 6 Format: DDIVU rs, rt Description: The contents of general register rs are divided by the contents of general register rt, treating both operands as unsigned values. No integer overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DIV DIV Divide 31 26 25 21 20 16 15 SPECIAL 000000 rs rt 6 5 5 6 5 00 0 0000 0000 10 0 DIV 011010 6 Format: DIV rs, rt Description: The contents of general register rs are divided by the contents of general register rt, treating both operands as 2’s complement values. No overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DIVU DIVU Divide Unsigned 31 26 25 21 20 16 15 6 5 0 SPECIAL 000000 rs rt 0 00 0000 0000 DIVU 011011 6 5 5 10 6 Format: DIVU rs, rt Description: The contents of general register rs are divided by the contents of general register rt, treating both operands as unsigned values. No integer overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DMACC 31 DMACC Doubleword Multiply and Accumulate (1/3) 26 25 21 20 16 15 11 10 SPECIAL 000000 rs rt rd 6 5 5 5 7 6 9 sat 0 0 0 us 1 3 1 5 0 DMACC 101001 6 Format: DMACC rd, rs, rt DMACCU rd, rs, rt DMACCS rd, rs, rt DMACCUS rd, rs, rt Description: DMACC instruction differs mnemonics by each setting of op codes sat, hi and us as follows.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DMACC • Doubleword Multiply and Accumulate (2/3) DMACC When saturation processing is not executed (sat = 0): DMACC, DMACCU instructions The contents of general register rs is multiplied by the contents of general register rt. If both operands are set as "us = 1" (DMACCU instruction), the contents are handled as 32 bit unsigned data. If they are set as "us = 0" (DMACC instruction), the contents are handled as 32 bit signed integers.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DMACC Doubleword Multiply and Accumulate (3/3) DMACC Operation: 64, sat=0, us=0 (DMACC instruction) T: temp1 ← ((GPR[rs]31) 32 32 || GPR [rt]) 32 || GPR [rt]) || GPR [rs]) * ((GPR[rt]31) temp2 ← temp1 + LO LO ← temp2 GPR[rd] ← LO 64, sat=0, us=1 (DMACCU instruction) T: temp1 ← (0 32 || GPR [rs]) * (0 32 || GPR [rt]) temp2 ← temp1 + LO LO ← temp2 GPR[rd] ← LO 64, sat=1, us=0 (DMACCS instruction) T: temp1 ← ((GPR[rs]31) 32 || GPR [rs]) * ((GPR[r
APPENDIX A MIPS III INSTRUCTION SET DETAILS DMFC0 31 Doubleword Move From System Control Coprocessor 26 25 21 20 16 15 DMFC0 11 10 COP0 010000 DMF 00001 rt rd 6 5 5 5 0 000 0 0000 0000 11 Format: DMFC0 rt, rd Description: The contents of coprocessor register rd of the CP0 are loaded into general register rt. This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DMTC0 31 Doubleword Move To System Control Coprocessor 26 25 21 20 16 15 DMTC0 11 10 COP0 010000 DMT 00101 rt rd 6 5 5 5 0 000 0 0000 0000 11 Format: DMTC0 rt, rd Description: The contents of general register rt are loaded into coprocessor register rd of the CP0. This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DMULT 31 DMULT Doubleword Multiply 26 25 21 20 16 15 SPECIAL 000000 rs rt 6 5 5 6 5 00 0 0000 0000 0 DMULT 011100 10 6 Format: DMULT rs, rt Description: The contents of general registers rs and rt are multiplied, treating both operands as 2’s complement values. No integer overflow exception occurs under any circumstances.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DMULTU 31 DMULTU Doubleword Multiply Unsigned 26 25 21 20 16 15 SPECIAL 000000 rs rt 6 5 5 6 5 00 0 0000 0000 10 0 DMULTU 011101 6 Format: DMULTU rs, rt Description: The contents of general register rs and the contents of general register rt are multiplied, treating both operands as unsigned values. No overflow exception occurs under any circumstances.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSLL DSLL Doubleword Shift Left Logical 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa DSLL 111000 6 5 5 5 5 6 Format: DSLL rd, rt, sa Description: The contents of general register rt are shifted left by sa bits, inserting zeros into the low-order bits. The result is placed in register rd. This operation is defined in 64-bit mode or in 32-bit kernel mode.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSLLV 31 DSLLV Doubleword Shift Left Logical Variable 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 DSLLV 010100 6 5 5 5 5 6 Format: DSLLV rd, rt, rs Description: The contents of general register rt are shifted left by the number of bits specified by the low-order six bits contained in general register rs, inserting zeros into the low-order bits. The result is placed in register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSLL32 31 DSLL32 Doubleword Shift Left Logical + 32 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa DSLL32 111100 6 5 5 5 5 6 Format: DSLL32 rd, rt, sa Description: The contents of general register rt are shifted left by 32 + sa bits, inserting zeros into the low-order bits. The result is placed in register rd. This operation is defined in 64-bit mode or in 32-bit kernel mode.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRA DSRA Doubleword Shift Right Arithmetic 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa DSRA 111011 6 5 5 5 5 6 Format: DSRA rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, sign-extending the high-order bits. The result is placed in register rd. This operation is defined in 64-bit mode or in 32-bit kernel mode.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRAV 31 Doubleword Shift Right Arithmetic Variable 26 25 21 20 16 15 11 10 DSRAV 6 5 0 SPECIAL 000000 rs rt rd 0 00000 DSRAV 010111 6 5 5 5 5 6 Format: DSRAV rd, rt, rs Description: The contents of general register rt are shifted right by the number of bits specified by the low-order six bits of general register rs, sign-extending the high-order bits. The result is placed in register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRA32 31 DSRA32 Doubleword Shift Right Arithmetic + 32 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa DSRA32 111111 6 5 5 5 5 6 Format: DSRA32 rd, rt, sa Description: The contents of general register rt are shifted right by 32 + sa bits, sign-extending the high-order bits. The result is placed in register rd. This operation is defined in 64-bit mode or in 32-bit kernel mode.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRL DSRL Doubleword Shift Right Logical 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa DSRL 111010 6 5 5 5 5 6 Format: DSRL rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, inserting zeros into the high-order bits. The result is placed in register rd. This operation is defined in 64-bit mode or in 32-bit kernel mode.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRLV 31 DSRLV Doubleword Shift Right Logical Variable 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 DSRLV 010110 6 5 5 5 5 6 Format: DSRLV rd, rt, rs Description: The contents of general register rt are shifted right by the number of bits specified by the low-order six bits of general register rs, inserting zeros into the high-order bits. The result is placed in register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRL32 31 DSRL32 Doubleword Shift Right Logical + 32 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa DSRL32 111110 6 5 5 5 5 6 Format: DSRL32 rd, rt, sa Description: The contents of general register rt are shifted right by 32 + sa bits, inserting zeros into the high-order bits. The result is placed in register rd. This operation is defined in 64-bit mode or in 32-bit kernel mode.
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSUB DSUB Doubleword Subtract 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 DSUB 101110 6 5 5 5 5 6 Format: DSUB rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result. The result is placed into general register rd. An integer overflow exception takes place if the carries out of bits 62 and 63 differ (2's complement overflow).
APPENDIX A MIPS III INSTRUCTION SET DETAILS DSUBU 31 DSUBU Doubleword Subtract Unsigned 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 DSUBU 101111 6 5 5 5 5 6 Format: DSUBU rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result. The result is placed into general register rd. The only difference between this instruction and the DSUB instruction is that DSUBU never traps on overflow.
APPENDIX A MIPS III INSTRUCTION SET DETAILS ERET ERET Exception Return 31 26 25 24 COP0 010000 CO 1 6 1 6 5 000 0000 0 0000 0000 0000 19 0 ERET 011000 6 Format: ERET Description: ERET is the instruction for returning from an interrupt, exception, or error trap. Unlike a branch or jump instruction, ERET does not execute the next instruction. ERET must not itself be placed in a branch delay slot.
APPENDIX A MIPS III INSTRUCTION SET DETAILS HIBERNATE 31 Hibernate HIBERNATE 26 25 24 COP0 010000 CO 1 6 1 6 5 0 000 0000 0000 0000 0000 0 HIBERNATE 100011 19 6 Format: HIBERNATE Description: HIBERNATE instruction starts mode transition from Fullspeed mode to Hibernate mode. When the HIBERNATE instruction finishes the WB stage, the processor wait by the SysAD bus is idle state, after then the internal clocks and the system interface clocks will shut down, thus freezing the pipeline.
APPENDIX A MIPS III INSTRUCTION SET DETAILS J J Jump 31 26 25 0 J 000010 target 6 26 Format: J target Description: The 26-bit target address is shifted left two bits and combined with the high-order four bits of the address of the delay slot. The program unconditionally jumps to this calculated address with a delay of one instruction. Operation: 32 T: temp ← target T+1: PC ← PC31..28 || temp || 02 64 T: temp ← target T+1: PC ← PC63..
APPENDIX A MIPS III INSTRUCTION SET DETAILS JAL Jump And Link 31 26 25 JAL 0 JAL 000011 target 6 26 Format: JAL target Description: The 26-bit target address is shifted left two bits and combined with the high-order four bits of the address of the delay slot. The program unconditionally jumps to this calculated address with a delay of one instruction. The address of the instruction after the delay slot is placed in the link register, r31.
APPENDIX A MIPS III INSTRUCTION SET DETAILS JALR 31 JALR Jump And Link Register 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs 0 00000 rd 0 00000 JALR 001001 6 5 5 5 5 6 Format: JALR rs JALR rd, rs Description: The program unconditionally jumps to the address contained in general register rs, with a delay of one instruction.
APPENDIX A MIPS III INSTRUCTION SET DETAILS JALX Jump And Link Exchange 31 26 25 JALX 0 JALX 011101 target 6 26 Format: JALX target Description: When a MIPS16 instruction can be executed, a 26-bit target is shifted to left by 2 bits and then added to higher 4 bits of the delay slot's address to make a target address. The program unconditionally jumps to the target address with a delay of one instruction.
APPENDIX A MIPS III INSTRUCTION SET DETAILS JR JR Jump Register 31 26 25 21 20 SPECIAL 000000 rs 6 5 6 5 000 0000 0 0000 0000 15 0 JR 001000 6 Format: JR rs Description: The program unconditionally jumps to the address contained in general register rs, with a delay of one instruction.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LB 31 26 25 Load Byte LB 16 15 0 21 20 LB 100000 base rt offset 6 5 5 16 Format: LB rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the byte at the memory location specified by the effective address are sign-extended and loaded into general register rt. Operation: 32 T: vAddr ← ((offset15) 16 || offset15..
APPENDIX A MIPS III INSTRUCTION SET DETAILS LBU LBU Load Byte Unsigned 31 26 25 21 20 16 15 0 LBU 100100 base rt offset 6 5 5 16 Format: LBU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the byte at the memory location specified by the effective address are zero-extended and loaded into general register rt. Operation: 32 T: vAddr ← ((offset15) 16 || offset15..
APPENDIX A MIPS III INSTRUCTION SET DETAILS LD 31 26 25 Load Doubleword LD 16 15 0 21 20 LD 110111 base rt offset 6 5 5 16 Format: LD rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the 64-bit doubleword at the memory location specified by the effective address are loaded into general register rt.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LDL LDL Load Doubleword Left (1/3) 31 26 25 21 20 16 15 0 LDL 011010 base rt offset 6 5 5 16 Format: LDL rt, offset (base) Description: This instruction can be used in combination with the LDR instruction to load a register with eight consecutive bytes from memory, when the bytes cross a doubleword boundary.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LDL Load Doubleword Left (2/3) LDL The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LDL (or LDR) instruction which also specifies register rt. No address error exceptions due to alignment are possible. This operation is defined in 64-bit mode or in 32-bit kernel mode.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LDL LDL Load Doubleword Left (3/3) Given a doubleword in a register and a doubleword in memory, the operation of LDL is as follows: LDL Register A B C D E F G H Memory I J K L M N O P vAddr2..
APPENDIX A MIPS III INSTRUCTION SET DETAILS LDR LDR Load Doubleword Right (1/3) 31 26 25 21 20 16 15 0 LDR 011011 base rt offset 6 5 5 16 Format: LDR rt, offset (base) Description: This instruction can be used in combination with the LDL instruction to load a register with eight consecutive bytes from memory, when the bytes cross a doubleword boundary. LDL instruction loads the high-order portion of data and LDR instruction loads the low-order portion of data.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LDR Load Doubleword Right (2/3) LDR The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LDR (or LDL) instruction which also specifies register rt. No address error exceptions due to alignment are possible. This operation is defined in 64-bit mode or in 32-bit kernel mode.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LDR LDR Load Doubleword Right (3/3) Given a doubleword in a register and a doubleword in memory, the operation of LDR is as follows: LDR Register A B C D E F G H Memory I J K L M N O P vAddr2..
APPENDIX A MIPS III INSTRUCTION SET DETAILS LH 31 26 25 Load Halfword LH 16 15 0 21 20 LH 100001 base rt offset 6 5 5 16 Format: LH rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the halfword at the memory location specified by the effective address are sign-extended and loaded into general register rt.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LHU LHU Load Halfword Unsigned 31 26 25 21 20 16 15 0 LHU 100101 base rt offset 6 5 5 16 Format: LHU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the halfword at the memory location specified by the effective address are zero-extended and loaded into general register rt.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LUI LUI Load Upper Immediate 31 26 25 21 20 16 15 0 LUI 001111 0 00000 rt immediate 6 5 5 16 Format: LUI rt, immediate Description: The 16-bit immediate is shifted left 16 bits and concatenated to 16 bits of zeros. The result is placed into general register rt. In 64-bit mode, the loaded word is sign-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LW LW Load Word 31 26 25 21 20 16 15 0 LW 100011 base rt offset 6 5 5 16 Format: LW rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the word at the memory location specified by the effective address are loaded into general register rt. In 64-bit mode, the loaded word is sign-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LWL LWL Load Word Left (1/3) 31 26 25 21 20 16 15 0 LWL 100010 base rt offset 6 5 5 16 Format: LWL rt, offset (base) Description: This instruction can be used in combination with the LWR instruction to load a register with four consecutive bytes from memory, when the bytes cross a word boundary.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LWL Load Word Left (2/3) LWL The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LWL (or LWR) instruction which also specifies register rt. No address error exceptions due to alignment are possible. Operation: 32 T: vAddr ← ((offset15) 16 || offset15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS LWL LWL Load Word Left (3/3) Given a doubleword in a register and a doubleword in memory, the operation of LWL is as follows: LWL Register A B C D E F G H Memory I J K L M N O P vAddr2..
APPENDIX A MIPS III INSTRUCTION SET DETAILS LWR LWR Load Word Right (1/3) 31 26 25 21 20 16 15 0 LWR 100110 base rt offset 6 5 5 16 Format: LWR rt, offset (base) Description: This instruction can be used in combination with the LWL instruction to load a register with four consecutive bytes from memory, when the bytes cross a word boundary.
APPENDIX A MIPS III INSTRUCTION SET DETAILS LWR Load Word Right (2/3) LWR The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LWR (or LWL) instruction which also specifies register rt. No address error exceptions due to alignment are possible. Operation: 32 T: vAddr ← ((offset15) 16 || offset15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS LWR LWR Load Word Right (3/3) Given a word in a register and a word in memory, the operation of LWR is as follows: LWR Register A B C D E F G H Memory I J K L M N O P vAddr2..
APPENDIX A MIPS III INSTRUCTION SET DETAILS LWU LWU Load Word Unsigned 31 26 25 21 20 16 15 0 LWU 101111 base rt offset 6 5 5 16 Format: LWU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the word at the memory location specified by the effective address are loaded into general register rt. The loaded word is zero-extended.
APPENDIX A MIPS III INSTRUCTION SET DETAILS MACC 31 MACC Multiply and Accumulate (1/5) 26 25 21 20 16 15 11 10 SPECIAL 000000 rs rt rd 6 5 5 5 76 9 8 sat hi 0 0 us 1 1 2 1 5 0 MACC 101000 6 Format: MACC rd, rs, rt MACCU rd, rs, rt MACCHI rd, rs, rt MACCHIU rd, rs, rt MACCS rd, rs, rt MACCUS rd, rs, rt MACCHIS rd, rs, rt MACCHIUS rd, rs, rt Description: MACC instruction differs mnemonics by each setting of op codes sat, hi and us as follows.
APPENDIX A MIPS III INSTRUCTION SET DETAILS MACC • MACC Multiply and Accumulate (2/5) When saturation processing is not executed (sat = 0): MACC, MACCU, MACCHI, MACCHIU instructions The contents of general register rs is multiplied to the contents of general register rt. If both operands are set as "us = 1" (MACCU, MACCHIU instructions), the contents are handled as 32 bit unsigned data. If they are set as "us = 0" (MACC, MACCHI instructions), the contents are handled as 32 bit signed integers.
APPENDIX A MIPS III INSTRUCTION SET DETAILS MACC Multiply and Accumulate (3/5) Operation: 32, sat=0, hi=0, us=0 (MACC instruction) T: temp1 ← GPR[rs] * GPR[rt] temp2 ← temp1 + (HI || LO) LO ← temp263..32 HI ← temp231..0 GPR[rd] ← LO 32, sat=0, hi=0, us=1 (MACCU instruction) T: temp1 ← (0 || GPR[rs]) * (0 || GPR[rt]) temp2 ← temp1 + ((0 || HI) || (0 || LO)) LO ← temp263..32 HI ← temp231..
APPENDIX A MIPS III INSTRUCTION SET DETAILS MACC Multiply and Accumulate (4/5) MACC 32, sat=1, hi=1, us=0 (MACCHIS instruction) T: temp1 ← GPR[rs] * GPR[rt] temp2 ← saturation(temp1 + (HI || LO)) LO ← temp263..32 HI ← temp231..0 GPR[rd] ← HI 32, sat=1, hi=1, us=1 (MACCHIUS instruction) T: temp1 ← (0 || GPR[rs]) * (0 || GPR[rt]) temp2 ← saturation(temp1 + ((0 || HI) || (0 || LO))) LO ← temp263..32 HI ← temp231..
APPENDIX A MIPS III INSTRUCTION SET DETAILS MACC Multiply and Accumulate (5/5) 64, sat=1, hi=0, us=0 (MACCS instruction) T: temp1 ← ((GPR[rs]31) 32 || GPR[rs]) * ((GPR[rt]31) 32 || GPR[rt]) 32 || GPR[rt]) temp2 ← saturation(temp1 + (HI31..0 || LO31..0)) LO ← ((temp263) HI ← ((temp231) 32 32 || temp263..32) || temp231..0) GPR[rd] ← LO 64, sat=1, hi=0, us=1 (MACCUS instruction) T: temp1 ← (0 32 || GPR[rs]) * (0 32 || GPR[rt]) temp2 ← saturation(temp1 + (HI31..0 || LO31..
APPENDIX A MIPS III INSTRUCTION SET DETAILS MFC0 MFC0 Move From System Control Coprocessor 31 26 25 21 20 16 15 11 10 COP0 010000 MF 00000 rt rd 6 5 5 5 0 000 0 0000 0000 11 Format: MFC0 rt, rd Description: The contents of coprocessor register rd of the CP0 are loaded into general register rt. Operation: 32 T: data ← CPR [0, rd] T+1: GPR [rt] ← data 64 T: data ← CPR [0, rd] T+1: GPR [rt] ← (data 31)32 || data31...
APPENDIX A MIPS III INSTRUCTION SET DETAILS MFHI MFHI Move From HI 31 26 25 SPECIAL 000000 16 15 00 6 0 0000 10 0000 6 5 11 10 0 rd 0 00000 MFHI 010000 5 5 6 Format: MFHI rd Description: The contents of special register HI are loaded into general register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS MFLO MFLO Move From LO 31 26 25 SPECIAL 000000 16 15 00 6 0 0000 10 0000 6 5 11 10 0 rd 0 00000 MFLO 010010 5 5 6 Format: MFLO rd Description: The contents of special register LO are loaded into general register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS MTC0 MTC0 Move To Coprocessor0 31 21 20 26 25 16 15 11 10 COP0 010000 MT 00100 rt rd 6 5 5 5 0 0 000 0000 0000 11 Format: MTC0 rt, rd Description: The contents of general register rt are loaded into coprocessor register rd of coprocessor 0.
APPENDIX A MIPS III INSTRUCTION SET DETAILS MTHI MTHI Move To HI 31 26 25 21 20 6 5 0 SPECIAL 000000 rs 0 000 0000 0000 0000 MTHI 010001 6 5 15 6 Format: MTHI rs Description: The contents of general register rs are loaded into special register HI. If a MTHI operation is executed following a MULT, MULTU, DIV, or DIVU instruction, but before any MFLO, MFHI, MTLO, or MTHI instructions, the contents of special register HI are undefined.
APPENDIX A MIPS III INSTRUCTION SET DETAILS MTLO MTLO Move To LO 31 26 25 21 20 6 5 0 SPECIAL 000000 rs 0 000 0000 0000 0000 MTLO 010011 6 5 15 6 Format: MTLO rs Description: The contents of general register rs are loaded into special register LO. If an MTLO operation is executed following a MULT, MULTU, DIV, or DIVU instruction, but before any MFLO, MFHI, MTLO, or MTHI instructions, the contents of special register LO are undefined.
APPENDIX A MIPS III INSTRUCTION SET DETAILS MULT MULT Multiply 31 26 25 16 15 21 20 SPECIAL 000000 rs rt 6 5 5 6 5 00 0 0000 0000 0 MULT 011000 10 6 Format: MULT rs, rt Description: The contents of general registers rs and rt are multiplied, treating both operands as signed 32-bit integer. No integer overflow exception occurs under any circumstances. In 64-bit mode, the operands must be valid 32-bit, sign-extended values.
APPENDIX A MIPS III INSTRUCTION SET DETAILS MULTU 31 MULTU Multiply Unsigned 26 25 16 15 21 20 SPECIAL 000000 rs rt 6 5 5 6 5 00 0 0000 0000 10 0 MULTU 011001 6 Format: MULTU rs, rt Description: The contents of general register rs and the contents of general register rt are multiplied, treating both operands as unsigned values. No overflow exception occurs under any circumstances. In 64-bit mode, the operands must be valid 32-bit, sign-extended values.
APPENDIX A MIPS III INSTRUCTION SET DETAILS NOR NOR Nor 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 NOR 100111 6 5 5 5 5 6 Format: NOR rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical NOR operation. The result is placed into general register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS OR OR Or 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 OR 100101 6 5 5 5 5 6 Format: OR rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical OR operation. The result is placed into general register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS ORI ORI Or Immediate 31 26 25 21 20 16 15 0 ORI 001101 rs rt immediate 6 5 5 16 Format: ORI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical OR operation. The result is placed into general register rt. Operation: 32 T: GPR [rt] ← GPR [rs] 31...16 || (immediate or GPR [rs] 15...0) 64 T: GPR [rt] ← GPR [rs] 63...16 || (immediate or GPR [rs] 15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS SB 31 26 25 Store Byte SB 16 15 0 21 20 SB 101000 base rt offset 6 5 5 16 Format: SB rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The least-significant byte of register rt is stored at the effective address. Operation: 32 T: vAddr ← ((offset15) 16 || offset15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS SD 31 26 25 Store Doubleword SD 16 15 0 21 20 SD 111111 base rt offset 6 5 5 16 Format: SD rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of general register rt are stored at the memory location specified by the effective address.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SDL SDL Store Doubleword Left (1/3) 31 26 25 21 20 16 15 0 SDL 101100 base rt offset 6 5 5 16 Format: SDL rt, offset (base) Description: This instruction can be used with the SDR instruction to store the contents of a register into eight consecutive bytes of memory, when the bytes cross a doubleword boundary.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SDL Store Doubleword Left (2/3) SDL An address error exception is not occurred that specify address is not located in doubleword boundary. This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: vAddr ← ((offset15) 48 || offset15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS SDL SDL Store Doubleword Left (3/3) Given a doubleword in a register and a doubleword in memory, the operation of SDL instruction is as follows: SDL Register A B C D E F G H Memory I J K L M N O P vAddr2..
APPENDIX A MIPS III INSTRUCTION SET DETAILS SDR SDR Store Doubleword Right (1/3) 31 26 25 21 20 16 15 0 SDR 101101 base rt offset 6 5 5 16 Format: SDR rt, offset (base) Description: This instruction can be used with the SDL instruction to store the contents of a register into eight consecutive bytes of memory, when the bytes cross a boundary between two doublewords.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SDR Store Doubleword Right (2/3) SDR An address error exception is not occurred that specify address is not located in doubleword boundary. This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: vAddr ← ((offset15) 48 || offset15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS SDR SDR Store Doubleword Right (3/3) Given a doubleword in a register and a doubleword in memory, the operation of SDR instruction is as follows: SDR Register A B C D E F G H Memory I J K L M N O P vAddr2..
APPENDIX A MIPS III INSTRUCTION SET DETAILS SH 31 26 25 Store Halfword SH 16 15 0 21 20 SH 101001 base rt offset 6 5 5 16 Format: SH rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form an unsigned effective address. The least-significant halfword of register rt is stored at the effective address. If the least-significant bit of the effective address is non-zero, an address error exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SLL SLL Shift Left Logical 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa SLL 000000 6 5 5 5 5 6 Format: SLL rd, rt, sa Description: The contents of general register rt are shifted left by sa bits, inserting zeros into the low-order bits. The result is placed in register rd. In 64-bit mode, the 32-bit result is sign-extended when placed in the destination register.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SLLV SLLV Shift Left Logical Variable 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SLLV 000100 6 5 5 5 5 6 Format: SLLV rd, rt, rs Description: The contents of general register rt are shifted left the number of bits specified by the low-order five bits contained in general register rs, inserting zeros into the low-order bits. The result is placed in register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SLT SLT Set On Less Than 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SLT 101010 6 5 5 5 5 6 Format: SLT rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs. Considering both quantities as signed integers, if the contents of general register rs are less than the contents of general register rt, the result is set to one; otherwise the result is set to zero.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SLTI SLTI Set On Less Than Immediate 31 26 25 21 20 16 15 0 SLTI 001010 rs rt immediate 6 5 5 16 Format: SLTI rt, rs, immediate Description: The 16-bit immediate is sign-extended and subtracted from the contents of general register rs. Considering both quantities as signed integers, if rs is less than the sign-extended immediate, the result is set to 1; otherwise the result is set to 0. No integer overflow exception occurs under any circumstances.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SLTIU Set On Less Than Immediate Unsigned 31 26 25 21 20 16 15 SLTIU 0 SLTIU 001011 rs rt immediate 6 5 5 16 Format: SLTIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and subtracted from the contents of general register rs. Considering both quantities as unsigned integers, if rs is less than the sign-extended immediate, the result is set to 1; otherwise the result is set to 0.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SLTU SLTU Set On Less Than Unsigned 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SLTU 101011 6 5 5 5 5 6 Format: SLTU rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SRA SRA Shift Right Arithmetic 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa SRA 000011 6 5 5 5 5 6 Format: SRA rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, sign-extending the high-order bits. The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SRAV SRAV Shift Right Arithmetic Variable 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SRAV 000111 6 5 5 5 5 6 Format: SRAV rd, rt, rs Description: The contents of general register rt are shifted right by the number of bits specified by the low-order five bits of general register rs, sign-extending the high-order bits. The result is placed in register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SRL SRL Shift Right Logical 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 0 00000 rt rd sa SRL 000010 6 5 5 5 5 6 Format: SRL rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, inserting zeros into the high-order bits. The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value. Operation: 32 T: GPR [rd] ← 0 64 T: s ← 0 || sa sa || GPR [rt] 31...
APPENDIX A MIPS III INSTRUCTION SET DETAILS SRLV SRLV Shift Right Logical Variable 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SRLV 000110 6 5 5 5 5 6 Format: SRLV rd, rt, rs Description: The contents of general register rt are shifted right by the number of bits specified by the low-order five bits of general register rs, inserting zeros into the high-order bits. The result is placed in register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS STANDBY 31 Standby 26 25 24 STANDBY 6 5 0 COP0 010000 CO 1 0 000 0 000 0000 0000 0000 STANDBY 100001 6 1 19 6 Format: STANDBY Description: STANDBY instruction starts mode transition from Fullspeed mode to Standby mode. When the STANDBY instruction finishes the WB stage, this processor wait by the SysAD bus is idle state, after then the internal clocks will shut down, thus freezing the pipeline.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SUB SUB Subtract 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SUB 100010 6 5 5 5 5 6 Format: SUB rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result. The result is placed into general register rd. In 64-bit mode, the operands must be valid sign-extended, 32-bit values.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SUBU SUBU Subtract Unsigned 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 SUBU 100011 6 5 5 5 5 6 Format: SUBU rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result. The result is placed into general register rd. In 64-bit mode, the operands must be valid sign-extended, 32-bit values.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SUSPEND Suspend 26 25 24 31 COP0 010000 CO 6 1 1 SUSPEND 6 5 000 0 0000 0000 0000 0000 0 SUSPEND 100010 19 6 Format: SUSPEND Description: SUSPEND instruction starts mode transition from Fullspeed mode to Suspend mode. When the SUSPEND instruction finishes the WB stage, this processor wait by the SysAD bus is idle state, after then the internal clocks including the TClock will shut down, thus freezing the pipeline.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SW SW Store Word 31 26 25 21 20 16 15 0 SW 101011 base rt offset 6 5 5 16 Format: SW rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of general register rt are stored at the memory location specified by the effective address.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SWL SWL Store Word Left (1/3) 31 26 25 21 20 16 15 0 SWL 101010 base rt offset 6 5 5 16 Format: SWL rt, offset (base) Description: This instruction can be used with the SWR instruction to store the contents of a register into four consecutive bytes of memory, when the bytes cross a word boundary.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SWL Store Word Left (2/3) SWL Operation: 32 T: vAddr ← ((offset15) 16 || offset15...0) + GPR [base] (pAddr, uncached) ← AddressTranslation (vAddr, DATA) 3 pAddr ← pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 0 then 2 pAddr ← pAddrPSIZE - 1...2 || 0 endif byte ← vAddr1...0 xor BigEndianCPU 2 if (vAddr 2 xor BigEndianCPU) = 0 then data ← 0 32 data ← 0 24 – 8 * byte || 0 24 – 8 * byte || GPR [rt]31...
APPENDIX A MIPS III INSTRUCTION SET DETAILS SWL SWL Store Word Left (3/3) Given a doubleword in a register and a doubleword in memory, the operation of SWL is as follows: SWL Register A B C D E F G H Memory I J K L M N O P vAddr2..
APPENDIX A MIPS III INSTRUCTION SET DETAILS SWR SWR Store Word Right (1/3) 31 26 25 21 20 16 15 0 SWR 101110 base rt offset 6 5 5 16 Format: SWR rt, offset (base) Description: This instruction can be used with the SWL instruction to store the contents of a register into four consecutive bytes of memory, when the bytes cross a boundary between two words.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SWR Store Word Right (2/3) Operation: 32 T: vAddr ← ((offset15) 16 || offset15...0) + GPR [base] (pAddr, uncached) ← AddressTranslation (vAddr, DATA) 3 pAddr ← pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian ) if BigEndianMem = 1 then 2 pAddr ← pAddrPSIZE - 1...2 || 0 endif byte ← vAddr1...0 xor BigEndianCPU 2 if (vAddr 2 xor BigEndianCPU) = 0 then data ← 0 32 || GPR [rt]31 – 8 * byte...
APPENDIX A MIPS III INSTRUCTION SET DETAILS SWR SWR Store Word Right (3/3) Given a doubleword in a register and a doubleword in memory, the operation of SWR instruction is as follows: SWR Register A B C D E F G H Memory I J K L M N O P vAddr2..
APPENDIX A MIPS III INSTRUCTION SET DETAILS SYNC SYNC Synchronize 31 26 25 SPECIAL 000000 6 6 5 0000 0000 0 0000 0000 0000 20 0 SYNC 001111 6 Format: SYNC Description: The SYNC instruction is executed as a NOP on the VR4121. This operation maintains compatibility with code compiled for the VR4000. This instruction is defined to maintain the compatibility with VR4000 and VR4400.
APPENDIX A MIPS III INSTRUCTION SET DETAILS SYSCALL 31 System Call 26 25 SYSCALL 6 5 0 SPECIAL 000000 Code SYSCALL 001100 6 20 6 Format: SYSCALL Description: A system call exception occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TEQ TEQ Trap If Equal 31 26 25 21 20 16 15 0 6 5 SPECIAL 000000 rs rt code TEQ 110100 6 5 5 10 6 Format: TEQ rs, rt Description: The contents of general register rt are compared to general register rs. If the contents of general register rs are equal to the contents of general register rt, a trap exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TEQI TEQI Trap If Equal Immediate 31 26 25 21 20 16 15 0 REGIMM 000001 rs TEQI 01100 immediate 6 5 5 16 Format: TEQI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. If the contents of general register rs are equal to the sign-extended immediate, a trap exception occurs. Operation: 32 T: if GPR [rs] = (immediate15)16 || immediate15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS TGE TGE Trap If Greater Than Or Equal 31 26 25 21 20 6 5 16 15 0 SPECIAL 000000 rs rt code TGE 110000 6 5 5 10 6 Format: TGE rs, rt Description: The contents of general register rt are compared to the contents of general register rs. Considering both quantities as signed integers, if the contents of general register rs are greater than or equal to the contents of general register rt, a trap exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TGEI Trap If Greater Than Or Equal Immediate 31 26 25 21 20 16 15 TGEI 0 REGIMM 000001 rs TGEI 01000 immediate 6 5 5 16 Format: TGEI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. Considering both quantities as signed integers, if the contents of general register rs are greater than or equal to the sign-extended immediate, a trap exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TGEIU Trap If Greater Than Or Equal Immediate Unsigned 31 26 25 21 20 16 15 TGEIU 0 REGIMM 000001 rs TGEIU 01001 immediate 6 5 5 16 Format: TGEIU rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. Considering both quantities as unsigned integers, if the contents of general register rs are greater than or equal to the sign-extended immediate, a trap exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TGEU Trap If Greater Than Or Equal Unsigned 31 26 25 21 20 16 15 TGEU 0 6 5 SPECIAL 000000 rs rt code TGEU 110001 6 5 5 10 6 Format: TGEU rs, rt Description: The contents of general register rt are compared to the contents of general register rs. Considering both quantities as unsigned integers, if the contents of general register rs are greater than or equal to the contents of general register rt, a trap exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TLBP TLBP Probe TLB For Matching Entry 26 25 24 31 COP0 010000 CO 1 6 1 6 5 000 0000 0 0000 0000 0000 19 0 TLBP 001000 6 Format: TLBP Description: The Index register is loaded with the address of the TLB entry whose contents match the contents of the EntryHi register. If no TLB entry matches, the high-order bit of the Index register is set.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TLBR TLBR Read Indexed TLB Entry 26 25 24 31 COP0 010000 CO 1 6 1 6 5 000 0000 0 0000 0000 0000 19 0 TLBR 000001 6 Format: TLBR Description: The EntryHi and EntryLo registers are loaded with the contents of the TLB entry pointed at by the contents of the TLB Index register. The G bit (which controls ASID matching) read from the TLB is written into both of the EntryLo0 and EntryLo1 registers.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TLBWI 26 25 24 31 TLBWI Write Indexed TLB Entry COP0 010000 CO 1 6 1 6 5 000 0000 0 0000 0000 0000 19 0 TLBWI 000010 6 Format: TLBWI Description: The TLB entry pointed at by the contents of the TLB Index register is loaded with the contents of the EntryHi and EntryLo registers. The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TLBWR 26 25 24 31 TLBWR Write Random TLB Entry COP0 010000 CO 1 6 1 6 5 000 0000 0 0000 0000 0000 19 0 TLBWR 000110 6 Format: TLBWR Description: The TLB entry pointed at by the contents of the TLB Random register is loaded with the contents of the EntryHi and EntryLo registers. The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers. Operation: 32, 64 T: TLB [Random 5...
APPENDIX A MIPS III INSTRUCTION SET DETAILS TLT TLT Trap If Less Than 31 26 25 21 20 6 5 16 15 0 SPECIAL 000000 rs rt code TLT 110010 6 5 5 10 6 Format: TLT rs, rt Description: The contents of general register rt are compared to general register rs. Considering both quantities as signed integers, if the contents of general register rs are less than the contents of general register rt, a trap exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TLTI TLTI Trap If Less Than Immediate 31 26 25 21 20 16 15 0 REGIMM 000001 rs TLTI 01010 immediate 6 5 5 16 Format: TLTI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. Considering both quantities as signed integers, if the contents of general register rs are less than the sign-extended immediate, a trap exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TLTIU Trap If Less Than Immediate Unsigned 31 26 25 21 20 16 15 TLTIU 0 REGIMM 000001 rs TLTIU 01011 immediate 6 5 5 16 Format: TLTIU rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. Considering both quantities as unsigned integers, if the contents of general register rs are less than the sign-extended immediate, a trap exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TLTU TLTU Trap If Less Than Unsigned 31 26 25 21 20 6 5 16 15 0 SPECIAL 000000 rs rt code TLTU 110011 6 5 5 10 6 Format: TLTU rs, rt Description: The contents of general register rt are compared to general register rs. Considering both quantities as unsigned integers, if the contents of general register rs are less than the contents of general register rt, a trap exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TNE TNE Trap If Not Equal 31 26 25 21 20 6 5 16 15 0 SPECIAL 000000 rs rt code TNE 110110 6 5 5 10 6 Format: TNE rs, rt Description: The contents of general register rt are compared to general register rs. If the contents of general register rs are not equal to the contents of general register rt, a trap exception occurs.
APPENDIX A MIPS III INSTRUCTION SET DETAILS TNEI TNEI Trap If Not Equal Immediate 31 26 25 21 20 16 15 0 REGIMM 000001 rs TNEI 01110 immediate 6 5 5 16 Format: TNEI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs. If the contents of general register rs are not equal to the sign-extended immediate, a trap exception occurs. Operation: 32 T: if GPR [rs] ≠ (immediate15)16 || immediate15...
APPENDIX A MIPS III INSTRUCTION SET DETAILS XOR XOR Exclusive Or 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 000000 rs rt rd 0 00000 XOR 100110 6 5 5 5 5 6 Format: XOR rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical exclusive OR operation. The result is placed into general register rd.
APPENDIX A MIPS III INSTRUCTION SET DETAILS XORI XORI Exclusive OR Immediate 31 26 25 21 20 16 15 0 XORI 001110 rs rt immediate 6 5 5 16 Format: XORI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical exclusive OR operation. The result is placed into general register rt.
APPENDIX A MIPS III INSTRUCTION SET DETAILS A.6 CPU Instruction Opcode Bit Encoding Figure A-1 lists the VR4120A Opcode Bit Encoding. Figure A-1. VR4120A Opcode Bit Encoding (1/2) Opcode 28...26 31...
APPENDIX A MIPS III INSTRUCTION SET DETAILS Figure A-1. VR4120AOpcode Bit Encoding (2/2) COP0 rs 23...21 25, 24 0 1 2 3 4 5 6 7 0 MF DMFε γ γ MT DMTε γ γ 1 BC γ γ γ γ γ γ γ 4 5 6 7 2 CO 3 COP0 rt 18...16 20...19 0 1 2 3 0 BCF BCT BCFL BCTL γ γ γ γ 1 γ γ γ γ γ γ γ γ 2 γ γ γ γ γ γ γ γ 3 γ γ γ γ γ γ γ γ 5...
APPENDIX B VR4120A COPROCESSOR 0 HAZARDS The VR4120A core avoids contention of its internal resources by causing a pipeline interlock in such cases as when the contents of the destination register of an instruction are used as a source in the succeeding instruction. Therefore, instructions such as NOP must not be inserted between instructions. However, interlocks do not occur on the operations related to the CP0 registers and the TLB.
APPENDIX B VR4120A COPROCESSOR 0 HAZARDS Table B-1. VR4120A CPU Coprocessor 0 Hazards Operation Source Destination Source Name No. of Cycles MTC0 Destination Name No. of Cycles cpr rd 5 MFC0 cpr rd 3 TLBR Index, TLB 2 PageMask, EntryHi, EntryLo0, EntryLo1 5 TLBWI TLBWR Index or Random, PageMask, EntryHi, EntryLo0, EntryLo1 2 TLB 5 TLBP PageMask, EntryHi 2 Index 6 ERET EPC or ErrorEPC, TLB 2 Status.EXL, Status.
APPENDIX B VR4120A COPROCESSOR 0 HAZARDS Remarks 1. The instruction following MTC0 must not be MFC0. 2. The five instructions following MTC0 to Status register that changes KSU and sets EXL and ERL may be executed in the new mode, and not kernel mode. This can be avoided by setting EXL first, leaving KSU set to kernel, and later changing KSU. 3. There must be two non-load, non-CACHE instructions between a store and a CACHE instruction directed to the same primary cache line as the store.
APPENDIX B VR4120A COPROCESSOR 0 HAZARDS (10) Instruction Fetch Source: The confirmation of the operating mode and TLB necessary for instruction fetch. Examples 1. When changing the operating mode from User to Kernel and fetching instructions after the KSU, EXL, and ERL bits of the Status register are modified. 2. When fetching instructions using the modified TLB entry after TLB modification.
APPENDIX B VR4120A COPROCESSOR 0 HAZARDS Table B-2 indicates examples of calculation. Table B-2.
Facsimile Message From: Name Company Tel. Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. FAX Address Thank you for your kind support.