Server Technical Overview

Memory
2-6
Each channel pair operates in lockstep; that is, a single cache line is stored across
two DIMMs with each DIMM on a different channel of the lockstep pair.
y Eight fully buffered DIMM slots for each channel. A cell with two memory boards
contains 32 DIMM slots.
y Double Data Rate 2 533-MHz and 667-MHz fully buffered DIMMs (single, dual, or
quad rank).
y DIMM capacities of 2 GB or 4 GB.
y Hot-add memory (requires operating system support).
Figure 2-4
shows the channels, channel pairs and fully buffered DIMMs on the memory
boards.
Figure 2-4 Memory Boards
DIMM Slot Numbering
Figure 2-5 shows the numbering of the DIMM slots on the memory board relative to their
physical layout on the board.