MAY 2004 CP3BT26 Reprogrammable Connectivity Processor with Bluetooth®, USB, and CAN Interfaces 1.0 General Description The CP3BT26 connectivity processor combines high performance with the massive integration needed for embedded Bluetooth applications. A powerful RISC core with on-chip SRAM and Flash memory provides high computing bandwidth, hardware communications peripherals provide highI/O bandwidth, and an external bus provides system expandability.
CP3BT26 Table of Contents 1.0 2.0 3.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 4.0 5.0 Operating Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface Unit (BIU) . . .
Power-down modes Features Flexible I/O CPU Features Fully static RISC processor core, capable of operating Up to 54 general-purpose I/O pins (shared with on-chip peripheral I/O) from 0 to 24 MHz with zero wait/hold states Programmable I/O pin characteristics: TRI-STATE out Minimum 41.
CP3BT26 3.0 Device Overview The CP3BT26 connectivity processor is a complete microcomputer with all system timing, interrupt logic, program memory, data memory, and I/O ports included on-chip, making it well-suited to a wide range of embedded applications. The block diagram on page 1 shows the major on-chip components of the CP3BT26 devices. 3.1 3.3 The device has up to 54 software-configurable I/O pins, organized into seven ports called Port B, Port C, Port E, Port G, Port H, Port I, and Port J.
BLUETOOTH LLC 3.11 ADVANCED AUDIO INTERFACE The integrated hardware Bluetooth Lower Link Controller The audio interface provides a serial synchronous, full-du(LLC) complies to the Bluetooth Specification Version 1.1 plex interface to CODECs and similar serial devices. Transand integrates the following functions: mit and receive paths operate asynchronously with respect to each other. Each path uses three signals for communica 4.
CP3BT26 3.14 RANDOM NUMBER GENERATOR 3.18 TIMING AND WATCHDOG MODULE RNG peripheral for use in Trusted Computer Peripheral Applications (TCPA) to improve the authenticity, integrity, and privacy of Internet-based communication and commerce. The Timing and Watchdog Module (TWM) contains a RealTime timer and a Watchdog unit. The Real-Time Clock Timing function can be used to generate periodic real-time based system interrupts. The timer output is one of 16 in3.
POWER MANAGEMENT In the normal mode of operation, the interface only transfers one word at a periodic rate. In the network mode, the interface transfers multiple words at a periodic rate. The periodic rate is also called a data frame and each word within one frame is called a slot. The beginning of each new data frame is marked by the frame sync signal.
CP3BT26 4.0 Signal Descriptions X1CKI/BBCLK X1CKO 12 MHz Crystal or Ext. Clock 8 8 1 1 1 1 6 6 15 14 Chip Reset JTAG I/F to Debugger/ Programmer Mode Selection RF/MFT ADC/ Touchscreen ACCESS.bus CAN Bus/MIWU CAN Bus USB AVCC AGND ADVCC ADGND VCC GND IOVCC IOGND RESET TMS TDI TDO TCK RDY ENV0 ENV1 ENV2 X1CKI/BBCLK X1CKO 12 MHz Crystal GPIO or Ext. Clock X2CKI X2CKO 32.768 kHz Crystal Power Supply PB[7:0] PC[7:0] X2CKI X2CKO 32.
I/O Alternate Name Name Pins Primary Function X1CKI 1 Input 12 MHz Oscillator Input BBCLK BB reference clock for the RF Interface X1CKO 1 Output 12 MHz Oscillator Output None None X2CKI 1 Input 32 kHz Oscillator Input None None X2CKO 1 Output 32 kHz Oscillator Output None None RESET 1 Input Chip general reset None None ENV0 1 I/O Special mode select input with internal pull-up during reset PLLCLK PLL Clock Output ENV1 1 I/O Special mode select input with internal
CP3BT26 ADC3 1 I/O ADC Input Channel 3 TSY- Touchscreen Y- contact ADC4 1 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplexer Output 0 ADC5 1 I/O ADC Input Channel 5 MUXOUT1 Analog Multiplexer Output 1 ADC6 1 Input ADC Input Channel 6 None None ADC7 1 Input ADC Input Channel 7 ADCIN ADC Input (in MUX mode) VREFP 1 Input ADC Positive Voltage Reference None None PB[7:0] 8 I/O Generic I/O None None PC[7:0] 8 I/O Generic I/O None None PE0 1 I/O Generic I/O RXD
Pins PG4 1 I/O Generic I/O SDAT BT Serial I/F Data PG5 1 I/O Generic I/O SLE BT Serial I/F Load Enable Output WUI10 Multi-Input Wake-Up Channel 10 PG6 1 I/O Generic I/O BTSEQ2 Bluetooth Sequencer Status TA Multi Function Timer Port A PG7 1 BTSEQ3 Bluetooth Sequencer Status RXD1 UART Channel 1 Receive Data Input PH0 1 WUI11 Multi-Input Wake-Up Channel 11 TXD1 UART Channel 1 Transmit Data Output PH1 1 WUI12 Multi-Input Wake-Up Channel 12 RXD2 UART Channel 2 Receive Data
CP3BT26 Table 3 CP3BT26 LQFP-144 Signal Descriptions Pins X1CKI 1 Input 12 MHz Oscillator Input BBCLK BB reference clock for the RF Interface X1CKO 1 Output 12 MHz Oscillator Output None None X2CKI 1 Input 32 kHz Oscillator Input None None X2CKO 1 Output 32 kHz Oscillator Output None None RESET 1 Input Chip general reset None None ENV0 1 I/O Special mode select input with internal pull-up during reset PLLCLK PLL Clock Output ENV1 1 I/O Special mode select input with
Pins ADC3 1 I/O ADC Input Channel 3 TSY- Touchscreen Y- contact ADC4 1 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplexer Output 0 ADC5 1 I/O ADC Input Channel 5 MUXOUT1 Analog Multiplexer Output 1 ADC6 1 Input ADC Input Channel 6 None None ADC7 1 Input ADC Input Channel 7 ADCIN ADC Input (in MUX mode) VREFP 1 Input ADC Positive Voltage Reference None None PB[7:0] 8 I/O Generic I/O D[7:0] External Data Bus Bits 0 to 7 PC[7:0] 8 I/O Generic I/O D[8:15] External
CP3BT26 Name Pins I/O PF6 1 PF7 1 PG0 1 I/O PG1 1 PG2 1 PG3 1 I/O PG4 1 PG5 Alternate Name Primary Function Alternate Function STD AAI Transmit Data Output TIO7 Versatile Timer Channel 7 SRD AAI Receive Data Input TIO8 Versatile Timer Channel 8 Generic I/O RFSYNC BT AC Correlation/TX Enable Output I/O Generic I/O RFCE BT RF Chip Enable Output BTSEQ1 Bluetooth Sequencer Status I/O Generic I/O SRCLK AAI Receive Clock Generic I/O SCLK BT Serial I/F Shift Clock Outp
CPU Architecture The CP3BT26 uses the CR16C third-generation 16-bit CompactRISC processor core. The CPU implements a Reduced Instruction Set Computer (RISC) architecture that allows an effective execution rate of up to one instruction per clock cycle. For a detailed description of the CPU16C architecture, see the CompactRISC CR16C Programmer’s Reference Manual which is available on the National Semiconductor web site (http://www.nsc.com).
CP3BT26 5.2.4 Interrupt Base Register (INTBASE) N The INTBASE register holds the address of the dispatch table for exceptions. The dispatch table can be located anywhere in the CPU address space. When loading the INTBASE register, bits 31 to 24 and bit 0 must written with 0. 5.3 PROCESSOR STATUS REGISTER (PSR) E The PSR provides state information and controls operating modes for the CPU. The format of the PSR is shown below.
CP3BT26 5.4 CONFIGURATION REGISTER (CFG) The CFG register is used to enable or disable various operating modes and to control optional on-chip caches. Because the CP3BT26 does not have cache memory, the cache control bits in the CFG register are reserved. All CFG bits are cleared on reset. 15 10 9 Reserved ED SR 8 7 6 SR ED 0 0 5 2 Reserved 1 0 0 0 The Extended Dispatch bit selects whether the size of an entry in the interrupt dispatch table (IDT) is 16 or 32 bits.
CP3BT26 5.5 ADDRESSING MODES The CR16C CPU core implements a load/store architecture, in which arithmetic and logical instructions operate on register operands. Memory operands are made accessible in registers using load and store instructions. For efficient implementation of I/O-intensive embedded applications, the architecture also provides a set of bit operations that operate on memory operands.
STACKS 5.7 A stack is a last-in, first-out data structure for dynamic storage of data and addresses. A stack consists of a block of memory used to hold the data and a pointer to the top of the stack. As more data is pushed onto a stack, the stack grows downward in memory. The CR16C supports two types of stacks: the interrupt stack and program stacks. INSTRUCTION SET Table 4 lists the operand specifiers for the instruction set, and Table 5 is a summary of all instructions.
CP3BT26 Table 5 Instruction Set Summary Mnemonic Operands Description MOVi Rsrc/imm, Rdest Move MOVXB Rsrc, Rdest Move with sign extension MOVZB Rsrc, Rdest Move with zero extension MOVXW Rsrc, RPdest Move with sign extension MOVZW Rsrc, RPdest Move with zero extension MOVD imm, RPdest Move immediate to register-pair RPsrc, RPdest Move between register-pairs ADD[U]i Rsrc/imm, Rdest Add ADDCi Rsrc/imm, Rdest Add with carry ADDD RPsrc/imm, RPdest Add with RP or immediate.
CP3BT26 Table 5 Instruction Set Summary Mnemonic Operands Description ASHUD Rsrc/imm, RPdest Arithmetic left/right shift LSHi Rsrc/imm, Rdest Logical left/right shift LSHD Rsrc/imm, RPdest Logical left/right shift SBITi Iposition, disp(Rbase) Set a bit in memory (Because this instruction treats the destination as a readmodify-write operand, it not be used to set bits in writeonly registers.
CP3BT26 Table 5 Instruction Set Summary Mnemonic Operands Description RETX Return from exception PUSH imm, Rsrc, RA Push “imm” number of registers on user stack, starting with Rsrc and possibly including RA POP imm, Rdest, RA Restore “imm” number of registers from user stack, starting with Rdest and possibly including RA POPRET imm, Rdest, RA Restore registers (similar to POP) and JUMP RA LOADi disp(Rbase), Rdest Load (register relative) abs, Rdest Load (absolute) (Rindex)abs, Rdest Loa
Mnemonic STORMP Operands Description imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R7,R6) DI Disable maskable interrupts EI Enable maskable interrupts EIWAIT Enable maskable interrupts and wait for interrupt NOP No operation WAIT Wait for interrupt 23 www.national.
CP3BT26 6.0 Memory The CP3BT26 supports a uniform 16M-byte linear address space. Table 6 lists the types of memory and peripherals that occupy this memory space. Unlisted address ranges Table 6 6.1 are reserved and must not be read or written. The BIU zones are regions of the address space that share the same control bits in the Bus Interface Unit (BIU).
Table 7 Operating Environment Selection ENV[2:0] EMPTY 6.2 The BIU has a set of control registers that determine how many wait cycles and hold cycles are to be used for accessing memory. During initialization of the system, these registers should be programmed with appropriate values so that the minimum allowable number of cycles is used. This number varies with the clock frequency.
CP3BT26 6.4.2 I/O Zone Configuration Register (IOCFG) 6.4.3 The IOCFG register is a word-wide, read/write register that controls the timing and bus characteristics of accesses to the 256-byte I/O Zone memory space (FF FB00h to FF FBFFh). The registers associated with Port B and Port C reside in the I/O memory array. At reset, the register is initialized to 069Fh. The register format is shown below.
6.4.4 The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a different zone. No idle cycles are required for onchip accesses. 0 – No idle cycle (recommended). 1 – Idle cycle inserted. At reset, the register is initialized to 069Fh. The register format is shown below.
CP3BT26 FRE IPST IPRE The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. 0 – Normal read cycles. 1 – Fast read cycles. The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. 0 – No idle cycle. 1 – Idle cycle inserted.
System Configuration Registers The system configuration registers control and provide status for certain aspects of device setup and operation, such as indicating the states sampled from the ENV[2:0] inputs. The system configuration registers are listed in Table 9. Table 9 System Configuration Registers Name Address Description MCFG FF F910h Module Configuration Register MSTAT FF F914h Module Status Register 7.
CP3BT26 7.2 MODULE STATUS REGISTER (MSTAT) 7.3 SOFTWARE RESET REGISTER (SWRESET) The MSTAT register is a byte-wide, read-only register that indicates the general status of the device. The MCFG regis- The SWRESET register is a byte-wide, write-only register ter format is shown below. which provides a mechanism for software to initiate a reset into ISP mode without regard to the status of the EMPTY bits in the flash protection word.
Flash Memory The flash memory consists of the flash program memory and the flash data memory. The flash program memory is further divided into the Boot Area and the Code Area. default (after reset) all bits in the FM0WER, FM1WER, and FSM0WER registers are cleared, which disables write access by the CPU to all sections. Write access to a section is A special protection scheme is applied to the lower portion enabled by setting the corresponding write enable bit.
CP3BT26 8.2.1 Main Block 0 and 1 8.2.4 Main Block 0 and Main Block 1 hold the 256K-byte program space, which consists of the Boot Area and Code Area. Each block consists of sixteen 8K-byte sections. Write access by the CPU to Main Block 0 and Main Block 1 is controlled by the corresponding bits in the FM0WER and FM1WER registers, respectively. The least significant bit in each register controls the section at the lowest address. 8.2.
Main Block Page Erase 8.3.6 A flash erase operation sets all of the bits in the erased region. Pages of a main block can be individually erased if their write enable bits are set. This method cannot be used to erase the boot area, if defined. Each page in Main Block 0 and 1 consists of 1024 bytes (512 words). Each page in Main Block 2 consists of 512 bytes (256 words). To erase a page, the following steps are performed: Writing is only allowed when global write protection is disabled.
CP3BT26 8.4 INFORMATION BLOCK WORDS Table 14 lists all possible boot area encodings. Two words in the information blocks are dedicated to hold settings that affect the operation of the system: the Function Word in Information Block 0 and the Protection Word in Information Block 1.
EMPTY Not Empty Not Empty Not Empty ISPE Boot Area Start-Up Operation ISP Defined Device starts in IRE/ ERE mode from Code Area start address ISP Not Defined Device starts in IRE/ ERE mode from Code Area start address No ISP Device starts in IRE/ Don’t Care ERE mode from address 0 Empty ISP Defined Empty ISP Not Defined Empty No ISP Don’t Care RDPROT WRPROT 8.
CP3BT26 8.5.1 Flash Memory Information Block Address Register (FMIBAR/FSMIBAR) 8.5.3 The FMIBAR register specifies the 8-bit address for read or write access to an information block. Because only word access to the information blocks is supported, the least significant bit (LSB) of the FMIBAR must be 0 (word-aligned). The hardware automatically clears the LSB, without regard to the value written to the bit. The FMIBAR register is cleared after device reset.
Flash Data Memory 0 Write Enable Register (FSM0WER) DISVRF The FSM0WER register controls write protection for the flash data memory. The data block is divided into 16 512byte sections. Each bit in the FSM0WER register controls write protection for one of these sections. The FSM0WER register is cleared after device reset, so the flash memory is write protected after reset. The CPU bus master has read/ write access to this registers. 15 IENPROG 0 FSM0WE FSM0WEn 8.5.
CP3BT26 8.5.7 DERR Flash Memory Status Register (FMSTAT/ FSMSTAT) The Data Loss Error bit indicates that a buffer overrun has occurred during a programming sequence. After a data loss error occurs, software can clear the DERR bit by writing a 1 to it. Writing a 0 to the DERR bit has no effect. Software must not change this bit while the flash program memory is busy being programmed or erased. 0 – No data loss error occurred. 1 – Data loss error occurred.
Flash Memory Transition Time Reload Register (FMTRAN/FSMTRAN) 8.5.13 The FMTRAN/FMSTRAN register is a byte-wide read/write register that controls some program/erase transition times. Software must not modify this register while program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 30h if the flash memory is idle. The CPU bus master has read/write access to this register.
CP3BT26 8.5.16 8.5.18 Flash Memory Recovery Time Reload Register (FMRCV/FSMRCV) The FMRCV/FSMRCV register is a byte-wide read/write register that controls the recovery delay time between two flash memory accesses. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master has read/write access to this register.
DMA Controller The DMA Controller (DMAC) has a register-based programming interface, as opposed to an interface based on I/O control blocks. After loading the registers with source and destination addresses, as well as block size and type of operation, a DMAC channel is ready to respond to DMA transfer requests. A request can only come from on-chip peripherals or software, not external peripherals.
CP3BT26 Direct mode supports two bus policies: intermittent and continuous. In intermittent mode, the DMAC gives bus mastership back to the CPU after every cycle. In continuous mode, the DMAC remains bus master until the transfer is completed. The maximum bus throughput in intermittent mode is one transfer for every three System Clock cycles. The maximum bus throughput in continuous mode is one transfer for every clock cycle. The I/O device which made the DMA request is called the implied I/O device.
1. 2. 3. 4. The transfer operation terminates. The channel sets the DMASTAT.OVR bit. The DMASTAT.CHAC bit is cleared. An interrupt is generated if enabled DMACNTLn.EOVR bit. by the The DMACNTLn.CHEN bit must be cleared before loading the DMACNTLn register to avoid prematurely starting a new DMA transfer. For each channel, use the software DMA transfer request only when the corresponding hardware DMA request is inactive and no terminal count interrupt is pending. Software can poll the DMASTAT.
CP3BT26 9.6.2 Table 18 DMA Controller Registers Name Address Description ADCA2 FF F840h Device A Address Counter Register ADRA2 FF F844h Device A Address Register ADCB2 FF F848h Device B Address Counter Register ADRB2 FF F84Ch Device B Address Register Device A Address Register (ADRAn) The Device A Address register is a 32-bit, read/write register.
Block Length Register (BLTRn) DIR The Block Length register is a 16-bit, read/write register. It holds the number of DMA transfers to be performed for the next block. Writing this register automatically sets the DMASTAT.VLD bit. 15 0 OT Block Length Note: 0000h is interpreted as 216-1 transfer cycles. 9.6.7 DMA Control Register (DMACNTLn) BPC The DMA Control register n is a word-wide, read/write register that controls the operation of DMA channel n. This register is cleared at reset.
CP3BT26 9.6.8 DMA Status Register (DMASTAT) The DMA status register is a byte-wide, read register that holds the status information for the DMA channel n. This register is cleared at reset. The reserved bits always return zero when read. The VLD, OVR and TC bits are sticky (once set by the occurrence of the specific condition, they remain set until explicitly cleared by software). These bits can be individually cleared by writing 1 to the bit positions in the DMASTAT register to be cleared.
The Interrupt Control Unit (ICU) receives interrupt requests from internal and external sources and generates interrupts to the CPU. Interrupts from the timers, UARTs, Microwire/ SPI interface, and Multi-Input Wake-Up module are all maskable interrupts. The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is triggered by a falling edge received on the NMI input pin. 10.2.1 10.1 would seem that the interrupt vector would never return the value 10h.
CP3BT26 10.3.1 Interrupt Vector Register (IVCT) 10.3.3 The IVCT register is a byte-wide read-only register which reports the encoded value of the highest priority maskable interrupt that is both asserted and enabled. The valid range is from 10h to 3Fh. The register is read by the CPU during an interrupt acknowledge bus cycle, and INTVECT is valid during that time. It may contain invalid data while INTVECT is updated. 7 6 0 0 INTVECT 10.3.
Interrupt Enable and Mask Register 0 (IENAM0) The IENAM0 register is a word-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ1 through IRQ15. The register is initialized to FFFFh at reset. 15 1 IENA IENA 10.3.5 15 Res. Interrupt Enable and Mask Register 1 (IENAM1) IST 10.3.8 The Interrupt Status bits indicate if a maskable interrupt source is signalling an interrupt request. IST15:1 correspond to IRQ15 to IRQ1 respectively.
CP3BT26 10.4 MASKABLE INTERRUPT SOURCES Table 20 shows the interrupts assigned to various on-chip maskable interrupts. The priority of simultaneous maskable interrupts is linear, with IRQ47 having the highest priority.
The Triple Clock and Reset module generates a 12 MHz Main Clock and a 32.768 kHz Slow Clock from external crystal networks or external clock sources. It provides various clock signals for the rest of the chip. It also provides the main system reset signal, a power-on reset function, Main Clock prescalers to generate two additional low-speed clocks, and a 32-kHz oscillator start-up delay. Figure 4 is block diagram of the Triple Clock and Reset module.
CP3BT26 11.1 EXTERNAL CRYSTAL NETWORK An external crystal network is connected to the X1CKI and X1CKO pins to generate the Main Clock, unless an external clock signal is driven on the X1CKI pin. A similar external crystal network may be used at pins X2CKI and X2CKO for the Slow Clock. If an external crystal network is not used for the Slow Clock, the Slow Clock is generated by dividing the fast Main Clock.
Component Crystal Parameters Resonance Frequency Type Maximum Serial Resistance Maximum Shunt Capacitance Load Capacitance Min. Q factor Capacitor C1, C2 Capacitance Choose capacitor component values in the tables to obtain the specified load capacitance for the crystal when combined with the parasitic capacitance of the trace, socket, and package (which can vary from 0 to 8 pF).
CP3BT26 11.5 SYSTEM CLOCK The System Clock drives most of the on-chip modules, including the CPU. Typically, it is driven by the Main Clock, but it can also be driven by the PLL. In either case, the clock signal is passed through a programmable divider (scale factors from ÷1 to ÷16). 11.6 rise time. The time constant also should exceed the stabilization time for the high-frequency oscillator. 11.9 Table 23 lists the clock and reset registers.
ACE1 ACE2 POR 11.9.2 Res 6 4 MODE 3 0 11.9.3 MODE Description 000 Reserved Reserved 001 Reserved Reserved 010 Reserved Reserved 011 36 MHz 3× Mode 100 48 MHz 4× Mode 101 60 MHz 5× Mode 110 Reserved Reserved 111 Reserved Reserved Low Frequency Clock Prescaler Register (PRSSC) The PRSSC register is a byte-wide read/write register that holds the clock divisor used to generate the Slow Clock from the Main Clock. The register is initialized to B6h at reset.
CP3BT26 12.0 Power Management The Power Management Module (PMM) improves the efficiency of the CP3BT26 by changing the operating mode (and therefore the power consumption) according to the required level of device activity. The device implements four power modes: * The Analog/Digital Converter (ADC) module is not automatically disabled by entering Halt mode, however its clock is stopped so no conversions may be performed in Halt mode.
IDLE MODE 12.6 POWER MANAGEMENT REGISTERS In Idle mode, the System Clock is disabled and therefore the Table 26 lists the power management registers. clock is stopped to most modules of the device. The PLL Table 26 Power Management Registers and the high-frequency oscillator may be disabled as controlled by register bits. The low-frequency oscillator remains Name Address Description active.
CP3BT26 HALT WBPSM DMC The Halt Mode bit indicates whether the de- DHC vice is in Halt mode. Before entering Halt mode, the WBPSM bit must be set. When the HALT bit is written with 1, the device enters the Halt mode at the execution of the next WAIT instruction. When in HALT mode, the PMM stops the System Clock and then turns off the PLL and the high-frequency oscillator. The HALT bit can be set and cleared by software. The Halt mode is exited by a hardware wake-up event.
12.7 Power Management Status Register (PMMSR) The Management Status Register (PMMR) is a byte-wide, read/write register that provides status signals for the various clocks. The reset value of PMSR register bits 0 to 2 depend on the status of the clock sources monitored by the PMM. The upper 5 bits are clear after reset. The format of the register is shown below.
CP3BT26 12.7.2 Entering Idle Mode 12.7.6 Entry into Idle mode is performed by writing a 1 to the PMMCR.IDLE bit and then executing a WAIT instruction. The PMMCR.WBPSM bit must be set before the WAIT instruction is executed. Idle mode can be entered only from the Active or Power Save mode. 12.7.3 Wake-Up Transition to Active Mode A hardware wake-up event switches the device directly from Power Save, Idle, or Halt mode to Active mode.
The Multi-Input Wake-Up (MIWU) unit consists of two identical 16-channel modules. Each module can assert a wakeup signal for exiting from a low-power mode, and each can assert an interrupt request on any of four Interrupt Control Unit (ICU) channels assigned to that module. The modules operate independently, so each may assert an interrupt request to the ICU. Together, these modules provide 32 MIWU input channels and 8 interrupt request outputs.
CP3BT26 13.1 Table 27 MIWU Sources MIWU Channel Source WUI0 TWM T0OUT WUI1 ACCESS.
13.1.4 Wake-Up Edge Detection Register (WK0EDG) The WK0EDG register is a word-wide read/write register that controls the edge sensitivity of the MIWU channels. The WK0EDG register is cleared upon reset, which configures all channels to be triggered on rising edges. The register format is shown below. 15 Wake-Up 1 Enable Register (WK1ENA) The WK1ENA register is a word-wide read/write register that individually enables or disables wake-up events from the MIWU channels.
CP3BT26 13.1.7 Wake-Up Interrupt Control Register 1 (WK0ICTL1) 13.1.9 Wake-Up Interrupt Control Register 2 (WK0ICTL2) The WK0ICTL1 register is a word-wide read/write register that selects the interrupt request signal for the associated MIWU channels WUI7:0. At reset, the WK0ICTL1 register is cleared, which selects MIWU Interrupt Request 0 for all eight channels. The register format is shown below.
13.1.13 Wake-Up Pending Clear Register (WK0PCL) The WK0PND register is a word-wide read/write register in which the Multi-Input Wake-Up module latches any detected trigger conditions. The CPU can only write a 1 to any bit position in this register. If the CPU attempts to write a 0, it has no effect on that bit. To clear a bit in this register, the CPU must use the WK0PCL register.
CP3BT26 13.2 PROGRAMMING PROCEDURES To set up and use the Multi-Input Wake-Up function, use the following procedure. Performing the steps in the order shown will prevent false triggering of a wake-up condition. This same procedure should be used following a reset because the wake-up inputs are left floating, resulting in unknown data on the input pins. 1. Clear the WK0ENA and WK1ENA registers to disable the MIWU channels. 2.
Each device has up to 54 software-configurable I/O pins, organized into 8-bit ports (not all bits are used in some ports). The ports are named Port B, Port C, Port E, Port F, Port G, Port H, and Port J. In addition to their general-purpose I/O capability, the I/O pins of Ports E, F, G, H, and J have alternate functions for use with on-chip peripheral modules such as the UART or the Multi-Input Wake-Up unit. The alternate functions of all I/O pins are shown in Table 94.
CP3BT26 Table 29 Port Registers Table 29 Port Registers Name PBALT Address FF FB00h Port B Direction Register PBDIN FF FB04h Port B Data Input Register PBDOUT FF FB06h Port B Data Output Register PBWPU FF FB08h Port B Weak Pull-Up Register PBHDRV FF FB0Ah Port B High Drive Strength Register FF FB0Ch Port B Alternate Function Select Register PCALT FF FB10h Port C Alternate Function Register PCDIR FF FB12h Port C Direction Register PCDIN FF FB14h Port C Data Input Register PCDOUT F
14.1.1 14.1.3 Port Data Input Register (PxDIN) The data input register (PxDIN) is a read-only register that returns the current state on each port pin. The CPU can read this register at any time even when the pin is configured as an output. Port Alternate Function Register (PxALT) 7 The PxALT registers control whether the port pins are used for general-purpose I/O or for their alternate function. Each port pin can be controlled independently.
CP3BT26 14.1.6 Port High Drive Strength Register (PxHDRV) Table 30 The PxHDRV register is a byte-wide, read/write register that controls the slew rate of the corresponding pins. The high drive strength function is enabled when the corresponding bits of the PxHDRV register are set. In both GPIO and alternate function modes, the drive strength function is enabled by the PxHDRV registers. At reset, the PxHDRV registers are cleared, making the ports low speed. 7 0 PxHDRV PxHDRV 14.1.
CP3BT26 14.2 OPEN-DRAIN OPERATION A port pin can be configured to operate as an inverting open-drain output buffer. To do this, the CPU must clear the bit in the data output register (PxDOUT) and then use the port direction register (PxDIR) to set the value of the port pin. With the direction register bit set (direction = out), the value zero is forced on the pin. With the direction register bit clear (direction = in), the pin is placed in the TRI-STATE mode.
CP3BT26 15.0 Bluetooth Controller The integrated hardware Bluetooth Lower Link Controller Figure 12 shows the interface between the CP3BT26 and (LLC) complies to the Bluetooth Specification Version 1.1 the LMX5252 radio chip. and integrates the following functions: +2.8V 4.5K-byte dedicated Bluetooth data RAM 1K-byte dedicated Bluetooth Sequencer RAM Support of all Bluetooth 1.
SCLK The SCLK signal is the serial interface shift clock output. The CP3BT26 always acts as the master of the serial interface and therefore always provides the shift clock. The SCLK signal is the alternate function of the general-purpose I/O pin PG3. At reset, this pin is in TRI-STATE mode. Software must enable the alternate function of the PG3 pin to give control over this signal to the RF interface.
CP3BT26 Write Operation When the R/W bit is clear, the 16 bits of the data field are shifted out of the CP3BT26 on the falling edge of SCLK. Data is sampled by the radio chip on the rising edge of SCLK. When SLE is high, the 16-bit data are copied into the radio chip register on the next rising edge of SCLK. The data is loaded in the appropriate radio chip register depending on the state of the four address bits, Address[4:0]. Figure 14 shows the timing for the write operation.
H2 H1 H0 W A4 A3 A2 A1 A0 D31 D30 D16 H2 H1 H0 W A4 A3 A2 A1 A0 D15 D14 CP3BT26 SDAT D0 SCLK >500 ns SLE DS322 Figure 18. 32-Bit Write Timing SDAT H2 H1 H0 R A4 A3 A2 A1 A0 D31 D16 H2 H1 H0 R A4 A3 A2 A1 A0 D15 D0 SCLK >500 ns SLE DS323 Figure 19. 32-Bit Read Timing An example of a 32-bit write is shown in Table 31. In this example, the 32-bit value FFFF DC04h is written to register address 0Ah. In cycle 1, the high word (FFFFh) is written.
CP3BT26 15.3 LMX5251 POWER-UP SEQUENCE 15.4 To power-up a Bluetooth system based on the CP3BT26 and LMX5251 devices, the following sequence must be performed: 1. Apply VDD to the LMX5251. 2. Apply IOVCC and VCC to the CP3BT26. 3. Drive the RESET# pin of the LMX5251 high a minimum of 2 ms after the LMX5251 and CP3000 supply rails are powered up. This resets the LMX5251 and CP3BT26. 4. After internal Power-On Reset (POR) of the CP3BT26, the RFDATA pin is driven high.
RESET RFDATA t5 t3 RFCE BBCLK BPOR t1 t2 B3k2 t4 SLE SCLK CPU SDAT DS321 Figure 22. 15.5 System Clock LMX5252 Power-Up Sequence HCC BLUETOOTH SLEEP MODE BT LCC Clock The Bluetooth controller is capable of putting itself into a sleep mode for a specified number of Slow Clock cycles. In this mode, the controller clocks are stopped internally. The only circuitry which remains active are two counters (counter N and counter M) running at the Slow Clock rate.
CP3BT26 15.8 BLUETOOTH SHARED DATA RAM The shared data RAM is a 4.5K memory-mapped section of RAM that contains the link control data, RF programming look-up table, and the link payload. This RAM can be read and written in the same way as the Static RAM space and can also be read by the sequencer in the Bluetooth LLC. Arbitration between these devices is performed in hardware. Table 33 shows the memory map of the Bluetooth LLC shared Data RAM.
CP3BT26 16.
CP3BT26 The output of the Input Multiplexer is available externally as the MUXOUT0 and MUXOUT1 signals. In single-ended mode, only MUXOUT0 is used. In differential mode, MUXOUT0 is the positive side and MUXOUT1 is the negative side. The MUXOUT0 and MUXOUT1 outputs and the ADCIN external analog input are provided so that external signal conditioning circuits (such as filters) may be applied to the analog signals before conversion.
TOUCHSCREEN INTERFACE 16.2.1 The ADC provides an interface for 4-wire resistive touchscreens with the resolution necessary for applications such as signature analysis. A typical touchscreen configuration is shown in Figure 25. Touchscreen Driver Configuration An equivalent circuit for the touchscreen interface is shown in Figure 26. VCC TSX+/ADC0 TSY+/ADC1 6Ω 6Ω TSY+ TSX-/ADC2 TSX+ X Plate TSY-/ADC3 Y Plate RX1 A To ADC RX2 MUXOUT0 RY1 RZ B RY2 TSX- ADCIN TSY- DS186 6Ω Figure 25.
CP3BT26 16.2.2 Measuring Pen Force Solving for RY1, the resistance is: Figure 27 shows equivalent circuits for the driver modes used to measure the X, Y, and Z coordinates, in which Z represents pen force. In this discussion, the ohmic resistance of the drivers is neglected (see Section 16.2.3), and series resistance between the node of interest and the ADC is ignored because it has no significant effect.
16.5 Table 34 lists the ADC registers. The Global Configuration Register (ADCGCR) provides the flexibility to implement any of these techniques. 16.3 ADC REGISTER SET ADC OPERATION IN POWER-SAVING MODES To reduce the level of switching noise in the environment of the ADC, it is possible to operate the CP3BT26 in low-power modes, in which the System Clock is slowed or switched off.
CP3BT26 16.5.1 ADC Global Configuration Register (ADCGCR) MUX_CFG The ADCGCR register controls the basic operation of the interface. The CPU bus master has read/write access to the ADCGCR register. After reset this register is set to 0000h. 8 7 6 5 TOUCH_CFG 15 4 3 MUX_CFG 14 13 2 Table 35 MUX_CFG Operation 0 DIFF ADCIN CLKEN 12 MUXOUTEN INTEN Res. 1 The Multiplexer Configuration field and the DIFF bit configure the analog circuits of the ADC module, as shown in Table 35.
PREF_CFG PREF Source 00 Internal (AVCC) 01 VREFP 10 ADC0 11 ADC1 16.5.2 ADC Auxiliary Configuration Register (ADCACR) The ADCACR register is used to control the clock configuration and report the status of the ADC module. The CPU bus master has read/write access to the ADCACR register. After reset, this register is clear.
CP3BT26 16.5.3 ADC Conversion Control Register (ADCCNTRL) 16.5.4 The ADCCNTRL register specifies the trigger conditions for an ADC conversion. 15 3 Reserved POL EXT AUTO 2 1 AUTO EXT 0 The ADCSTART register is a write-only register used by software to initiate an ADC conversion. Writing any value to this register will cause the ADC to initiate a conversion or prime the ADC to initiate a conversion, as controlled by the ADCCNTRL register. 16.5.
ADC Result Register (ADCRESLT) The ADCRESLT register includes the software-visible end of a 4-word FIFO. Conversion results are loaded into the FIFO from the 12-bit ADC and unloaded when software reads the ADCRESLT register. The ADCRESLT register is read-only. With the exception of the PEN_DOWN bit, the fields in this register are cleared when the register is read.
CP3BT26 17.0 Random Number Generator (RNG) The RNG unit is a hardware “true random” number generator. When enabled, this unit provides up to 800 random bits per second. The bits are available for reading from a 16-bit register. The RNG unit includes two oscillators which operate independently of the System Clock: When a new 16-bit word of random data is available, it is loaded into the RNGD register. If enabled, an interrupt request (IRQ3) is asserted when the word is available for reading.
RANDOM NUMBER GENERATOR REGISTER SET 17.2.2 The RNGD register holds random data generated by the RNG module. After reading the register, it is cleared and the DVALID bit of the RNGCST register is cleared. When a new word of valid (random) data becomes available in the RNGD register, the DVALID bit is set and (if enabled) and interrupt request is asserted. Table 34 lists the RNG registers.
CP3BT26 18.0 USB Controller The CR16 USB node is an integrated USB node controller NodeOperational that features enhanced DMA support with many automatic This is the normal operating state of the node. In this state, data handling features. It is compatible with USB specifica- the node is configured for operation on the USB. tion versions 1.0 and 1.1. NodeSuspend It integrates the required USB transceiver, a Serial Interface Engine (SIE), and USB endpoint (EP) FIFOs.
ENDPOINT OPERATION 18.2.2 Transmit and Receive Endpoint FIFOs The CR16 USB node uses a total of seven transmit and receive FIFOs: one bidirectional transmit and receive FIFO for Packets are broadcast from the host controller to all nodes the mandatory control endpoint, three transmit FIFOs, and on the USB network. Address detection is implemented in three receive FIFOs.
CP3BT26 Bidirectional Control Endpoint FIFO0 Operation FIFO0 should be used for the bidirectional control endpoint 0. It can be configured to receive data sent to the default address with the DEF bit in the EPC0 register. Isochronous transfers are not supported for the control endpoint. The Endpoint 0 FIFO can hold a single receive or transmit packet with up to 8 bytes of data. Figure 30 shows the basic operation in both receive and transmit direction.
The Receive FIFOs for endpoints 2, 4, and 6 support bulk, interrupt, and isochronous USB packet transfers larger than the actual FIFO size. If the packet length exceeds the FIFO size, software must read the FIFO contents while the USB packet is being received on the bus. Figure 32 shows the detailed behavior of receive FIFOs. The CR16 USB node has a set of memory-mapped registers that can be read/written from the CPU bus to control the USB interface.
CP3BT26 Table 40 USB Controller Registers Table 40 USB Controller Registers Name Address Description Name Address Description EPC0 FF FDC0h Endpoint Control 0 Register RXS3 FF FDFCh Receive Status 3 Register EPC1 FF FDD0h Endpoint Control 1 Register RXC0 FF FDCEh Receive Command 0 Register EPC2 FF FDD8h Endpoint Control 2 Register RXC1 FF FDDEh Receive Command 1 Register EPC3 FF FDE0h Endpoint Control 3 Register RXC2 FF FDEEh Receive Command 2 Register EPC4 FF FDDE8h Endpoi
The Node Attached indicates that this node is ready to be detected as attached to USB. When clear, the transceiver forces SE0 on the USB node controller to prevent the hub (to which this node is connected) from detecting an attach event. After reset or when the USB node is disabled, this bit is cleared to give the device time before it must respond to commands. After this bit has been set, the device no longer drives the USB and should be ready to receive Reset signaling from the hub.
CP3BT26 18.3.3 Main Event Register (MAEV) RX_EV The Receive Event bit is set if any of the unmasked bits in the Receive Event (RXEV) register is set. It indicates that a SETUP or OUT transaction has been completed. This bit is cleared when all of the RX_LAST bits in each Receive Status (RXSn) register and all RXOVRRN bits in the RXEV register are cleared. 0 – No receive event has occurred. 1 – A receive event has occurred.
SD5 RESET RESUME 18.3.6 The Suspend Detect 3 ms bit is set after 3 ms of IDLE have been detected on the upstream port, indicating that the device should be suspended. The suspend occurs under software control by writing the suspend value to the Node Functional State (NFSR) register. This bit is cleared when the register is read. 0 – No 3 ms in IDLE has been detected. 1 – 3 ms in IDLE has been detected.
CP3BT26 18.3.9 Receive Event Register (RXEV) 18.3.11 NAK Event Register (NAKEV) The RXEV register reports the current status of the FIFO, used by the three Receive Endpoints. The RXEV register is clear after reset. It provides read-only access from the CPU bus. 7 4 3 RXOVRRN RXFIFO RXOVRRN 0 7 RXFIFO 18.3.10 Receive Mask Register (RXMSK) The RXMSK register is used to select the bits of the RXEV register, which cause the RX_EV bit in the MAEV register to be set.
18.3.15 Frame Number High Byte Register (FNH) The FWEV register signals whether a receive or transmit FIFO has reached its warning limit. It reports the status for all FIFOs, except for the Endpoint 0 FIFO, as no warning limit can be specified for this FIFO. The FWEV register provides read-only access from the CPU bus. It is clear after reset. The FNH register contains the three most significant bits (MSB) of the current frame counter as well as status and control bits for the frame counter.
CP3BT26 MF The Missed SOF bit is set when the frame number in a valid received SOF does not match the expected next value, or when an SOF is not received within 12060 bit times. The MF bit provides read-only access. On reset, this bit is set. This bit is set by the hardware and is cleared by reading the FNH register. 0 – No condition indicated. 1 – The frame number in a valid SOF does not match the expected next value, or no valid SOF was received within 12060 bit times. 18.3.
The DMA Toggle bit is used to determine the initial state of Automatic DMA (ADMA) operations. Software initially sets this bit if starting with a DATA1 operation, and clears this bit if starting with a DATA0 operation. Writes to this bit also update the NTGL bit in the DMAEV register. IGNRXTGL The Ignore RX Toggle controls whether the compare between the NTGL bit in the DMAEV register and the TOGGLE bit in the respective RXSn register is ignored during receive operations.
CP3BT26 18.3.20 DMA Mask Register (DMAMSK) 18.3.23 DMA Error Register (DMAERR) Any set bit in the DMAMSK register enables automatic setting of the DMA bit in the ALTEV register when the respective event in the DMAEV register occurs. Otherwise, setting the DMA bit is disabled. For a description of bits 0 to 3, see the DMAEV register. The DMAMSK register provides read/ write access. After reset it is clear. Reading reserved bits returns undefined data.
18.3.25 Transmit Status 0 Register (TXS0) The TXS0 register reports the transmit status of the mandatory Endpoint 0. It is loaded with 08h after reset. This register allows read-only access from the CPU bus. 18.3.24 Endpoint Control 0 Register (EPC0) 7 The EPC0 register controls the mandatory Endpoint 0. It is clear after reset. Reserved bits read undefined data. 7 6 STALL DEF EP DEF STALL 5 4 Reserved 3 6 5 4 3 Res. ACK_STAT TX_DONE Res.
CP3BT26 FLUSH Writing a 1 to the Flush FIFO bit flushes all TOGGLE The Toggle bit reports the PID used when redata from the control endpoint FIFOs, resets ceiving the packet. When clear, this bit indithe endpoint to Idle state, clears the FIFO cates that the last successfully received read and write pointer, and then clears itself. packet had a DATA0 PID. When set, this bit inIf the endpoint is currently using the FIFO0 to dicates that the packet had a DATA1 PID.
Writing 1 to the Flush bit flushes all data from ISO the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using FIFO0 to transfer data on USB, flushing is delayed until after the transfer is done. This bit is cleared on reset. This bit is equivalent to FLUSH in the TXC0 register. 0 – Writing 0 has no effect. 1 – Writing 1 flushes the FIFOs. STALL 18.3.
CP3BT26 ACK_STAT TX_URUN The Acknowledge Status bit is valid when the LAST TX_DONE bit is set. The meaning of the ACK_STAT bit differs depending on whether ISO or non-ISO operation is used (as selected by the ISO bit in the EPCn register). Non-Isochronous mode—This bit indicates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set when an ACK is received; otherwise, it is clear.
The Transmit FIFO Warning Limit bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs. If the number of bytes remaining in the FIFO is equal to or less than the selected warning limit, the TXWARN bit in the FWEV register is set. To avoid interrupts caused by setting this bit while the FIFO is being filled before a transmission begins, TXWARN is only set when transmission from the endpoint is enabled (TX_ENn in the TXCn register is set).
CP3BT26 18.3.36 Receive Command Register n (RXCn) 18.3.37 Receive Data Register n (RXD) Each of the receive endpoints (2, 4, and 6) has one RXCn register. The registers provide read/write access from the CPU bus. Reading reserved bits returns undefined data. After reset, it is clear. Each of the three Receive Endpoint FIFOs has one RXD register. Reading the Receive Data register n returns the data located in the receive FIFO n at the current position of the receive read pointer.
The CAN module contains a Full CAN class, CAN (Controller Area Network) serial bus interface for low/high speed applications. It supports reception and transmission of extended frames with a 29-bit identifier, standard frames with an 11-bit identifier, applications that require high speed (up to 1 MBit/s), and a low-speed CAN interface with CAN master capability.
CP3BT26 CANTX CANRX Wake-Up CTX 0 0 1 1 CRX CAN CORE Transceiver Logic BTL, RX shift, TX shift, CRC Bit Stream Processor Control Error Management Logic Status INTERFACE MANAGEMENT Data Control Interface Management Processor RAM TX/RX Message Buffer 0 Acceptance Filtering TX/RX Message Buffer 1 Interface Management Processor BTL CONFIG CAN PRESCALER CONTROL TX/RX Message Buffer 14 ACCEPTANCE MASKS CPU BUS DS018 Figure 34.
written by a message with a higher priority. As soon as a transmitting module detects another module with a higher priority accessing the bus, it stops transmitting its own frame and switches to receive mode, as shown in Figure 35. TxPIN MODULE A RxPIN TxPIN MODULE B RxPIN BUS LINE RECESSIVE DOMINANT MODULE A SUSPENDS TRANSMISSION DS019 Figure 35.
The remainder of this division is the CRC sequence transmitted over the bus. On the receiver side, the module divides all bit fields up to the CRC delimiter excluding stuff bits, and checks if the result is zero. This will then be interpreted as a valid CRC. After the CRC sequence a single “recessive” bit is transmitted as the CRC delimiter. The DLC field indicates the number of bytes in the data field. It consists of four bits. The data field can be of length zero.
Start of Frame (SOF) Arbitration Field + Extended Arbitration Control Field Data Field Cyclic Redundancy Check Field (CRC) Remote Frame Figure 38 shows the structure of a standard remote frame. Figure 39 shows the structure of an extended remote frame. Control Field 11 CRC Field d 15 CRC DLC0 ID0 RTR IDE RB0 DLC3 4 ID3 START OF FRAME ID 10 16 Arbitration Field d d d IDENTIFIER 10 ...
CP3BT26 Error Frame at the bit following the acknowledge delimiter, unless an erAs shown in Figure 40, the Error Frame consists of the error ror flag for a previous error condition has already been startflag and the error delimiter bit fields. The error flag field is ed. built up from the various error flags of the different nodes.
CP3BT26 INTERFRAME SPACE 3 START OF FRAME 8 SUSPEND TRANSMIT INT Bus Idle ANY FRAME r r r r r r r r r r r r r r r r r r r r r DATA FRAME OR REMOTE FRAME r d Note: d = dominant r = recessive INT = Intermission Suspend Transmission is only for error passive nodes. DS026 Figure 42. Interframe Space 19.2.4 Error Types a receiver, a “dominant” bit during the last bit of End of Frame does not constitute a frame error.
CP3BT26 Error Active when the transmit error counter is greater than 255. A bus An error active unit can participate in bus communication off device will become error active again after monitoring 128 × 11 “recessive” bits (including bus idle) on the bus. and may send an active (“dominant”) error flag. When the device goes from “bus off“ to “error active“, both Error Warning error counters will have a value of 0. The Error Warning state is a sub-state of Error Active to indicate a heavily disturbed bus.
Bit Time Logic CAN Bit Time In the Bit Time Logic (BTL), the CAN bus speed and the Synchronization Jump Width can be configured by software. The CAN module divides a nominal bit time into three time segments: synchronization segment, time segment 1 (TSEG1), and time segment 2 (TSEG2). Figure 44 shows the various elements of a CAN bit time. The number of time quanta in a CAN bit (CAN Bit Time) ranges between 4 and 25.
CP3BT26 e Bus Signal CAN Clock PREVIOUS BIT A TSEG1 TSEG2 NEXT BIT "NORMAL" BIT TIME PREVIOUS BIT A TSEG1 SJW TSEG2 NEXT BIT BIT TIME LENGTHENED BY SJW DS029 Figure 45. Resynchronization (e > SJW) e Bus Signal CAN Clock PREVIOUS BIT A TSEG1 TSEG2 "NORMAL" BIT TIME PREVIOUS BIT A TSEG1 TSEG2 NEXT BIT BIT TIME SHORTENED BY SJW DS030 Figure 46. 19.2.
For reception of data frame or remote frames, the CAN module follows a “receive on first match” rule which means that a given message is only received by one buffer: the first one which matches the received message ID. This provides the capability to accept only a single ID for each buffer or to accept a group of IDs. The following two examples illustrate the difference.
CP3BT26 buffer status field. With this lock function, software has the capability to save several messages with the same identifier or same identifier group into more than one buffer. For example, a buffer with the second highest priority will receive a message if the buffer with the highest priority has already received a message and is now locked (provided that both buffers use the same acceptance filtering mask).
Data Frames. In the second method, a remote frame can trigger one or more message buffer to transmit a data frame upon reception. This procedure is described under To Answer Remote Frames on page 123. 19.5.1 Receive Timing As soon as the CAN module receives a “dominant” bit on the CAN bus, the receive process is started. The received ID and data will be stored in the hidden receive buffer if the global or basic acceptance filtering matches.
CP3BT26 Yes Read buffer 2. Read CNSTAT 3. 4. 5. RX_READY? No 6. Yes RX_BUSYx? 7. No When the BUFFLOCK function is enabled (see BUFFLOCK on page 119), it is not necessary to check for new messages received during the read process from the buffer, as this buffer is locked after the reception of the first valid frame. A read from a locked receive buffer can be performed as shown in Figure 55. Interrupt Entry Point RX_OVERRUN? that case the procedure described below must be followed.
tance filtering mask of one or more buffers, the buffer status will change to TX_ONCE_RTR, the contents of the buffer will be transmitted, and afterwards the CAN module will write TX_RTR in the status code register again.
CP3BT26 ity is combined by the 4-bit TXPRI value and the 4-bit buffer number (0...14) as shown below. The lowest resulting number results in the highest transmit priority. 7 4 3 19.6.3 The transmission of a CAN message must be executed as follows (see also Figure 57) 1. Configure the CNSTAT status field as TX_NOT_ACTIVE. If the status is TX_BUSY, a previous transmit request is still pending and software has no access to the data contents of the buffer.
TX Buffer States If the CPU configures the message buffer to The transmission process can be started after software has TX_ONCE_RTR, it will transmit its data contents. During the loaded the buffer registers (data, ID, DLC, PRI) and set the transmission, the buffer state is 1111b as the CPU wrote buffer status from TX_NOT_ACTIVE to TX_ONCE, 1110b into the status section of the CNSTAT register. After the successful transmission, the buffer enters the TX_RTR TX_RTR, or TX_ONCE_RTR.
CP3BT26 19.7.1 Table 49 Highest Priority Interrupt Code (ICEN=FFFF) Highest Priority Interrupt Code To reduce the decoding time for the CIPND register, the buffer interrupt request with the highest priority is placed as interrupt status code into the IST[3:0] section of the CSTPND register.
MEMORY ORGANIZATION vide single-cycle word and byte access without any potential wait state. The CAN module occupies 144 words in the memory address space. This space is organized as 15 banks of 8 All register descriptions within the next sections have the folwords per bank (plus one reserved bank) for the message lowing layout: buffers and 14 words (plus 2 reserved words) for control and status. 15 0 19.9.
CP3BT26 19.10 CAN CONTROLLER REGISTERS 19.10.1 Buffer Status/Control Register (CNSTAT) The buffer status (ST), the buffer priority (PRI), and the data length code (DLC) are controlled by manipulating the contents of the Buffer Status/Control Register (CNSTAT). The CPU and CAN module have access to this register. Table 51 lists the CAN module registers. Table 51 CAN Controller Registers Name Address Description CNSTAT See Table 50.
CP3BT26 Table 52 Buffer Status Section of the CNSTAT Register ST3 (DIR) ST2 ST1 ST0 (BUSY) Buffer Status 0 0 0 0 RX_NOT_ACTIVE 0 0 0 1 Reserved for RX_BUSY. (This condition indicates that software wrote RX_NOT_ACTIVE to a buffer when the data copy process is still active.) 0 0 1 0 RX_READY 0 0 1 1 RX_BUSY0 (Indicates data is being copied for the first time RX_READY → RX_BUSY0.
CP3BT26 PRI DLC The Transmit Priority Code field holds the software-defined transmit priority code for the message buffer. The Data Length Code field determines the number of data bytes within a received/transmitted frame. For transmission, these bits need to be set according to the number of data bytes to be transmitted. For reception, these bits indicate the number of valid received data bytes available in the message buffer.
19.10.4 Storage of Extended Messages The data bytes that are not used for data transfer are “don’t cares”. If the object is transmitted, the data within these bytes will be ignored. If the object is received, the data within these bytes will be overwritten with invalid data. If the IDE bit is set, the buffer handles extended frames. The storage of the extended ID follows the descriptions in Table 55. The SRR bit is at the bit position of the RTR bit for standard frame and needs to be transmitted as 1.
CP3BT26 19.10.5 Storage of Remote Messages During remote frame transfer, the buffer registers DATA0– DATA3 are “don’t cares”. If a remote frame is transmitted, the contents of these registers are ignored. If a remote frame is received, the contents of these registers will be overwritten with invalid data. The structure of a message buffer set up for a remote frame with extended identifier is shown in Table 56.
TSTPEN The CAN Global Configuration Register (CGCR) is a 16-bit wide register used to: Enable/disable the CAN module. Configure the BUFFLOCK function for the message buffer 0..14. Enable/disable the time stamp synchronization. Set the logic levels of the CAN Input/Output pins, CANRX and CANTX. Choose the data storage direction (DDIR). Select the error interrupt type (EIT). Enable/disable diagnostic functions.
CP3BT26 Sequence of Data Bytes on the Bus ID Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 CRC t ADDR Offset Storage of Data Bytes in the Buffer Memory Data Bytes 0A16 Data1 Data2 0816 Data3 Data4 0616 Data5 Data6 0416 Data7 Data8 DS045 Figure 61.
DIAGEN EIT If the Internal function is enabled, the CANTX and CANRX pins of the CAN module are internally connected to each other. This feature can be used in conjunction with the LOOPBACK mode. This means that the CAN module can receive its own sent messages without connecting an external transceiver chip to the CANTX and CANRX pins; it allows software to run real stand-alone tests without any peripheral devices. 0 – Normal mode. 1 – Internal mode.
CP3BT26 TSEG1 The Time Segment 1 field configures the length of the Time Segment 1 (TSEG1). It is not recommended to configure the time segment 1 to be smaller than 2 time quanta. (see Table 59). Table 59 Time Segment 1 Settings 19.10.8 Global Mask Register (GMSKB/GMSKX) The GMSKB and GMSKX registers allow software to globally mask, or “don’t care” the incoming extended/standard identifier bits, RTR/XRTR and IDE.
19.10.10 CAN Interrupt Enable Register (CIEN) The BMSKB and BMSKX registers allow masking the buffer The CAN Interrupt Enable (CIEN) register enables the 14, or “don’t care” the incoming extended/standard identifier transmit/receive interrupts of the message buffers 0 through bits, RTR/XRTR, and IDE. Throughout this document, the 14 as well as the CAN Error Interrupt. two 16-bit registers BMSKB and BMSKX are referenced to as a 32-bit register BMSK. 15 14 0 The following are the bits for the BMSKB register.
CP3BT26 19.10.12 CAN Interrupt Clear Register (CICLR) 19.10.14 CAN Status Pending Register (CSTPND) The CICLR register bits individually clear CAN interrupt The CSTPND register holds the status of the CAN Node pending flags caused by the message buffers and from the and the Interrupt Code. Error Management Logic. Do not modify this register with instructions that access the register as a read-modify-write 15 8 7 5 4 3 0 operand, such as the bit manipulation instructions.
The CANEC register reports the values of the CAN Receive Error Counter and the CAN Transmit Error Counter. 15 8 7 0 REC TEC EFID3:0 Field 1101 DLC 1110 DATA 1111 CRC 0 EBID R REC The CAN Receive Error Counter field reports the value of the receive error counter. The CAN Transmit Error Counter field reports the value of the transmit error counter. TEC The Error Bit Identifier field reports the bit position of the incorrect bit within the erroneous frame field.
CP3BT26 DRIVE The Drive bit shows the output value on the CANTX pin at the time of the error. Note that a receiver will not drive the bus except during ACK and during an active error flag. 19.10.17 CAN Timer Register (CTMR) 19.11.1 External Connection The CAN module uses the CANTX and CANRX pins to connect to the physical layer of the CAN interface. They provide the functionality described in Table 64.
Task Cycle Count Occurrence/ Frame Copy hidden buffer to receive message buffer 17 0–1 Baud Rate Minimum Clock Frequency Update status from TX_RTR to TX_ONCE_RTR 3 0–15 1 Mbit/sec 15.25 MHz Schedule a message for transmission 2 0–1 500 kbit/sec 7.625 MHz 250 kbit/sec 3.81 MHz Table 66 Minimum Clock Frequency Requirements The critical path derives from receiving a remote frame, which triggers the transmission of one or more data frames.
CP3BT26 19.12 USAGE HINT Under certain conditions, the CAN module receives a frame sent by itself, even though the loopback feature is disabled. Two conditions must be true to cause this malfunction: A transmit buffer and at least one receive buffer are configured with the same identifier. Assume this identifier is called ID_RX_TX.
The Advanced Audio Interface (AAI) provides a serial synchronous, full duplex interface to codecs and similar serial devices. The transmit and receive paths may operate asynchronously with respect to each other. Each path uses a 3wire interface consisting of a bit clock, a frame synchronization signal, and a data signal. The CPU interface can be either interrupt-driven or DMA. If the interface is configured for interrupt-driven I/O, data is buffered in the receive and transmit FIFOs.
CP3BT26 20.2.2 Synchronous Mode In synchronous mode, the receive and transmit paths of the audio interface use the same shift clock and frame sync signal. The bit shift clock and frame sync signal for both paths are derived from the same set of clock prescalers. 20.2.3 Normal Mode data bytes or words available in the transmit FIFO is equal or less than a programmable warning limit.
ta da 0 Sl ot Assignment Sl Figure 67 shows the frame timing while operating in network mode with four slots per frame, slot 1 assigned to the interface, and a long frame sync interval.
CP3BT26 The ideal required prescaler value Pideal can be calculated as follows: Pideal = fAudio In / fbit = 12 MHz / 256 kHz = 46.875 SFS Therefore, the real prescaler value is 47. This results in a bit clock error equal to: SRCLK (auxiliary frame sync) fbit_error = (fbit - fAudio In/Preal) / fbit × 100 = (256 kHz - 12 MHz/47) / 256 kHz × 100 = 0.27% SRFS (auxiliary frame sync) 20.
event, the read pointer (TRP) will be decremented by 1 (incremented by 15) and the previous data word will be transmitted again. A transmit FIFO underrun is indicated by the TXU bit in the Audio Interface Transmit Status and Control Register (ATSCR). Also, no transmit interrupt will be generated (even if enabled). RXIE RXIP = 1 When the TRP is equal to the TWP and the last access to the FIFO was a write operation (to the ATFR), the FIFO is full.
CP3BT26 20.5.6 Network Mode DMA Operation In network mode, each frame sync signal marks the beginning of new frame. Each frame can consist of up to four slots. The audio interface operates in a similar way to normal mode, however, in network mode the transmitter and receiver can be assigned to specific slots within each frame as described below. 20.5.7 Transmit The transmitter only shifts out data during the assigned slot. During all other slots the STD output is in TRI-STATE mode.
Bit Shift Clock (SCK/SRCLK) Shift Data (STD/SRD) D0 D1 D2 D3 D4 D5 D6 D7 Some codecs require an inverted frame sync signal. This is available by setting the Inverted Frame Sync bit in the AGCR register. 20.6.3 Audio Control Data The audio interface provides the option to fill a 16-bit slot with up to three data bits if only 13, 14, or 15 PCM data bits are transmitted. These additional bits are called audio control data and are appended to the PCM data stream.
CP3BT26 20.6.4 IOM-2 Mode The IOM-2 interface has the following properties: The AAI can operate in a special IOM-2 compatible mode to allow to connect to an external ISDN controller device. In this IOM-2 mode, the AAI can only operate as a slave, i.e. the bit clock and frame sync signal is provided by the ISDN controller. The AAI only supports the B1 and B2 data of the IOM-2 channel 0, but ignores the other two IOM-2 channels. The AAI handles the B1 and B2 data as one 16-bit data word.
20.7 Freeze Mode The audio interface provides a FREEZE input, which allows to freeze the status of the audio interface while a development system examines the contents of the FIFOs and registers. When the FREEZE input is asserted, the audio interface behaves as follows: The receive FIFO or receive DMA registers are not updated with new data. The receive status bits (RXO, RXE, RXF, and RXAF) are not changed, even though the receive FIFO or receive DMA registers are read.
CP3BT26 20.7.1 Audio Receive FIFO Register (ARFR) 20.7.3 The Audio Receive FIFO register shows the receive FIFO location currently addressed by the Receive FIFO Read Pointer (RRP). The receive FIFO receives 8-bit or 16-bit data from the Audio Receive Shift Register (ARSR), when the ARSR is full. In 8-bit mode, only the lower byte of the ARFR is used, and the upper byte contains undefined data. In 16-bit mode, a 16-bit word is copied from ARSR into the receive FIFO.
Audio Global Configuration Register (AGCR) IEFS The AGCR register controls the basic operation of the interface. The CPU bus master has read/write access to the AGCR register. After reset, this register is clear. 7 6 5 4 IEBC FSS IEFS 3 SCS 2 1 0 LPB DWL ASS 10 9 8 CTF CRF FSS 15 14 13 CLKEN AAIEN IOM2 ASS DWL LPB SCS 12 11 IFS FSL The Asynchronous/Synchronous Mode Select bit controls whether the audio interface operates in Asynchronous or in Synchronous mode.
CP3BT26 IOM2 The IOM-2 Mode bit selects the normal PCM interface mode or a special IOM-2 mode used to connect to external ISDN controller devices. The AAI can only operate as a slave in the IOM-2 mode, i.e. the bit clock and frame sync signals are provided by the ISDN controller. If the IOM2 bit is clear, the AAI operates in the normal PCM interface mode used to connect to external PCM codecs and other PCM audio devices. 0 – IOM-2 mode disabled. 1 – IOM-2 mode enabled.
Audio Receive Status and Control Register (ARSCR) The following table shows the slot assignment scheme. The ARSCR register is used to control the operation of the receiver path of the audio interface. It also holds bits which report the current status of the receive FIFO. The CPU bus master has read/write access to the ASCR register. At reset, this register is loaded with 0004h.
CP3BT26 20.7.8 Audio Transmit Status and Control Register (ATSCR) The ASCR register controls the basic operation of the interface. It also holds bits which report the current status of the audio communication. The CPU bus master has read/write access to the ASCR register. At reset, this register is loaded with F003h.
Audio Clock Control Register (ACCR) ignored. The following table shows the receive DMA request scheme. The ACCR register is used to control the bit timing of the audio interface. After reset, this register is clear. 7 1 FCPRS 15 RMD DMA Request Condition 0 0000 None CSS 0001 ARDR0 full 0010 ARDR1 full 0011 ARDR0 full or ARDR1 full x1xx Not supported on CP3BT26 8 BCPRS CSS FCPRS BCPRS The Clock Source Select bit selects one out of two possible clock sources for the audio interTMD face.
CP3BT26 21.0 CVSD/PCM Conversion Module The CVSD/PCM module performs conversion between CVSD data and PCM data, in which the CVSD encoding is as defined in the Bluetooth specification and the PCM encoding may be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit Linear. The CVSD conversion module operates at a fixed rate of 125 µs (8 kHz) per PCM sample. On the CVSD side, there 2 MHz Clock Input is a read and a write FIFO allowing up to 8 words of data to be read or written at the same time.
If the resolution is not set properly, the audio signal may be 8 × 16 bit (8 words). The warning limits for the two FIFOs is set at 5 words. (The CVSD In FIFO interrupt will occur when clipped or have reduced attenuation. there are 3 words left in the FIFO, and the CVSD Out FIFO 21.4 PCM TO CVSD CONVERSION interrupt will occur when there are 3 or less empty words left The converter core reads out the double-buffered PCMIN in the FIFO.
CP3BT26 The CVSD/PCM module only supports indirect DMA transfers. Therefore, transferring PCM data between the CVSD/ PCM module and another on-chip module requires two bus cycles. Table 68 CVSD/PCM Registers Name Address Description The trigger for DMA may also trigger an interrupt if the corresponding enable bits in the CVCTRL register is set. Therefore care must be taken when setting the desired interrupt and DMA enable bits.
Logarithmic PCM Data Input Register (LOGIN) The LOGIN register is an 8-bit wide write-only register. It is used to receive 8-bit logarithmic PCM data from the peripheral bus and convert it into 13-bit linear PCM data. 7 0 LOGIN 21.9.6 Logarithmic PCM Data Output Register (LOGOUT) The LOGOUT register is an 8-bit wide read-only register. It holds logarithmic PCM data that has been converted from linear PCM data. After reset, the LOGOUT register is clear. 7 0 LOGOUT 21.9.
CP3BT26 DMAPI The DMA Enable for PCM In bit enables hard- CVNF ware DMA control for writing PCM data into the PCMIN register. If cleared, DMA support is disabled. After reset, this bit is clear. 0 – PCM input DMA disabled. 1 – PCM input DMA enabled. CVSDCONV The CVSD to PCM Conversion Format field specifies the PCM format for CVSD/PCM conversions. After reset, this field is clear. 00 – CVSD <-> 8-bit µ-Law PCM. 01 – CVSD <-> 8-bit A-Law PCM. 10 – CVSD <-> Linear PCM. 11 – Reserved.
The CP3BT26 provides four UART modules. Each UART module is a full-duplex Universal Asynchronous Receiver/ Transmitter that supports a wide range of software-programmable baud rates and data formats. It handles automatic parity generation and several error detection schemes.
of the RSFT register are copied into the UnRBUF register and the Receive Buffer Full bit (URBF) is set. The URBF bit is automatically cleared when software reads the character from the URBUF register. The RSFT register is not software accessible. Serial data input on the RXD pin is shifted into the RSFT register.
Synchronous Mode 22.2.3 The synchronous mode of the UART enables the device to communicate with other devices using three communication signals: transmit, receive, and clock. In this mode, data bits are transferred synchronously with the UART clock signal. Data bits are transmitted on the rising edges and received on the falling edges of the clock signal, as shown in Figure 78. Data bytes are transmitted and received least significant bit (LSB) first.
CP3BT26 Table 69 Prescaler Factors (Continued) parity bit is generated and transmitted following the eight data bits. 2 Start Bit 2a Start Bit 2b Start Bit 8-Bit Data PA 2c Start Bit 8-Bit Data PA 8-Bit Data Prescaler Select Prescaler Factor 01011 6 01100 6.5 01101 7 01110 7.5 01111 8 10000 8.5 10001 9 10010 9.5 10011 10 10100 10.5 10101 11 10110 11.5 10111 12 11000 12.5 11001 13 11010 13.5 11011 14 11100 14.5 11101 15 11110 15.
CP3BT26 Figure 82 shows a diagram of the interrupt sources and associated enable bits. UEEI UFE UDOE UERR RX Interrupt UPE UERI URBF UETI TX Interrupt UTBE UEFCI FC Interrupt UDCTS DS066 Figure 82. UART Interrupts The interrupts can be individually enabled or disabled using the Enable Transmit Interrupt (UETI), Enable Receive Interrupt (UERI), and Enable Receive Error Interrupt (UEER) bits in the UnICTRL register. 22.2.
CP3BT26 22.3 UART REGISTERS Table 70 Software interacts with the UART modules by accessing the UART registers, as listed in Table 70. Table 70 UART Registers Name U0RBUF U0TBUF U0PSR U0BAUD U0FRS U0MDSL1 U0STAT U0ICTRL U0OVR U0MDSL2 U0SPOS U1RBUF U1TBUF U1PSR U1BAUD U1FRS U1MDSL1 U1STAT U1ICTRL U1OVR www.national.
22.3.4 Name Address Description U3OVR FF F270h UART3 Oversample Rate Register U3MDSL2 FF F272h UART3 Mode Select Register 2 FF F274h UART3 Sample Position Register U3SPOS 22.3.1 The UnBAUD register is a byte-wide, read/write register that contains the lower eight bits of the baud rate divisor. The register contents are unknown at power-up and are left unchanged by a reset operation. The register format is shown below.
CP3BT26 UPEN 22.3.6 The Parity Enable bit enables or disables parity generation and parity checking. When the UART is configured to transmit nine data bits per frame, there is no parity bit and the UnPEN bit is ignored. 0 – Parity generation and checking disabled. 1 – Parity generation and checking enabled. UART Mode Select Register 1 (UnMDSL1) 6 5 4 3 2 1 The Enable Receive DMA bit controls whether DMA is used for UART receive operations.
The Break Detect bit indicates when a line break condition occurs. This condition is detected if RXD remains low for at least ten bit times after a missing stop bit has been detected at the end of a frame. The hardware automatically clears the UBKD bit on reading the UnSTAT register, but only if the break condition on RXD no longer exists.
CP3BT26 22.3.10 UART Mode Select Register 2 (UnMDSL2) The UnMDSL2 register is a byte-wide, read/write register that controls the sample mode used to recover asynchronous data. At reset, the UnOVR register is cleared. The register format is shown below. 7 1 USMD USMD BAUD RATE CALCULATIONS The USMD bit controls the sample mode for 22.4.1 Asynchronous Mode asynchronous transmission. 0 – UART determines the sample position au- The equation to calculate the baud rate in asynchronous mode is: tomatically.
Synchronous Mode where BR is the baud rate, SYS_CLK is the System Clock, N is the value of the baud rate divisor + 1, and P is the prescaler divide factor selected by the value in the UnPSR register. Oversampling is not used in synchronous mode. Synchronous mode is only available for the UART0 module. When synchronous mode is selected and the UCKS bit is set, the UART operates from a clock received on the CKX pin.
CP3BT26 Table 72 Baud Rate Programming SYS_CLK = 8 MHz SYS_CLK = 6 MHz SYS_CLK = 5 MHz SYS_CLK = 4 MHz Baud Rate O N P %err O N P %err O N P %err O N P %err 300 7 401 9.5 0.00 16 1250 1.0 0.00 11 202 7.5 0.01 12 202 5.5 0.01 600 12 1111 1.0 0.01 16 625 1.0 0.00 11 101 7.5 0.01 12 101 5.5 0.01 1200 12 101 5.5 0.01 16 125 2.5 0.00 10 119 3.5 0.04 11 202 1.5 0.01 1800 8 101 5.5 0.01 11 303 1.0 0.01 11 101 2.5 0.01 11 202 1.
Microwire/Plus is a synchronous serial communications protocol, originally implemented in National Semiconductor's COP8® and HPC families of microcontrollers to minimize the number of connections, and therefore the cost, of communicating with peripherals. The CP3BT26 has an enhanced Microwire/SPI interface module (MWSPI) that can communicate with all peripherals that conform to Microwire or Serial Peripheral Interface (SPI) specifications.
CP3BT26 Interrupt Request Write Data Control + Status MWCS 16-BIt Read Buffer Write Data 8 8 MWDAT 16-BIt Shift Register Data Out Slave Master MDODI Slave Data In Master MDIDO MSK System Clock Clock Prescaler + Select Master Figure 84. 23.1.2 MSK DS068 Microwire Block Diagram Reading 23.1.4 The enhanced Microwire interface implements a double buffer on read. As illustrated in Figure 84, the double read buffer consists of the 16-bit shifter and a buffer, called the read buffer.
MASTER MODE In Master mode, the MSK pin is an output for the shift clock, MSK. When data is written to the MWDAT register, eight or sixteen MSK clocks, depending on the mode selected, are generated to shift the 8 or 16 bits of data, and then MSK goes idle again. The MSK idle state can be either high or low, depending on the SCIDL bit. End of Transfer MSK Shift Out Data Out MSB MSB - 1 MSB - 2 Bit 1 Bit 0 (LSB) MSB - 1 MSB - 2 Bit 1 Bit 0 (LSB) Sample Point Data In MSB DS069 Figure 85.
CP3BT26 23.3 SLAVE MODE 23.4 In Slave mode, the MSK pin is an input for the shift clock MSK. MDIDO is placed in TRI-STATE mode when MWCS is inactive. Data transfer is enabled when MWCS is active. INTERRUPT GENERATION Interrupts may be enabled for any of the conditions shown in Table 73. Table 73 Microwire Interrupt Trigger Condition The slave starts driving MDIDO when MWCS is active. The most significant bit (lower byte in 8-bit mode or upper byte in 16-bit mode) is output onto the MDIDO pin first.
MICROWIRE INTERFACE REGISTERS 23.5.2 MICROWIRE Control Register (MWCTL1) Software interacts with the Microwire interface by accessing The MWCTL1 register is a word-wide, read/write register used to control the Microwire module. To avoid clock glitchthe Microwire registers. There are three such registers: es, the MWEN bit must be clear while changing the states Table 74 Microwire Interface Registers of any other bits in the register. At reset, all non-reserved bits are cleared.
CP3BT26 EIO EIR EIW SCM SCIDL SCDV MWDAT register is transmitted on MDIDO, whether or not the data is valid. 0 – Echo back disabled. 1 – Echo back enabled. The Enable Interrupt on Overrun bit enables or disables the overrun error interrupt. When set, an interrupt is generated when the Receive Overrun Error bit (MWSTAT.OVR) is set. Otherwise, no interrupt is generated when an overrun error occurs. This bit must only be enabled in master mode. 0 – Disable overrun error interrupts.
CP3BT26 24.0 ACCESS.bus Interface The ACCESS.bus interface module (ACB) is a two-wire serial interface compatible with the ACCESS.bus physical layer. It permits easy interfacing to a wide range of low-cost memories and I/O devices, including: EEPROMs, SRAMs, timers, A/D converters, D/A converters, clock chips, and peripheral drivers. It is compatible with Intel’s SMBus and Philips’ I2C bus.
CP3BT26 Acknowledge Cycle Addressing Transfer Formats The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device (Figure 93). Each device on the bus has a unique address. Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA signal, once it recognizes its address.
ACB FUNCTIONAL DESCRIPTION 4. If the requested direction is transmit, and the start transaction was completed successfully (i.e., neither the ACBST.NEGACK nor ACBST.BER bit is set, and no other master has accessed the device), the ACBST.SDAST bit is set to indicate that the module is waiting for service. 5. If the requested direction is receive, the start transaction was completed successfully, and the ACBCTL1.STASTRE bit is clear, the module starts receiving the first byte automatically. 6.
CP3BT26 Master Bus Stall 24.2.2 The ACB module can stall the ACCESS.bus between transfers while waiting for the core’s response. The ACCESS.bus is stalled by holding the SCL signal low after the acknowledge cycle. Note that this is interpreted as the beginning of the following bus operation. Software must make sure that the next operation is prepared before the bit that causes the bus stall is cleared. A slave device waits in Idle mode for a master to initiate a bus transaction.
24.3.1 When this device is in Power Save, Idle, or Halt mode, the ACB module is not active but retains its status. If the ACB is enabled (ACBCTL2.ENABLE = 1) on detection of a Start Condition, a wake-up signal is issued to the MIWU module. Use this signal to switch this device to Active mode. The ACBSDA register is a byte-wide, read/write shift register used to transmit and receive data. The most significant bit is transmitted (received) first and the least significant bit is transmitted (received) last.
CP3BT26 NEGACK BER SDAST SLVSTP The Negative Acknowledge bit is set by hardware when a transmission is not acknowledged on the ninth clock. (In this case, the SDAST bit is not set.) Writing 1 to NEGACK clears it. It is also cleared when the module is disabled. Writing 0 to the NEGACK bit is ignored. 0 – No transmission not acknowledged condition. 1 – Transmission not acknowledged. The Bus Error bit is set by the hardware when a Start or Stop Condition is detected during data transfer (i.e.
TSDA TGSCL The Global Call Match bit is set in slave mode when the ACBCTL1.GCMEN bit is set and the address byte (the first byte transferred after a Start Condition) is 00h. It is cleared by a Start Condition or repeated Start and Stop Condition (including illegal Start or Stop Condition). 0 – No global call match occurred. 1 – Global call match occurred. The Test SDA bit samples the state of the SDA signal.
CP3BT26 INTEN ACK GCMEN NMINTE STASTRE The Interrupt Enable bit controls generating ACB interrupts. When the INTEN bit is cleared ACB interrupt is disabled. When the INTEN bit is set, interrupts are enabled. 0 – ACB interrupts disabled. 1 – ACB interrupts enabled. An interrupt is generated (the interrupt signals to the ICU is high) on any of the following events: An address MATCH is detected (ACBST.NMATCH = 1) and the NMINTE bit is set. A Bus Error occurs (ACBST.BERR = 1).
24.4 ACB Own Address Register 1 (ACBADDR1) The ACBADDR1 register is a byte-wide, read/write register that holds the module’s first ACCESS.bus address. After reset, its value is undefined. 7 6 SAEN ADDR ADDR The Own Address field holds the first 7-bit ACCESS.bus address of this device. When in slave mode, the first 7 bits received after a Start Condition are compared to this field (first bit received to bit 6, and the last to bit 0).
CP3BT26 24.4.1 Avoiding Bus Error During Write Transaction A Bus Error (BER) may occur during a write transaction if the data register is written at a very specific time. The module generates one system-clock cycle setup time of SDA to SCL vs. the minimum time of the clock divider ratio. The problem can be masked within the driver by dynamically dividing-by-half the SCL width immediately after the slave address is successfully sent and before writing to the ACBSDA register.
|= ACBSTOP; /* Send STOP bit /* Return success status.... */ */ return (ACB_NOERR); } /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ; NAME: ACBStartX Initiates an ACB bus transaction by sending the Start bit, followed by the Slave address ; and R/W flag. Checks for any ACB errors throughout this sequence and returns status.
CP3BT26 25.0 Timing and Watchdog Module The Timing and Watchdog Module (TWM) generates the clocks and interrupts used for timing periodic functions in the system; it also provides Watchdog protection over software execution. Slow Clock period. The prescaled clock signal is called T0IN. The TWM is designed to provide flexibility in system design by configuring various clock ratios and by selecting the Watchdog clock source.
WATCHDOG OPERATION 25.3.2 The Watchdog is an 8-bit down counter that operates on the rising edge of a specified clock source. At reset, the Watchdog is disabled; it does not count and no Watchdog signal is generated. A write to either the Watchdog Count (WDCNT) register or the Watchdog Service Data Match (WDSDM) register starts the counter. The Watchdog counter counts down from the value programmed in the WDCNT register. Once started, only a reset can stop the Watchdog from operating.
CP3BT26 25.4.1 Timer and Watchdog Configuration Register (TWCFG) 25.4.2 The TWCFG register is a byte-wide, read/write register that selects the Watchdog clock input and service method, and also allows the Watchdog registers to be selectively locked. A locked register cannot be read or written; a read operation returns unpredictable values and a write operation is ignored. Once a lock bit is set, that bit cannot be cleared until the device is reset.
TWMT0 Control and Status Register (T0CSR) 25.4.5 The T0CSR register is a byte-wide, read/write register that controls Timer T0 and shows its current status. At reset, the non-reserved bits of the register are cleared. The register format is shown below. 7 5 Reserved 4 3 FRZT0E WDLTD 2 1 0 T0INTE TC RST Watchdog Count Register (WDCNT) The WDCNT register is a byte-wide, write-only register that holds the value that is loaded into the Watchdog counter each time the Watchdog is serviced.
Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a specified width and duty cycle, and which also provides a general-purpose timer/counter. Dual-Input Capture mode, which measures the elapsed time between occurrences of external events, and which also provides a general-purpose timer/counter. Dual Independent Timer mode, which generates system timing signals or counts occurrences of external events. The timer unit uses two I/O pins, called TA and TB.
External Event Clock There are two clock source selectors that allow software to The TB I/O pin can be configured to operate as an external independently select the clock source for each of the two event input clock for either of the two 16-bit counters. This 16-bit counters from any one of the following sources: input can be programmed to detect either rising or falling edges. The minimum pulse width of the external signal is No clock (which stops the counter) one System Clock cycle.
CP3BT26 26.2.1 Mode 1: Processor-Independent PWM The timer can be configured to toggle the TA output bit on Mode 1 is the Processor-Independent Pulse Width Modula- each underflow. This generates a clock signal on the TA outtion (PWM) mode, which generates pulses of a specified put with the width and duty cycle determined by the values width and duty cycle, and which also provides a separate stored in the TCRA and TCRB registers.
Mode 2: Dual Input Capture The values captured in the TCRA register at different times Mode 2 is the Dual Input Capture mode, which measures reflect the elapsed time between transitions on the TA pin. the elapsed time between occurrences of external events, The same is true for the TCRB register and the TB pin. The and which also provides a separate general-purpose timer/ input signal on the TA or TB pin must have a pulse width equal to or greater than one System Clock cycle. counter.
CP3BT26 26.2.3 Mode 3: Dual Independent Timer/Counter Mode 3 is the Dual Independent Timer mode, which generates system timing signals or counts occurrences of external events. Figure 102 is a block diagram of the Multi-Function Timer configured to operate in Mode 3. The timer is configured to operate as a dual independent system timer or dual external event counter. In addition, Timer/Counter 1 can generate a 50% duty cycle PWM signal on the TA pin.
Mode 4: Input Capture Plus Timer Mode 4 is the Single Input Capture and Single Timer mode, which provides one external event counter and one system timer. Figure 103 is a block diagram of the Multi-Function Timer configured to operate in Mode 4. This mode offers a combination of Mode 3 and Mode 2 functions. Timer/Counter 1 is used as a system timer as in Mode 3 and Timer/Counter 2 is used as a capture timer as in Mode 2, but with a single input rather than two inputs.
CP3BT26 26.3 TIMER INTERRUPTS 26.4 The Multi-Function Timer unit has four interrupt sources, designated A, B, C, and D. Interrupt sources A, B, and C are mapped into a single system interrupt called Timer Interrupt 1, while interrupt source D is mapped into a system interrupt called Timer Interrupt 2. Each of the four interrupt sources has its own enable bit and pending bit. The enable bits are named TAIEN, TBIEN, TCIEN, and TDIEN. The pending bits are named TAPND, TBPND, TCPND, and TDPND.
TIMER REGISTERS 26.5.2 Table 79 lists the CPU-accessible registers used to control the Multi-Function Timers.
CP3BT26 26.5.5 Reload/Capture A Register (TCRA) TAEN The TCRA register is a word-wide, read/write register that holds the reload or capture value for Timer/Counter 1. The register contents are not affected by a reset and are unknown after power-up. 15 0 TCRA 26.5.6 TBEN Reload/Capture B Register (TCRB) The TCRB register is a word-wide, read/write register that holds the reload or capture value for Timer/Counter 2. The register contents are not affected by a reset and are unknown after power-up.
Timer Interrupt Control Register (TICTL) TBIEN The TICTL register is a byte-wide, read/write register that contains the interrupt enable bits and interrupt pending bits for the four timer interrupt sources, designated A, B, C, and D. The condition that causes each type of interrupt depends on the operating mode, as shown in Table 77. This register is cleared upon reset. The register format is shown below.
CP3BT26 27.0 Versatile Timer Unit (VTU) The Versatile Timer Unit (VTU) contains four fully indepen- The VTU controls a total of eight I/O pins, each of which dent 16-bit timer subsystems. Each timer subsystem can can function as either: operate either as dual 8-bit PWM timers, as a single 16-bit — PWM output with programmable output polarity PWM timer, or as a 16-bit counter with 2 input capture chan— Capture input with programmable event detection and nels.
Dual 8-bit PWM Mode The period of the PWM output waveform is determined by Each timer subsystem may be configured to generate two the value of the PERCAPx register. The TIOx output starts fully independent PWM waveforms on the respective TIOx at the default value as programmed in the IOxCTL.PxPOL pins. In this mode, the counter COUNTx is split and oper- bit. Once the counter value reaches the value of the period ates as two independent 8-bit counters.
CP3BT26 The two I/O pins associated with a timer subsystem function as independent PWM outputs in the dual 8-bit PWM mode. If a PWM timer is stopped using its associated MODE.TxRUN bit the following actions result: Figure 107 illustrates the configuration of a timer subsystem while operating in 16-bit PWM mode. The numbering in Figure 107 refers to timer subsystem 1 but equally applies to the other three timer subsystems.
7 terrupt pending bits are denoted IxAPD through IxDPD where “x” relates to the specific timer subsystem. There is one system level interrupt request for each of the four timer subsystems. Figure 109 illustrates the interrupt structure of the versatile timer module.
CP3BT26 27.2 VTU REGISTERS 27.2.1 Mode Control Register (MODE) The VTU contains a total of 19 user accessible registers, as The MODE register is a word-wide read/write register which listed in Table 81. All registers are word-wide and are initial- controls the mode selection of all four timer subsystems. ized to a known value upon reset. All software accesses to The register is clear after reset. the VTU registers must be word accesses.
I/O Control Register 1 (IO1CTL) 27.2.3 The I/O Control Register 1 (IO1CTL) is a word-wide read/ write register. The register controls the function of the I/O pins TIO1 through TIO4 depending on the selected mode of operation. The register is clear after reset. 7 6 P2POL 15 P4POL CxEDG 4 3 C2EDG 14 P1POL 12 C4EDG 2 11 P3POL The IO2CTL register is a word-wide read/write register.
CP3BT26 IxCEN The Timer x Interrupt C Enable bit controls interrupt requests triggered on the corresponding IxCPD bit being set. The associated IxCPD bit will be updated regardless of the value of the IxCEN bit. 0 – Disable system interrupt request for the IxCPD pending bit. 1 – Enable system interrupt request for the IxCPD pending bit. Timer x Interrupt D Enable bit controls interrupt requests triggered on the corresponding IxDPD bit being set.
Counter Register n (COUNTx) 27.2.10 Duty Cycle/Capture Register n (DTYCAPx) The Counter (COUNTx) registers are word-wide read/write registers. There are a total of four registers called COUNT1 through COUNT4, one for each of the four timer subsystems. Software may read the registers at any time. Reading the register will return the current value of the counter. The register may only be written if the counter is stopped (i.e. if both TxRUN bits associated with a timer subsystem are clear).
CP3BT26 28.0 Register Map Table 82 is a detailed memory map showing the specific memory address of the memory, I/O ports, and registers. The table shows the starting address, the size, and a brief description of each memory block and register. For detailed information on using these memory locations, see the applicable sections in the data sheet. All addresses not listed in the table are reserved and must not be read or written. An attempt to access an unlisted address will have unpredictable results.
Address Access Type WTPTC_1SLOT Word 0E F1B0h Write-Only WTPTC_3SLOT Word 0E F1B2h Write-Only WTPTC_5SLOT Word 0E F1B4h Write-Only SEQ_RESET Byte 0E F1B6h Write-Only SEQ_CONTINUE Byte 0E F1B7h Write-Only RX_STATUS Byte 0E F1B8h Read-Only CHIP_ID Byte 0E F1BAh Read-Only INT_VECTOR Byte 0E F1BCh Read-Only SYSTEM_CLK_EN Byte 0E F1BEh Write-Only LINKTIMER_WR_RD Word 0E F1C0h Read-Only LINKTIMER_SELECT Byte 0E F1C2h Read-Only LINKTIMER_STATUS_EXP_FLAG Byte 0E F1C4h
CP3BT26 Size Address Access Type Value After Reset DMAEV Byte FF FDAAh Read/Write 00h DMAMSK Byte FF FDACh Read/Write 00h MIR Byte FF FDAEh Read/Write 1Fh DMACNT Byte FF FDB0h Read/Write 00h DMAERR Byte FF FDB2h Read/Write 00h EPC0 Byte FF FDC0h Read/Write 00h TXD0 Byte FF FDC2h Read/Write XXh TXS0 Byte FF FDC4h Read/Write 08h TXC0 Byte FF FDC6h Read/Write 00h RXD0 Byte FF FDCAh Read/Write XXh RXS0 Byte FF FDCCh Read/Write 00h RXC0 Byte FF FDCEh
Size Address Access Type Value After Reset Comments CAN Module Message Buffers CMB0_CNSTAT Word 0E F000h Read/Write XXXXh CMB0_TSTP Word 0E F002h Read/Write XXXXh CMB0_DATA3 Word 0E F004h Read/Write XXXXh CMB0_DATA2 Word 0E F006h Read/Write XXXXh CMB0_DATA1 Word 0E F008h Read/Write XXXXh CMB0_DATA0 Word 0E F00Ah Read/Write XXXXh CMB0_ID0 Word 0E F00Ch Read/Write XXXXh CMB0_ID1 Word 0E F00Eh Read/Write XXXXh CMB1 8-word 0E F010h– 0E F01Fh Read/Write XXXXh Sam
CP3BT26 Register Name Size Address Access Type Value After Reset CAN Registers CGCR Word 0E F100h Read/Write 0000h CTIM Word 0E F102h Read/Write 0000h GMSKX Word 0E F104h Read/Write 0000h GMSKB Word 0E F106h Read/Write 0000h BMSKX Word 0E F108h Read/Write 0000h BMSKB Word 0E F10Ah Read/Write 0000h CIEN Word 0E F10Ch Read/Write 0000h CIPND Word 0E F10Eh Read Only 0000h CICLR Word 0E F110h Write Only 0000h CICEN Word 0E F112h Read/Write 0000h CSTPND Wor
Address Access Type Value After Reset BLTC1 Word FF F830h Read/Write 0000h BLTR1 Word FF F834h Read/Write 0000h DMACNTL1 Word FF F83Ch Read/Write 0000h DMASTAT1 Byte FF F83Eh Read/Write 00h ADCA2 Double Word FF F840h Read/Write 0000 0000h ADRA2 Double Word FF F844h Read/Write 0000 0000h ADCB2 Double Word FF F848h Read/Write 0000 0000h ADRB2 Double Word FF F84Ch Read/Write 0000 0000h BLTC2 Word FF F850h Read/Write 0000h BLTR2 Word FF F854h Read/Write 0000h
CP3BT26 Register Name Size Address Access Type Value After Reset System Configuration MCFG Byte FF F910h Read/Write 00h DBGCFG Byte FF F912h Read/Write 00h MSTAT Byte FF F914h Read Only ENV2:0 pins SWRESET Byte FF F918h Write Only N/A Flash Program Memory Interface FMIBAR Word FF F940h Read/Write 0000h FMIBDR Word FF F942h Read/Write 0000h FM0WER Word FF F944h Read/Write 0000h FM1WER Word FF F946h Read/Write 0000h FMCTRL Word FF F94Ch Read/Write 0000h FMSTA
Address Access Type Value After Reset FSMTRAN Byte FF F754h Read/Write 30h FSMPROG Byte FF F756h Read/Write 16h FSMPERASE Byte FF F758h Read/Write 04h FSMMERASE0 Byte FF F75Ah Read/Write EAh FSMEND Byte FF F75Eh Read/Write 18h FSMMEND Byte FF F760h Read/Write 3Ch FSMRCV Byte FF F762h Read/Write 04h FSMAR0 Word FF F764h Read Only FSMAR1 Word FF F766h Read Only FSMAR2 Word FF F768h Read Only Comments CVSD/PCM Converter CVSDIN Word FF FC20h Write Only 0000
CP3BT26 Register Name Size Address Access Type Value After Reset Comments Power Management PMMCR Byte FF FC60h Read/Write 00h PMMSR Byte FF FC62h Read/Write 0000 0XXXb Multi-Input Wake-Up 0 WK0EDG Word FF FC80h Read/Write 00h WK0ENA Word FF FC82h Read/Write 00h WK0ICTL1 Word FF FC84h Read/Write 00h WK0ICTL2 Word FF FC86h Read/Write 00h WK0PND Word FF FC88h Read/Write 00h WK0PCL Word FF FC8Ah Write Only XXh WK0IENA Word FF FC8Ch Read/Write 00h Bits may only
Address Access Type Value After Reset PCDIR Byte FF FB12h Read Only 00h PCDIN Byte FF FB14h Read/Write XXh PCDOUT Byte FF FB16h Read/Write XXh PCWPU Byte FF FB18h Read/Write 00h PCHDRV Byte FF FB1Ah Read/Write 00h PCALTS Byte FF FB1Ch Read/Write 00h PEALT Byte FF FCC0h Read/Write 00h PEDIR Byte FF FCC2h Read/Write 00h PEDIN Byte FF FCC4h Read Only XXh PEDOUT Byte FF FCC6h Read/Write XXh PEWPU Byte FF FCC8h Read/Write 00h PEHDRV Byte FF FCCAh Read/
CP3BT26 Size Address Access Type Value After Reset PJDIN Byte FF F344h Read Only XXh PJDOUT Byte FF F346h Read/Write XXh PJWPU Byte FF F348h Read/Write 00h PJHDRV Byte FF F34Ah Read/Write 00h PJALTS Byte FF F34Ch Read/Write 00h Register Name Comments Advanced Audio Interface ARFR Word FF FD40h Read Only 0000h ARDR0 Word FF FD42h Read Only 0000h ARDR1 Word FF FD44h Read Only 0000h ARDR2 Word FF FD46h Read Only 0000h ARDR3 Word FF FD48h Read Only 0000h
Size Address Access Type Value After Reset Comments Microwire/SPI Interface MWDAT Word FF F3A0h Read/Write XXXXh MWCTL1 Word FF F3A2h Read/Write 0000h MWSTAT Word FF F3A4h Read Only All implemented bits are 0 UART0 U0TBUF Byte FF F200h Read/Write XXh U0RBUF Byte FF F202h Read Only XXh U0ICTRL Byte FF F204h Read/Write 01h U0STAT Byte FF F206h Read only 00h U0FRS Byte FF F208h Read/Write 00h U0MDSL1 Byte FF F20Ah Read/Write 00h U0BAUD Byte FF F20Ch Read/Wri
CP3BT26 Register Name Size Address Access Type Value After Reset Comments UART2 U2TBUF Byte FF F240h Read/Write XXh U2RBUF Byte FF F242h Read Only XXh U2ICTRL Byte FF F244h Read/Write 01h U2STAT Byte FF F246h Read only 00h U2FRS Byte FF F248h Read/Write 00h U2MDSL1 Byte FF F24Ah Read/Write 00h U2BAUD Byte FF F24Ch Read/Write 00h U2PSR Byte FF F24Eh Read/Write 00h U2OVR Byte FF F250h Read/Write 00h U2MDSL2 Byte FF F252h Read/Write 00h U2SPOS Byte FF
Size Address Access Type Value After Reset Comments ACCESS.
CP3BT26 Register Name Size Address Access Type Value After Reset Versatile Timer Unit MODE Word FF FF80h Read/Write 0000h IO1CTL Word FF FF82h Read/Write 0000h IO2CTL Word FF FF84h Read/Write 0000h INTCTL Word FF FF86h Read/Write 0000h INTPND Word FF FF88h Read/Write 0000h CLK1PS Word FF FF8Ah Read/Write 0000h COUNT1 Word FF FF8Ch Read/Write 0000h PERCAP1 Word FF FF8Eh Read/Write 0000h DTYCAP1 Word FF FF90h Read/Write 0000h COUNT2 Word FF FF92h Read/Writ
Size Address Access Type Value After Reset Comments RNG RNGCST Word FF F280h Read/Write 0000h RNGD Word FF F282h Read/Write 0000h RNGDIVH Word FF F284h Read/Write 0000h RNGDIVL Word FF F286h Read/Write 0000h 229 www.national.
CP3BT26 29.0 Register Bit Fields The following tables show the functions of the bit fields of the device registers. For more information on using these registers, see the detailed description of the applicable function elsewhere in this data sheet.
7 6 5 4 WTPTC_5SLOT[15:8] 3 2 1 0 WTPTC_5SLOT[15:8] SEQ_RESET Reserved SEQ_RESET SEQ_CONTINUE Reserved SEQ_ CONTINUE RX_STATUS Reserved HEC Error CHIP_ID Header Error Correction AM_ ADDR Error Payload CRC Error Payload Error Correction Reserved INT_VECTOR[7:0] SYSTEM_CLK_EN Reserved CLK_EN3 CLK_EN2 LINK_TIMER_WR_RD[7:0] LINKTIMER_WR_RD[7:0] LINK_TIMER_WR_RD[15:8] LINKTIMER_WR_RD[15:8] LINK_TIMER_SELECT Reserved LINK_TIMER_STATUS_ EXP_FLAG LINKTIMER_SELECT LINK_ TIMER _WRIT
CP3BT26 USB Registers 7 6 5 4 3 2 1 NAKEV OUT IN NAKMSK OUT IN 0 FWEV RXWARN[3:1] Reserved TXWARN[3:1] Reserved FWMSK RXWARN[3:1] Reserved TXWARN[3:1] Reserved FNH MF UL RFC Reserved FNL FN[7:0] DMACNTRL DEN DMAEV IGNRXTGL Reserved DMAMSK DTGL ADMA DMOD NTGL ARDY DSIZ DCNT DERR DSHLT DSIZ DCNT DERR DSHLT Reserved TX_EN Reserved MIR DCOUNT DMAERR AEH EPC0 STALL DMAERRCNT DEF Reserved TXD0 EP TXFD TXS0 Reserved TXC0 ACK_STAT TX_DONE Red TCOU
7 6 5 4 RXS2 RX_ERR SETUP TOGGLE RX_LAST RXC2 Reserved EPC5 STALL RFWL Reserved 3 Reserved ISO RCOUNT IGN_ SETUP FLUSH EPC6 STALL TFWL Reserved RFF ISO FLUSH TOGGLE LAST EP_EN TX_EN EP RXFD RXS3 RX_ERR RXC3 Reserved 15 CGCR 14 SETUP TOGGLE RFWL[1:0] 13 12 Reserved CTIM RX_LAST Reserved 11 10 EIT 9 RCOUNT IGN_ SETUP FLUSH 8 7 DIAG INTE LOOP IGN EN RNAL BACK ACK PSC[6:0] GMSKB 6 5 LO DD IR SJW[1:0] Reserved 4 3 RX_EN 2 1 RTR TSEG2[2:0] IDE GM[
CP3BT26 CAN Memory Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMBn.ID1 XI28 XI27 XI26 XI25 XI24 XI23 XI22 XI21 XI20 XI19 XI18 SRR IDE ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR XI17 XI16 XI15 CMBn.ID0 XI14 XI13 XI12 XI11 XI10 XI1 CMBn.DATA0 Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 CMBn.
MCFG 7 6 5 MEM_IO_ MISC_IO_ SPEED SPEED Reserved DBGCFG 4 3 2 USB_ ENABLE SCLKOE 1 MSTAT ISPRST BIU Registers 15 DPGM BUSY WDRST Reserved 12 11 10 9 8 BCFG PGMBUSY 7 6 0 MCLKOE PLLCLKOE Reserved 4 EXIOE FREEZE ON OENV1 OENV0 OENV2 5 3 2 1 Reserved IOCFG Reserved IPST Res. BW Reserved HOLD WAIT Reserved FRE IPRE IPST Res. BW WBR RBE HOLD WAIT SZCFG1 Reserved FRE IPRE IPST Res. BW WBR RBE HOLD WAIT SZCFG2 Reserved FRE IPRE IPST Res.
CP3BT26 Flash Program Memory Interface Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 FMPROG Reserved FTPROG FMPERASE Reserved FTPER FMMERASE0 Reserved FTMER FMEND Reserved FTEND FMMEND Reserved FTMEND FMRCV Reserved FTRCV FMAR0 FMAR1 FSMIBAR RDPROT WRPROT ISPE EMPTY BOOTAREA CADR15:0 15 14 13 12 11 10 9 8 7 6 5 Reserved FSM0WER FM0WE FSM1WER FM1WE FSM2WER FM2WE FSM3WER FM3WE Reserved FSMSTAT MER PER 3 2 1 PE 0 IENP DIS LOW Res.
15 14 13 12 11 10 9 FSMAR0 FSMAR1 8 6 5 4 3 2 RDPROT WRPROT EMPTY BOOTAREA CADR15:0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PCMIN PCMOUT PCMOUT LOGIN Reserved LOGIN LOGOUT Reserved LOGOUT LINEARIN LINEARIN LINEAROUT LINEAROUT PCM CO NV Reserved CVSTAT CVSD CONV Reserved CVTEST CVS DMA DMA DMA DMA CVS PCM CLK DER PI PO CI CO DINT INT EN RINT CV EN PCM CVN INT F CV NE CVOUTST CVINST Reserved RT TB CVRADD CVRDAT CVRDAT CVDECOUT CVDECOUT CVENCIN CVENCI
CP3BT26 PMM Register PMMCR 7 6 5 4 3 2 1 0 HCCH HCCM DHC DMC WBPSM HALT IDLE PSM OHC OMC OLC PMMSR Reserved MIWU16 Registers 15 14 13 12 11 10 9 8 7 WKEDG WKED WKENA WKEN WKINTR6 WKINTR5 WKINTR4 6 WKINTR3 5 4 3 2 1 0 WKICTL1 WKINTR7 WKINTR2 WKINTR1 WKINTR0 WKICTL2 WKINTR15 WKINTR14 WKINTR13 WKINTR12 WKINTR11 WKINTR10 WKINTR9 WKINTR8 WKPND WKPD WKPCL WKCL WKIENA WKIEN GPIO Registers 7 6 5 4 3 2 1 PxALT Px Pins Alternate Function Enable P
15 14 13 12 11 10 9 8 7 6 5 4 3 ATDR1 ATDH ATDL ATDR2 ATDH ATDL ATDR3 ATDH ATDL AGCR CLK EN AAI IOM2 IFS EN FSL TX EIC CTF CRF IEBC FSS IEFS TX IC RX EIC AISCR Reserved ARSCR RXFWM RXDSA ATSCR TXFWM TXDSA ACCR RX IC TX EIP TX IP Reserved ICU Registers ACO 7 6 Reserved 0 0 LPB DWL ASS TX EIE TX IE RX IE RXSA RXO RXE RXF RX AF TXSA TXU TXF TXE TXAE 5 4 RMD 3 2 1 0 INTVECT[5:0] ISTAT1 IST(31:16) IENAM0 IENA(15:0) IENAM1 IENA(31:16) 6 CSS
CP3BT26 MWSPI16 Registers 15 . . .
15 MODE 14 13 12 11 T8 T7 RUN RUN TMOD4 10 9 8 7 T6 T5 RUN RUN TMOD3 6 TMOD2 5 4 T4 T3 RUN RUN 3 2 1 0 T2 T1 RUN RUN TMOD1 IO1CTL P4 POL C4EDG P3 POL C3EDG P2 POL C2EDG P1 POL C1EDG IO2CTL P7 POL C7EDG P6 POL C6EDG P5 POL C5EDG P5 POL C5EDG INTCTL I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN INTPND I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD CLK1PS C2PRSC C1
CP3BT26 RNG Registers RNGCST 15 14 13 12 11 10 9 8 Reserved RNGDIVL www.national.
30.1 ABSOLUTE MAXIMUM RATINGS If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply voltage (VCC) All input and output voltages with respect to GND* TBD -0.5V to IOVCC + 0.5V ESD protection level 2 kV (Human Body Model) Allowable sink/source current per signal pin 30.
CP3BT26 Symbol Parameter Conditions IO(Off) Output Leakage Current (I/O pins in input mode) 0V ≤ Vout ≤ Vcc Icca1 Digital Supply Current Active Mode b Iccprog Min -2.0 Max Units 2.0 µA Vcc = 2.75V, IOVcc=3.63V 20 mA Digital Supply Current Active Mode c Vcc = 2.75V, IOVcc = 3.63V 20 mA Iccps Digital Supply Current Power Save Mode d Vcc = 2.75V, IOVcc =3.63V 4 mA Iccid Digital Supply Current Idle Mode e Vcc = 2.75V, IOVcc = 3.
USB TRANSCEIVER ELECTRICAL CHARACTERISTICS (Temperature: -40°C ≤ TA ≤ +85°C) Symbol Parameter Conditions Max Units -0.2 0.2 V VDI Differential Input Sensitivity VCM Differential Common Mode Range 0.8 2.5 V VSE Single-Ended Receiver Threshold 0.8 2.0 V VOL Output Low Voltage 0.3 V VOH Output High Voltage VOZ TRI-STATE Data Line Leakage CTRN Transceiver Capacitance 30.4 (D+) - (D-) Min RL = 1.5 kohm to 3.6V 2.8 0V < VIN < 3.
CP3BT26 30.
OUTPUT SIGNAL LEVELS The RESET and NMI input pins are active during the Power Save mode. In order to guarantee that the Power Save curAll output signals are powered by the digital supply (VCC). rent not exceed 1 mA, these inputs must be driven to a voltTable 83 summarizes the states of the output signals during age lower than 0.5V or higher than VCC - 0.5V. An input the reset state (when VCC power exists in the reset state) voltage between 0.5V and (VCC - 0.
CP3BT26 tX1p X1CKI tX1h tX1l tX2p X2CKI tX2h tX2l DS095 Figure 110. Clock Timing CLK tlS tlH tIW NMI DS096 Figure 111. NMI Signal Timing CLK tRST RESET DS097 Figure 112. Non-Power-On Reset 0.9 VCC VCC 0.1 VCC tR DS115 Figure 113. Power-On Reset www.national.
CP3BT26 30.
CP3BT26 30.
CP3BT26 30.
CP3BT26 SCK 0 1 2 SFS STD 0 1 tTDV DS117 Figure 117. SRCLK 0 Transmit Timing, Short Frame Sync 1 2 N SRFS tFSVL tFSVH SRD 0 tRDH tRDS DS118 Figure 118. SCK 1 0 Receive Timing, Long Frame Sync 1 2 N SFS STD 0 1 tTDV DS119 Figure 119. www.national.
CP3BT26 30.11 MICROWIRE/SPI TIMING Table 88 Microwire/SPI Signals Symbol Figure Description Reference Min (ns) Max (ns) Microwire/SPI Input Signals tMSKh 120 Microwire Clock High At 2.0V (both edges) 80 - tMSKl 120 Microwire Clock Low At 0.
CP3BT26 Table 88 Microwire/SPI Signals Symbol Figure tMDOv tMITOp Description 120 Microwire Data Out Valid 124 MDODI to MDIDO (slave only) Reference Min (ns) Max (ns) Normal Mode: After FE on MSK 25 Alternate Mode: After RE on MSK Propagation Time Value is the same in all clocking modes of the Microwire 25 tMSKp MSK tMSKh tMSKs Data In tMSKl tMSKhd msb tMDls MDIDO (slave) lsb tMDlh msb lsb tMDOf tMDOv tMDOff tMDOh MDODI (master) msb lsb tMSKd MCS (slave) tMCSs tMCSh Figu
CP3BT26 tMSKp MSK tMSKh tMSKh tMSKhd tMSKs Data In msb tMDls MDIDO (slave) lsb tMDlh msb lsb tMDOv tMDOf tMDOf tMDOh MDODO (master) msb lsb MCS (slave) tMCSs tMCSh DS102 Figure 121. Microwire Transaction Timing, Normal Mode, SCIDL = 1 255 www.national.
CP3BT26 tMSKp MSK tMSKhd tMSKs tMSKh Data In tMSKl msb tMDls MDIDO (slave) lsb tMDlh msb lsb tMDOv tMDOf tMDOf tMDOh MDODO (master) msb lsb MCS (slave) tMCSs Figure 122. www.national.
CP3BT26 tMSKp MSK tMSKhd tMSKs tMSKh Data In tMSKh msb lsb tMDlh tMDls MDIDO (slave) msb lsb tMDOf tMDOv tMDOff tMDOh MDODI (master) msb lsb tSKd MCS (slave only) tMCSs Figure 123. tMCSh DS104 Microwire Transaction Timing, Alternate Mode, SCIDL = 1 tMSKp MSK tMSKhd tMSKs tMSKh MDODI (slave) tMSKl Dl msb tMDls Dl lsb tMDlh tMITOp MDIDO (slave) tMITOp DO msb DO lsb tMDOnf tMDOf MCS tMCSs tMCSh DS105 Figure 124.
CP3BT26 30.12 ACCESS.BUS TIMING Table 89 ACCESS.bus Signals Symbol Figure Description Reference Min (ns) Max (ns) tSCLhigho - ACCESS.
0.7VCC 0.3VCC 0.3VCC CP3BT26 0.7VCC SDA tSDAr tSDAf 0.7VCC 0.7VCC 0.3VCC 0.3VCC SCL tSCLr tSCLf Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. DS106 Figure 125. ACB Signals (SDA and SCL) Timing Stop Condition Start Condition SDA tDLCs SCL tCSTOs tBUF tCSTRh Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. DS107 Figure 126.
CP3BT26 SDA tSDAsi SCL tSCAvo tSDAh tCSLlow tSCLhigh Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. unless the parameter already includes the suffix. DS109 Figure 128. www.national.
CP3BT26 30.13 USB PORT AC CHARACTERISTICS Table 90 USB Port Signals Symbol Conditionsa Description Min Typ Max Units TR Rise Time CL = 50 pF 4 20 ns TF Fall Time CL = 50 pF 4 20 ns TRFM Fall/Rise Time Matching (TR/TF) CL = 50 pF 90 110 % VCRS Output Signal Crossover Voltage CL = 50 pF 1.3 2.0 V ZDRV Driver Output Impedance CL = 50 pF 28 43 ohms a. Waveforms measured at 10% to 90%. 30.
CP3BT26 30.15 VERSATILE TIMING UNIT (VTU) TIMING Table 92 Versatile Timing Unit Input Signals Symbol Figur e tTIOH 129 TIOx Input High Time Rising Edge (RE) on CLK tTIOL 129 TIOx Input Low Time RE on CLK Description Reference Min (ns) 1.5 × TCLK + 5ns 1.5 × TCLK + 5ns CLK tTIOL tTIOH TIOx DS110 Figure 130. Versatile Timing Unit Input Timing www.national.
CP3BT26 30.
CP3BT26 Normal Read Bus State T1 Early Write T2 T1 T2 Normal Read T3 T1 T2 CLK t4 t4, t12 t5, t12 t5, t12 A[21:0] A22 ('13 only) SELx t5, t12 t5, t12 SELy (y ≠ x) t2 t3 D[15:0] In t1 t8, t12 Out In t5, t12 t5, t12 RD t9 t6, t13 t6, t13 WR[1:0] DS124 Figure 131. www.national.
Bus State T1 Late Write T2 T1 CP3BT26 Normal Read Normal Read T2 T1 T2 CLK t4, t12 t4, t12 A[21:0] A22 ('13 only) t5, t12 t5, t12 SELx (y ≠ x) t11 SELy (y ≠ x) t5, t12 t5, t12 t3 D[15:0] t8, t12 In Out In t10 RD t9 t5, t12 t5, t12 t6, t13 WR[1:0] t6, t13 DS125 Figure 132. Late Write Between Normal Read Cycles (No Wait States) 265 www.national.
CP3BT26 Normal Read T1 Bus State Normal Read T2 T2B T1 T2 T2B CLK t4, t12 t4, t12 t4 A[21:0] A22 ('13 only) t5, t12 t5, t12 SELx (y ≠ x) t5, t12 SELy (y ≠ x) t5, t12 t2 t2 t1 D[15:0] t1 In In In In t5, t12 RD t5, t12 t7 WR[1:0] DS126 Figure 133. Consecutive Normal Read Cycles (Burst, No Wait States) www.national.
TW T2 CP3BT26 T1 Bus State TH CLK t4, t12 t4 A21:0 A22 ('13 only) t5, t12 t5, t12 SELn, SELIO t2 t1 D[15:0] t5, t12 t5, t12 RD WR[1:0] DS127 Figure 134. Normal Read Cycle (Wait Cycle Followed by Hold Cycle) 267 www.national.
CP3BT26 Fast Read Bus State Tidle Early Write T1-2 T1 T2 Fast Read T3 T1-2 T1 CLK t4, t12 t4 A[21:0] A22 ('13 only) SELx (y ≠ x) t5, t12 t5, t12 SELy (y ≠ x) t1 t2 D[15:0] In Out In RD t5, t12 t5, t12 WR[1:0] DS128 Figure 135. Early Write Between Fast Read Cycles www.national.
31.1 LQFP-128 PACKAGE TDI TMS RESET ADC7/ADCIN ADC6 ADC5/MUXOUT1 ADC4/MUXOUT0 ADC3/TSYADC2/TSXADC1/TSY+ ADC0/TSX+ VREF ADGND ADVCC PE3/CTS PE0/RXD0 PE2/RTS GND VCC PE1/TXD0 SDA SCL IOVCC IOGND VCC GND IOGND IOVCC IOVCC PG5/SLE PG4/SDAT PG3/SCLK PG1/RFCE PG0/RFSYNC RFDATA IOGND PJ6/WUI24 PJ5/WUI23 For 128-pin devices, Figure 136 provides a pinout diagram, and Table 94 provides the pin assignments. The physical dimensions are provided in Section 33.0.
CP3BT26 Table 94 Pin Assignments for LQFP-128 Package Pin Name Alternate Function(s) Pin Numbers Type AVCC 29 PWR ADGND 90 PWR ADVCC 89 PWR UVCC 62 PWR UGND 63 PWR X2CKI 30 I X2CKO 31 O 34 I/O ENV2 SLOWCLK ENV1 CPUCLK 35 I/O ENV0 PLLCLK 36 I/O RESET 100 I TMS 101 I TDI 102 I TCK 103 I TDO 106 O RDY 108 O RFDATA 68 I/O D- 61 I/O D+ 60 I/O SCL 81 I/O 82 I/O ADC0 SDA TSX+ 92 I/O/HIZ 20mA+ ADC1 TSY+ 93 I/O/HIZ 20mA+ ADC2 TSX- 94 I/
Pin Name Alternate Function(s) Pin Numbers Type PC5 D13 5 GPIO PC6 D14 3 GPIO PC7 D15 2 GPIO PE0 RXD0 87 GPIO PE1 TXD0 83 GPIO PE2 RTS 86 GPIO PE3 CTS 88 GPIO PE4 CKX/TB 40 GPIO PE5 SRFS/NMI 120 GPIO PF0 MSK/TIO1 111 GPIO PF1 MDIDO/TIO2 114 GPIO PF2 MDODI/TIO3 116 GPIO PF3 MWCS/TIO4 109 GPIO PF4 SCK/TIO5 122 GPIO PF5 SFS/TIO6 123 GPIO PF6 STD/TIO7 125 GPIO PF7 SRD/TIO8 126 GPIO PG0 RFSYNC 69 GPIO PG1 RFCE 70 GPIO PG2 SRCLK 118
LQFP-144 PACKAGE TDI TMS RESET ADC7/ADCIN ADC6 ADC5/MUXOUT1 ADC4/MUXOUT0 ADC3/TSYADC2/TSXADC1/TSY+ ADC0/TSX+ VREF ADGND ADVCC PE3/CTS PE0/RXD0 PE2/RTS GND VCC PE1/TXD0 SDA SCL VCC GND IOGND SELIO SEL2 SEL1 IOVCC SEL0 PG5/SLE PG4/SDAT PG3/SCLK PG1/RFCE PG0/RFSYNC RFDATA For 144-pin devices, Figure 137 provides a pinout diagram, and Table 95 provides the pin assignments. The physical dimensions are provided in Section 33.0.
Pin Name Alternate Function(s) Pin Number Type GND 23, 32, 58, 85, 91, 121 PWR VCC 24, 31, 57, 86, 90, 122 PWR IOGND 3, 9, 16, 43, 46, 49, 55, 66, 84, 117, 130 PWR IOVCC 6, 12, 20, 41, 44, 51, 63, 80, 126, 140 PWR AGND 27 PWR AVCC 28 PWR ADGND 96 PWR ADVCC 95 PWR UVCC 71 PWR UGND 72 PWR 26 I X1CKO 25 O X2CKI 29 I X2CKO 30 O 33 I/O X1CKI BBCLK ENV2 SLOWCLK ENV1 CPUCLK 34 I/O ENV0 PLLCLK 35 I/O RESET 106 I TMS 107 I TDI 108 I TCK 109 I TDO
CP3BT26 Pin Name Alternate Function(s) Pin Number Type PB4 D4 17 GPIO PB5 D5 15 GPIO PB6 D6 14 GPIO PB7 D7 13 GPIO PC0 D8 11 GPIO PC1 D9 10 GPIO PC2 D10 8 GPIO PC3 D11 7 GPIO PC4 D12 5 GPIO PC5 D13 4 GPIO PC6 D14 2 GPIO PC7 D15 1 GPIO PE0 RXD0 93 GPIO PE1 TXD0 89 GPIO PE2 RTS 92 GPIO PE3 CTS 94 GPIO PE4 CKX/TB 37 GPIO PE5 SRFS/NMI 134 GPIO PF0 MSK/TIO1 120 GPIO PF1 MDIDO/TIO2 123 GPIO PF2 MDODI/TIO3 127 GPIO PF3 MWCS/T
Alternate Function(s) Pin Number Type A22 62 O A21 61 O A20 60 O A19 54 O A18 53 O A17 45 O A16 42 O A15 40 O A14 39 O A13 143 O A12 142 O A11 141 O A10 139 O A9 132 O A8 131 O A7 129 O A6 128 O A5 125 O A4 124 O A3 119 O A2 118 O A1 116 O A0 114 O SEL0 79 O SEL1 81 O SEL2 82 O SELIO 83 O RD 65 O WR0 67 O WR1 68 O Note 1: The ENV0, ENV1, ENV2, RESET, TCK, TDI, and TMS pins each have a weak pull-up to keep the input
CP3BT26 32.0 Revision History Table 96 Revision History Date Major Changes From Previous Version 4/3/03 Original release. 5/26/03 Fixed maximum boot area in Section 8. Fixed names of clock signals in Figures 5 and 6. Fixed addresses of FSMARx registers in Register Map section. Added default value for RNGDIV. 6/16/03 Corrected Table 27. Changed IOH and IOL. 6/30/03 Changed NSIDs, deleted commercial temperature range device, changed ADC conversion time to 15 microseconds.
CP3BT26 33.0 Physical Dimensions (millimeters) unless otherwise noted Figure 138. LQFP-128 Package Figure 139. LQFP-144 Package 277 www.national.
CP3BT26 Connectivity Processor with Bluetooth and Dual CAN Interfaces LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
