Network Card User Manual
Table Of Contents
- SCXI-1121 User Manual
- Support
- Important Information
- Contents
- About This Manual
- Chapter 1 Introduction
- Chapter 2 Configuration and Installation
- Chapter 3 Theory of Operation
- Chapter 4 Register Descriptions
- Chapter 5 Programming
- Appendix A Specifications
- Appendix B Rear Signal Connector
- Appendix C SCXIbus Connector
- Appendix D SCXI-1121 Front Connector
- Appendix E SCXI-1121 Cabling
- Appendix F Revision A and B Photo and Parts Locator Diagrams
- Appendix G Technical Support Resources
- Glossary
- Index
- Figures
- Figure 2-1. SCXI-1121 General Parts Locator Diagram
- Figure 2-2. SCXI-1121 Detailed Parts Locator Diagram
- Figure 2-3. SCXI-1121 Front Connector Pin Assignment
- Figure 2-4. Ground-Referenced Signal Connection with High Common-Mode Voltage
- Figure 2-5. Floating Signal Connection Referenced to Chassis Ground for Better Signal-to-Noise Ratio
- Figure 2-6. Floating AC-Coupled Signal Connection
- Figure 2-7. AC-Coupled Signal Connection with High Common-Mode Voltage
- Figure 2-8. Assembling and Mounting the SCXI-1330 Connector-and-Shell Assembly
- Figure 2-9. Nulling Circuit
- Figure 2-10. Shunt Circuit
- Figure 2-11. SCXI-1320 Parts Locator Diagram
- Figure 2-12. SCXI-1328 Parts Locator Diagram
- Figure 2-13. SCXI-1321 Parts Locator Diagram
- Figure 2-14. SCXI-1121 Rear Signal Connector Pin Assignment
- Figure 2-15. SCANCLK Timing Requirements
- Figure 2-16. Slot-Select Timing Diagram
- Figure 2-17. Serial Data Timing Diagram
- Figure 2-18. Configuration Register Write Timing Diagram
- Figure 2-19. SCXI-1121 Module ID Register Timing Diagram
- Figure 3-1. SCXI-1121 Block Diagram
- Figure 3-2. SCXIbus Connector Pin Assignment
- Figure 3-3. Digital Interface Circuitry Block Diagram
- Figure 3-4. SCXI-1121 Digital Control
- Figure 3-5. Analog Input Block Diagram
- Figure 3-6. Analog Output Circuitry
- Figure 3-7. Single-Module Parallel Scanning
- Figure 3-8. Single-Module Multiplexed Scanning (Direct)
- Figure 3-9. Single-Module Multiplexed Scanning (Indirect)
- Figure 3-10. Multiple-Module Multiplexed Scanning
- Figure 3-11. Multiple-Chassis Scanning
- Figure B-1. SCXI-1121 Rear Signal Connector Pin Assignment
- Figure C-1. SCXIbus Connector Pin Assignment
- Figure D-1. SCXI-1121 Front Connector Pin Assignment
- Figure E-1. SCXI-1340 Installation
- Figure E-2. SCXI-1180 Rear Connections
- Figure E-3. SCXI-1180 Front Panel Installation
- Figure E-4. Cover Removal
- Figure F-1. Revision A and B SCXI-1121 Signal Conditioning Module
- Figure F-2. Revision A and B SCXI-1121 General Parts Locator Diagram
- Figure F-3. Revision A and B SCXI-1121 Detailed Parts Locator Diagram
- Tables
- Table 2-1. Digital Signal Connections, Jumper Settings
- Table 2-2. Jumper W33 Settings
- Table 2-3. Gain Jumper Allocation
- Table 2-4. Gain Jumper Positions
- Table 2-5. Filter Jumper Allocation
- Table 2-6. Voltage and Current Mode Excitation Jumper Setup
- Table 2-7. Maximum Load per Excitation Channel
- Table 2-8. Excitation Level Jumper Selection
- Table 2-9. Completion Network Jumpers
- Table 2-10. Trimmer Potentiometer and Corresponding Channel
- Table 2-11. Nulling Resistors and Corresponding Channel
- Table 2-12. Jumper Settings of the Nulling Circuits
- Table 2-13. Jumper Settings on the SCXI-1320 Terminal Block
- Table 2-14. Jumper Settings on the SCXI-1328 Terminal Block
- Table 2-15. Jumper Settings on the SCXI-1321 Terminal Block
- Table 2-16. SCXIbus to SCXI-1121 Rear Signal Connector to Data Acquisition Board Pin Equivalences
- Table 3-1. SCXIbus Equivalents for the Rear Signal Connector
- Table 3-2. Calibration Potentiometer Reference Designators
- Table 5-1. SCXI-1121 Rear Signal Connector Pin Equivalences
- Table E-1. SCXI-1121 and MIO-16 Pinout Equivalences
- Table E-2. SCXI-1341 and SCXI-1344 Pin Translations
- Table E-3. SCXI-1342 Pin Translations
- Table E-4. SCXI-1343 Pin Connections
Chapter 5 Programming
© National Instruments Corporation 5-3 SCXI-1121 User Manual
3. For each bit, starting with the MSB first (bit 15):
a. SERDATIN = bit to be sent. These bits are the data that is being
written to the Slot-Select Register.
b. Clear SERCLK to 0.
c. Set SERCLK to 1. This rising edge clocks the data. (If you are
using an MIO-16 board, writing to the EXTSTROBE* register
will pulse EXTSTROBE* low and then high, accomplishing
steps 3b and 3c.)
4. Set SLOT0SEL* to 1. This will assert the SS* line of the module
whose slot number was written to Slot 0. If you are using multiple
chassis, the appropriate slot in the chassis whose address corresponds
to the written chassis number will be selected automatically. When no
communications are taking place between the data acquisition board
and any modules, write zero to the Slot-Select Register to ensure that
no accidental writes occur.
5. If you are writing to a Configuration Register, clear DAQD*/A to 0
(this indicates data will be written to the Configuration Register). If
you are writing to the HSCR or FIFO Register, leave DAQD*/A high.
6. For each bit to be written to the Configuration Register:
a. Establish the desired SERDATIN level corresponding to this bit.
b. Clear SERCLK to 0.
c. Set SERCLK to 1 (clock the data). (If you are using an MIO-16
board, writing to the EXTSTROBE* register will pulse
EXTSTROBE* low and then high, accomplishing steps 6b
and 6c.)
7. Pull SLOT0SEL* low to deassert the SS* line, latch the data into the
Configuration Register and establish conditions for writing a new slot
select number to the Slot 0 Slot-Select Register.
8. If you are not selecting another slot, write zero to the Slot 0 Slot-Select
Register. If you are selecting another slot, start at step 3.
For a timing illustration of a Configuration Register write, see Figure 2-18,
Configuration Register Write Timing Diagram, which shows the proper
write to configure an SCXI-1121 that is directly cabled to an MIO-16 for
multiple-module multiplexed scanning with a start channel of 3.
Initialization
The SCXI-1121 powers up with its Configuration register cleared to all
zeros. You can force this state by an active low signal on the RESET* pin
of the backplane connector. In the reset state, CH0 through CH3 are routed