Network Card User Manual
Table Of Contents
- SCXI-1121 User Manual
- Support
- Important Information
- Contents
- About This Manual
- Chapter 1 Introduction
- Chapter 2 Configuration and Installation
- Chapter 3 Theory of Operation
- Chapter 4 Register Descriptions
- Chapter 5 Programming
- Appendix A Specifications
- Appendix B Rear Signal Connector
- Appendix C SCXIbus Connector
- Appendix D SCXI-1121 Front Connector
- Appendix E SCXI-1121 Cabling
- Appendix F Revision A and B Photo and Parts Locator Diagrams
- Appendix G Technical Support Resources
- Glossary
- Index
- Figures
- Figure 2-1. SCXI-1121 General Parts Locator Diagram
- Figure 2-2. SCXI-1121 Detailed Parts Locator Diagram
- Figure 2-3. SCXI-1121 Front Connector Pin Assignment
- Figure 2-4. Ground-Referenced Signal Connection with High Common-Mode Voltage
- Figure 2-5. Floating Signal Connection Referenced to Chassis Ground for Better Signal-to-Noise Ratio
- Figure 2-6. Floating AC-Coupled Signal Connection
- Figure 2-7. AC-Coupled Signal Connection with High Common-Mode Voltage
- Figure 2-8. Assembling and Mounting the SCXI-1330 Connector-and-Shell Assembly
- Figure 2-9. Nulling Circuit
- Figure 2-10. Shunt Circuit
- Figure 2-11. SCXI-1320 Parts Locator Diagram
- Figure 2-12. SCXI-1328 Parts Locator Diagram
- Figure 2-13. SCXI-1321 Parts Locator Diagram
- Figure 2-14. SCXI-1121 Rear Signal Connector Pin Assignment
- Figure 2-15. SCANCLK Timing Requirements
- Figure 2-16. Slot-Select Timing Diagram
- Figure 2-17. Serial Data Timing Diagram
- Figure 2-18. Configuration Register Write Timing Diagram
- Figure 2-19. SCXI-1121 Module ID Register Timing Diagram
- Figure 3-1. SCXI-1121 Block Diagram
- Figure 3-2. SCXIbus Connector Pin Assignment
- Figure 3-3. Digital Interface Circuitry Block Diagram
- Figure 3-4. SCXI-1121 Digital Control
- Figure 3-5. Analog Input Block Diagram
- Figure 3-6. Analog Output Circuitry
- Figure 3-7. Single-Module Parallel Scanning
- Figure 3-8. Single-Module Multiplexed Scanning (Direct)
- Figure 3-9. Single-Module Multiplexed Scanning (Indirect)
- Figure 3-10. Multiple-Module Multiplexed Scanning
- Figure 3-11. Multiple-Chassis Scanning
- Figure B-1. SCXI-1121 Rear Signal Connector Pin Assignment
- Figure C-1. SCXIbus Connector Pin Assignment
- Figure D-1. SCXI-1121 Front Connector Pin Assignment
- Figure E-1. SCXI-1340 Installation
- Figure E-2. SCXI-1180 Rear Connections
- Figure E-3. SCXI-1180 Front Panel Installation
- Figure E-4. Cover Removal
- Figure F-1. Revision A and B SCXI-1121 Signal Conditioning Module
- Figure F-2. Revision A and B SCXI-1121 General Parts Locator Diagram
- Figure F-3. Revision A and B SCXI-1121 Detailed Parts Locator Diagram
- Tables
- Table 2-1. Digital Signal Connections, Jumper Settings
- Table 2-2. Jumper W33 Settings
- Table 2-3. Gain Jumper Allocation
- Table 2-4. Gain Jumper Positions
- Table 2-5. Filter Jumper Allocation
- Table 2-6. Voltage and Current Mode Excitation Jumper Setup
- Table 2-7. Maximum Load per Excitation Channel
- Table 2-8. Excitation Level Jumper Selection
- Table 2-9. Completion Network Jumpers
- Table 2-10. Trimmer Potentiometer and Corresponding Channel
- Table 2-11. Nulling Resistors and Corresponding Channel
- Table 2-12. Jumper Settings of the Nulling Circuits
- Table 2-13. Jumper Settings on the SCXI-1320 Terminal Block
- Table 2-14. Jumper Settings on the SCXI-1328 Terminal Block
- Table 2-15. Jumper Settings on the SCXI-1321 Terminal Block
- Table 2-16. SCXIbus to SCXI-1121 Rear Signal Connector to Data Acquisition Board Pin Equivalences
- Table 3-1. SCXIbus Equivalents for the Rear Signal Connector
- Table 3-2. Calibration Potentiometer Reference Designators
- Table 5-1. SCXI-1121 Rear Signal Connector Pin Equivalences
- Table E-1. SCXI-1121 and MIO-16 Pinout Equivalences
- Table E-2. SCXI-1341 and SCXI-1344 Pin Translations
- Table E-3. SCXI-1342 Pin Translations
- Table E-4. SCXI-1343 Pin Connections
Chapter 2 Configuration and Installation
SCXI-1121 User Manual 2-40 www.natinst.com
Digital I/O Signal Connections
Pins 24 through 27, 29, 33, 36, 37, and 43 constitute the digital I/O lines of
the rear signal connector. They are divided into three categories—the
digital input signals, the digital output signals, and the digital timing
signals.
The digital input signals are pins 24, 25, 27, 29, 33, and 37. The data
acquisition board uses these pins to configure an SCXI module that is under
data acquisition board control. Each digital line emulates the SCXIbus
communication signals as follows:
• Pin 25 is SERDATIN and is equivalent to the SCXIbus MOSI serial
data input line.
• Pin 27 is DAQD*/A and is equivalent to the SCXIbus D*/A line. It
indicates to the module whether the incoming serial stream on
SERDATIN is data (DAQD*/A = 0), or address (DAQD*/A = 1)
information.
• Pin 29 is SLOT0SEL* and is equivalent to the SCXIbus INTR* line. It
indicates whether the data on the SERDATIN line is being sent to
Slot 0 (SLOT0SEL* = 0) or to a module (SLOT0SEL* = 1).
• Pins 24 and 33 are the digital ground references for the data acquisition
board digital signals and are tied to the module digital ground.
• Pin 37 is SERCLK and is equivalent to the SCXIbus SPICLK line and
is used to clock the serial data on the SERDATIN line into the module
registers.
The digital output signal is pin 26.
• Pin 26 is SERDATOUT and is equivalent to SCXIbus MISO when
jumper W38 is in position 1.
The digital input and output signals of the SCXI-1121 match the digital I/O
lines of the MIO-16 board. When used with an SCXI-1341, SCXI-1342, or
SCXI-1344 cable assembly, the SCXI-1121 signals match the digital lines
of the Lab-NB/Lab-PC/Lab-PC+/Lab-LC boards and the PC-LPM-16
board, respectively. Table 2-16 lists the equivalences. For more
information, consult Appendix E, SCXI-1121 Cabling.