PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM PCI-6110E/6111E User Manual Multifunction I/O Boards for PCI Bus Computers April 1998 Edition Part Number 321759B-01 © Copyright 1998 National Instruments Corporation. All rights reserved.
PCI_E.book Page 2 Thursday, June 25, 1998 12:55 PM Internet Support E-mail: support@natinst.com FTP Site: ftp.natinst.com Web Address: http://www.natinst.
PCI_E.book Page 3 Thursday, June 25, 1998 12:55 PM Important Information Warranty The PCI-6110E/6111E boards are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
PCI_E.book Page v Thursday, June 25, 1998 12:55 PM Table of Contents About This Manual Organization of This Manual ........................................................................................ xi Conventions Used in This Manual................................................................................ xii National Instruments Documentation ........................................................................... xiii Related Documentation..................................................
PCI_E.book Page vi Thursday, June 25, 1998 12:55 PM Table of Contents Analog Output .............................................................................................................. 3-5 Analog Trigger ............................................................................................................. 3-6 Digital I/O..................................................................................................................... 3-10 Timing Signal Routing ..........................
PCI_E.book Page vii Thursday, June 25, 1998 12:55 PM Table of Contents General-Purpose Timing Signal Connections ................................................ 4-29 GPCTR0_SOURCE Signal.............................................................. 4-29 GPCTR0_GATE Signal................................................................... 4-30 GPCTR0_OUT Signal ..................................................................... 4-31 GPCTR0_UP_DOWN Signal .................................................
PCI_E.book Page viii Thursday, June 25, 1998 12:55 PM Table of Contents Figures Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware ............................................................... 1-4 Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. PCI-6110E Block Diagram ...................................................................
PCI_E.book Page ix Thursday, June 25, 1998 12:55 PM Table of Contents Figure 4-27. Figure 4-28. Figure 4-29. Figure 4-30. Figure 4-31. Figure 4-32. GPCTR0_GATE Signal Timing in Edge-Detection Mode ................... 4-31 GPCTR0_OUT Signal Timing .............................................................. 4-31 GPCTR1_SOURCE Signal Timing....................................................... 4-32 GPCTR1_GATE Signal Timing in Edge-Detection Mode ................... 4-33 GPCTR1_OUT Signal Timing .......
PCI_E.book Page xi Thursday, June 25, 1998 12:55 PM About This Manual This manual describes the electrical and mechanical aspects of the 611X E family of boards and contains information concerning their operation and programming. The 611X E family of boards includes: • PCI-6110E • PCI-6111E Your 611X E board is a high-performance multifunction analog, digital, and timing I/O board for PCI bus computers. Supported functions include analog input, analog output, digital I/O, and timing I/O.
PCI_E.book Page xii Thursday, June 25, 1998 12:55 PM About This Manual • Appendix C, Common Questions, contains a list of commonly asked questions and their answers relating to usage and special features of your 611X E board. • Appendix D, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products.
PCI_E.book Page xiii Thursday, June 25, 1998 12:55 PM About This Manual monospace Text in this font denotes text or characters that you should literally enter from the keyboard, sections of code, programming examples, and syntax examples. This font also is used for the proper names of disk drives, paths, directories, programs, subprograms, subroutines, device names, functions, operations, variables, filenames, and extensions, and for statements and comments taken from program code.
PCI_E.book Page xiv Thursday, June 25, 1998 12:55 PM About This Manual documentation or the NI-DAQ documentation to help you write your application. If you have a large, complicated system, it is worthwhile to look through the software documentation before you configure your hardware. • Accessory installation guides or manuals—If you are using accessory products, read the terminal block and cable assembly installation guides. They explain how to physically connect the relevant pieces of the system.
PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM Chapter 1 Introduction This chapter describes your 611X E board, lists what you need to get started, describes the optional software and optional equipment, and explains how to unpack your 611X E board. About the 611X E Boards Thank you for buying a National Instruments PCI-6110E/6111E board. Your 611X E board is a completely Plug and Play, multifunction analog, digital, and timing I/O board for PCI bus computers.
PCI_E.book Page 2 Thursday, June 25, 1998 12:55 PM Chapter 1 Introduction and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ boards in your computer. Detailed specifications of the 611X E board are in Appendix A, Specifications.
PCI_E.book Page 3 Thursday, June 25, 1998 12:55 PM Chapter 1 Introduction LabVIEW Data Acquisition VI Library, a series of VIs for using LabVIEW with National Instruments DAQ hardware, is included with LabVIEW. The LabVIEW Data Acquisition VI Library is functionally equivalent to NI-DAQ software. LabWindows/CVI features interactive graphics, state-of-the-art user interface, and uses the ANSI standard C programming language.
PCI_E.book Page 4 Thursday, June 25, 1998 12:55 PM Chapter 1 Introduction NI-DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers. NI-DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code.
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PCI_E.book Page 6 Thursday, June 25, 1998 12:55 PM Chapter 1 Introduction The following list gives recommended part numbers for connectors that mate to the I/O connector on the 611X E board: • Honda 68-position, solder cup, female connector (part number PCS-E68FS) • Honda backshell (part number PCS-E68LKPA) Unpacking The 611X E board is shipped in an antistatic package to prevent electrostatic damage to the board. Electrostatic discharge can damage several components on the board.
PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM Chapter Installation and Configuration 2 This chapter explains how to install and configure your 611X E board. Software Installation Install your software before you install the 611X E board. Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence. If you are using LabVIEW, LabWindows/CVI, or other National Instruments application software packages, refer to the appropriate release notes.
PCI_E.book Page 2 Thursday, June 25, 1998 12:55 PM Chapter 2 Installation and Configuration 5. Insert the 611X E board into a 5 V PCI slot. Gently rock the board to ease it into place. It may be a tight fit, but do not force the board into place. 6. If required, screw the mounting bracket of the 611X E board to the back panel rail of the computer. 7. Replace the cover. 8. Plug in and turn on your computer. The 611X E board is installed. You are now ready to configure your software.
PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview This chapter presents an overview of the hardware functions on your 611X E board. Figure 3-1 shows a block diagram for the PCI-6110E board.
PCI_E.book Page 2 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview Figure 3-2 shows a block diagram for the PCI-6111E board.
PCI_E.book Page 3 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview configuration, refer to the Analog Input Signal Connections section in Chapter 4, Signal Connections, which contains diagrams showing the signal paths for DIFF input. Input Polarity and Input Range The 611X E board has bipolar inputs only. Bipolar input means that the input voltage range is between –Vref /2 and + Vref/2. These boards have a bipolar input range of 20 V (±10 V).
PCI_E.book Page 4 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview Considerations for Selecting Input Ranges The range you select depends on the expected range of the incoming signal. A large input range can accommodate a large signal variation but reduces the voltage resolution. Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range.
PCI_E.book Page 5 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview You cannot disable dither on the 611X E board. This is because the ADC resolution is so fine that the ADC and the PGIA inherently produce almost 0.5 LSBrms of noise. This is equivalent to having a dither circuit that is always enabled. LSBs 6.0 LSBs 6.0 4.0 4.0 2.0 2.0 0.0 0.0 -2.0 -2.0 -4.0 -4.0 -6.0 -6.0 0 100 200 300 400 0 500 a. Dither disabled; no averaging 100 200 300 400 500 b.
PCI_E.book Page 6 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview Analog Trigger In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence, these boards also support analog triggering. You can configure the analog trigger circuitry to accept either a direct analog input from the PFI0/TRIG1 pin on the I/O connector or a postgain signal from the output of the PGIA on any of the channels, as shown in Figures 3-4 and 3-5.
PCI_E.book Page 7 Thursday, June 25, 1998 12:55 PM Chapter 3 Analog Input CH0 Analog Input CH1 Hardware Overview ADC + PGIA - Mux ADC + Analog Trigger Circuit DAQ-STC PGIA PFI0/TRIG1 Figure 3-5. Analog Trigger Block Diagram for the PCI-6111E Five analog triggering modes are available, as shown in Figures 3-6 through 3-10. You can set lowValue and highValue independently in software.
PCI_E.book Page 8 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview In above-high-level analog triggering mode, the trigger is generated when the signal value is greater than highValue, as shown in Figure 3-7. LowValue is unused. highValue Trigger Figure 3-7. Above-High-Level Analog Triggering Mode In inside-region analog triggering mode, the trigger is generated when the signal value is between the lowValue and the highValue, as shown in Figure 3-8.
PCI_E.book Page 9 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview In high-hysteresis analog triggering mode, the trigger is generated when the signal value is greater than highValue, with the hysteresis specified by lowValue, as shown in Figure 3-9. highValue lowValue Trigger Figure 3-9.
PCI_E.book Page 10 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview Digital I/O The 611X E board contains eight lines of digital I/O for general-purpose use. You can individually software-configure each line for either input or output. At system startup and reset, the digital I/O ports are all high impedance. The hardware up/down control for general-purpose counters 0 and 1 are connected onboard to DIO6 and DIO7, respectively.
PCI_E.book Page 11 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview Timing Signal Routing The DAQ-STC provides a very flexible interface for connecting timing signals to other boards or external circuitry. The 611X E board uses the RTSI bus to interconnect timing signals between boards, and the Programmable Function Input (PFI) pins on the I/O connector to connect the board to external circuitry.
PCI_E.book Page 12 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview This figure shows that CONVERT* can be generated from a number of sources, including the external signals RTSI<0..6> and PFI<0..9> and the internal signals Sample Interval Counter TC and GPCTR0_OUT. Many of these timing signals are also available as outputs on the RTSI pins, as indicated in the RTSI Triggers section later in this chapter, and on the PFI pins, as indicated in Chapter 4, Signal Connections.
PCI_E.book Page 13 Thursday, June 25, 1998 12:55 PM Chapter 3 Hardware Overview RTSI Triggers The seven RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for the 611X E board sharing the RTSI bus. These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals. This signal connection scheme is shown in Figure 3-12.
PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections This chapter describes how to make input and output signal connections to your 611X E board via the board I/O connector. The I/O connector for the 611X E board has 68 pins that you can connect to 68-pin accessories with the SH6868EP shielded cable. I/O Connector Figure 4-1 shows the pin assignments for the 68-pin I/O connector on the 611X E board. A signal description follows the connector pinouts.
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PCI_E.book Page 3 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections I/O Connector Signal Descriptions Table 4-1. Signal Descriptions for I/O Connector Pins Signal Name Reference Direction ACH <0..3> GND — — Analog Input Channels 0 through 3 ground—These pins are the bias current return point for differential measurements. ACH <2..3> GND signals are no connects on the PCI-6111E. ACH<0..3> + ACH <0..
PCI_E.book Page 4 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Table 4-1. Signal Descriptions for I/O Connector Pins (Continued) Signal Name PFI0/TRIG1 PFI1/TRIG2 PFI2/CONVERT* PFI3/GPCTR1_SOURCE PFI4/GPCTR1_GATE Reference Direction DGND Input PFI0/Trigger 1—As an input, this is either one of the Programmable Function Inputs (PFIs) or the source for the hardware analog trigger. PFI signals are explained in the Timing Connections section later in this chapter.
PCI_E.book Page 5 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Table 4-1. Signal Descriptions for I/O Connector Pins (Continued) Signal Name PFI6/WFTRIG PFI7/STARTSCAN PFI8/GPCTR0_SOURCE PFI9/GPCTR0_GATE Reference Direction DGND Input PFI6/Waveform Trigger—As an input, this is one of the PFIs. Output As an output, this is the WFTRIG signal. In timed analog output sequences, a low-to-high transition indicates the initiation of the waveform generation.
PCI_E.book Page 6 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Table 4-2 shows the I/O signal summary for the 611X E boards. Table 4-2. I/O Signal Summary for the 611X E Signal Name Signal Impedance Type and Input/ Direction Output Protection (Volts) On/Off Sink (mA at V) Source (mA at V) Rise Time (ns) Bias ACH<0..3> + AI 1 MΩ in parallel with 100 pF1 1 MΩ in parallel with 10 pF2 42 V — — — — ACH<0..3> – AI 10 nF 42 V — — — ±200 pA ACH <0..
PCI_E.book Page 7 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Table 4-2. I/O Signal Summary for the 611X E (Continued) Signal Name Signal Impedance Type and Input/ Direction Output Protection (Volts) On/Off Source (mA at V) PFI4/GPCTR1_GATE DIO — V +0.5 cc 3.5 at (V GPCTR1_OUT DO — — 3.5 at (V PFI5/UPDATE* DIO — PFI6/WFTRIG DIO PFI7/STARTSCAN Sink (mA at V) Rise Time (ns) Bias -0.4) 5 at 0.4 1.5 50 kΩ pu -0.4) 5 at 0.4 1.5 50 kΩ pu Vcc +0.5 3.
PCI_E.book Page 8 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Analog Input Signal Connections The analog input signals for the 611X E board are ACH<0..3>+ and ACH<0..3>–. The ACH<0..3>+ signals are routed to the positive input of the PGIA, and signals connected to ACH<0..3>– are routed to the negative input of the PGIA. ! Caution: Exceeding the differential and common-mode input ranges distorts your input signals.
PCI_E.book Page 9 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Types of Signal Sources When making signal connections, you must first determine whether the signal sources are floating or ground-referenced. The following sections describe these two types of signals. Floating Signal Sources A floating signal source is not connected in any way to the building ground system but, rather, has an isolated ground-reference point.
PCI_E.book Page 10 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Table 4-3 summarizes the recommended DIFF signal connections and includes input examples for both types of signal sources. Table 4-3.
PCI_E.book Page 11 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Differential Connections for Ground-Referenced Signal Sources Figure 4-3 shows how to connect a ground-referenced signal source to a channel on the 611X E board. ACH0+ GroundReferenced Signal Source CommonMode Noise and Ground Potential + Instrumentation Amplifier + Vs PGIA + - ACH0- - + Measured Voltage Vm - V cm - ACH0GND I/O Connector ACH0 Connections Shown Figure 4-3.
PCI_E.book Page 12 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections ACH0+ Floating Signal Source + + VS 100pf Instrumentation Amplifier 1MΩ - PGIA + ACH0- - Bias Current Return Paths 10nf Measured Voltage Vm - Bias Resistor (see text) ACH0GND I/O Connector ACH0 Connections Shown Figure 4-4. Differential Input Connections for Nonreferenced Signals Figure 4-4 shows a bias resistor connected between ACH0 – and the floating signal source ground.
PCI_E.book Page 13 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Analog Output Signal Connections The analog output signals are DAC0OUT, DAC1OUT, and AOGND. DAC0OUT is the voltage output signal for analog output channel 0. DAC1OUT is the voltage output signal for analog output channel 1. AOGND is the ground reference signal for the analog output channels. Figure 4-5 shows how to make analog output connections to the 611X E board.
PCI_E.book Page 14 Thursday, June 25, 1998 12:55 PM Chapter 4 ! Signal Connections Caution: Exceeding the maximum input voltage ratings, which are listed in Table 4-2, can damage the 611X E board and the computer. National Instruments is NOT liable for any damages resulting from such signal connections. Figure 4-6 shows signal connections for three typical digital I/O applications. +5 V LED DIO<4..7> TTL Signal DIO<0..3> +5 V Switch DGND I/O Connector 611X E Board Figure 4-6.
PCI_E.book Page 15 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Power Connections Two pins on the I/O connector supply +5 V from the computer power supply via a self-resetting fuse. The fuse will reset automatically within a few seconds after the overcurrent condition is removed. These pins are referenced to DGND and can be used to power external digital circuitry. • ! Caution: Power rating +4.65 to +5.
PCI_E.book Page 16 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections All digital timing connections are referenced to DGND. This reference is demonstrated in Figure 4-7, which shows how to connect an external TRIG1 source and an external CONVERT* source to two 611X E board PFI pins. PFI0/TRIG1 PFI2/CONVERT* TRIG1 Source CONVERT* Source DGND I/O Connector 611X E Board Figure 4-7.
PCI_E.book Page 17 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections for the PFI2/CONVERT* pin. Be careful not to drive a PFI signal externally when it is configured as an output. As an input, you can individually configure each PFI for edge or level detection and for polarity selection, as well. You can use the polarity selection for any of the 13 timing signals, but the edge or level detection will depend upon the particular timing signal being controlled.
PCI_E.book Page 18 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections TRIG1 TRIG2 Don't Care STARTSCAN CONVERT* Scan Counter 3 2 1 0 2 2 2 1 0 Figure 4-9. Typical Pretriggered Acquisition SCANCLK Signal SCANCLK is an output-only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A/D conversion begins.
PCI_E.book Page 19 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Figure 4-11 shows the timing for the hardware-strobe mode EXTSTROBE* signal. V OH V OL tw tw t w = 600 ns or 5 µs Figure 4-11. EXTSTROBE* Signal Timing TRIG1 Signal Any PFI pin can externally input the TRIG1 signal, which is available as an output on the PFI0/TRIG1 pin. Refer to Figures 4-8 and 4-9 for the relationship of TRIG1 to the DAQ sequence. As an input, the TRIG1 signal is configured in the edge-detection mode.
PCI_E.book Page 20 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Figures 4-12 and 4-13 show the input and output timing requirements for the TRIG1 signal. tw Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-12. TRIG1 Input Signal Timing tw t w = 25-50 ns Figure 4-13. TRIG1 Output Signal Timing The board also uses the TRIG1 signal to initiate pretriggered DAQ operations. In most pretriggered applications, the TRIG1 signal is generated by a software trigger.
PCI_E.book Page 21 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections of scans before TRIG2 can be recognized. After the scan counter decrements to zero, it is loaded with the number of posttrigger scans to acquire while the acquisition continues. The board ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero. After the selected edge of TRIG2 is received, the board will acquire a fixed number of scans and the acquisition will stop.
PCI_E.book Page 22 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal, which is available as an output on the PFI7/STARTSCAN pin. Refer to Figures 4-8 and 4-9 for the relationship of STARTSCAN to the DAQ sequence. As an input, the STARTSCAN signal is configured in the edge-detection mode. You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge.
PCI_E.book Page 23 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections tw STARTSCAN t w = 25-50 ns a. Start of Scan Start Pulse CONVERT* STARTSCAN toff = 10 ns minimum toff b. Scan in Progress, Two Conversions per Scan Figure 4-17. STARTSCAN Output Signal Timing The CONVERT* pulses are masked off until the board generates the STARTSCAN signal. If you are using internally generated conversions, the first CONVERT* appears when the onboard sample interval counter reaches zero.
PCI_E.book Page 24 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Refer to Figures 4-8 and 4-9 for the relationship of STARTSCAN to the DAQ sequence. As an input, the CONVERT* signal is configured in the edge-detection mode. You can select any PFI pin as the source for CONVERT* and configure the polarity selection for either rising or falling edge. The selected edge of the CONVERT* signal initiates an A/D conversion.
PCI_E.book Page 25 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections The sample interval counter on the 611X E board normally generates the CONVERT* signal unless you select some external source. The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished. It then reloads itself in preparation for the next STARTSCAN pulse.
PCI_E.book Page 26 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation. Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source. Figure 4-20 shows the timing requirements for the SISOURCE signal. tp tw tw t p = 50 ns minimum t w = 23 ns minimum Figure 4-20.
PCI_E.book Page 27 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Figures 4-21 and 4-22 show the input and output timing requirements for the WFTRIG signal. tw Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-21. WFTRIG Input Signal Timing tw t w = 25-50 ns Figure 4-22. WFTRIG Output Signal Timing UPDATE* Signal Any PFI pin can externally input the UPDATE* signal, which is available as an output on the PFI5/UPDATE* pin.
PCI_E.book Page 28 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Figures 4-23 and 4-24 show the input and output timing requirements for the UPDATE* signal. tw Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-23. UPDATE* Input Signal Timing tw t w = 50-75 ns Figure 4-24. UPDATE* Output Signal Timing The DACs are updated within 100 ns of the leading edge. Separate the UPDATE* pulses with enough time that new data can be written to the DAC latches.
PCI_E.book Page 29 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections polarity selection for the PFI pin for either active high or active low. Figure 4-25 shows the timing requirements for the UISOURCE signal. tp tw tw t p = 50 ns minimum t w = 10 ns minimum Figure 4-25. UISOURCE Signal Timing The maximum allowed frequency is 20 MHz, with a minimum pulse width of 10 ns high or low. There is no minimum frequency limitation.
PCI_E.book Page 30 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Figure 4-26 shows the timing requirements for the GPCTR0_SOURCE signal. tp tw tw t p = 50 ns minimum t w = 10 ns minimum Figure 4-26. GPCTR0_SOURCE Signal Timing The maximum allowed frequency is 20 MHz, with a minimum pulse width of 10 ns high or low. There is no minimum frequency limitation. The 20 MHz or 100 kHz timebase normally generates the GPCTR0_SOURCE signal unless you select some external source.
PCI_E.book Page 31 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections Figure 4-27 shows the timing requirements for the GPCTR0_GATE signal. tw Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-27. GPCTR0_GATE Signal Timing in Edge-Detection Mode GPCTR0_OUT Signal This signal is available only as an output on the GPCTR0_OUT pin. The GPCTR0_OUT signal reflects the terminal count (TC) of general-purpose counter 0.
PCI_E.book Page 32 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal, which is available as an output on the PFI3/GPCTR1_SOURCE pin. As an input, the GPCTR1_SOURCE signal is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge.
PCI_E.book Page 33 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections actions as starting and stopping the counter, generating interrupts, saving the counter contents, and so on. As an output, the GPCTR1_GATE signal monitors the actual gate signal connected to general-purpose counter 1. This is true even if the gate is being externally generated by another PFI. This output is set to tri-state at startup. Figure 4-30 shows the timing requirements for the GPCTR1_GATE signal.
PCI_E.book Page 34 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I/O connector. General-purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high. This input can be disabled so that software can control the up-down functionality and leave the DIO7 pin free for general use.
PCI_E.book Page 35 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections low) for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge, as shown by t gsu and tgh in Figure 4-32. The gate signal is not required to be held after the active edge of the source signal. If you use an internal timebase clock, the gate signal cannot be synchronized with the clock.
PCI_E.book Page 36 Thursday, June 25, 1998 12:55 PM Chapter 4 Signal Connections point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference. • Route signals to the board carefully. Keep cabling away from noise sources. The most common noise source in a PCI data acquisition system is the video monitor. Separate the monitor from the analog signals as much as possible.
PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM Chapter 5 Calibration This chapter discusses the calibration procedures for your 611X E board. If you are using the NI-DAQ device driver, that software includes calibration functions for performing all of the steps in the calibration process. Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments.
PCI_E.book Page 2 Thursday, June 25, 1998 12:55 PM Chapter 5 Calibration This method of calibration is not very accurate because it does not take into account the fact that the board measurement and output voltage errors can vary with time and temperature. It is better to self-calibrate when the board is installed in the environment in which it will be used. Self-Calibration The 611X E board can measure and correct for almost all of its calibration-related errors without any external signal connections.
PCI_E.book Page 3 Thursday, June 25, 1998 12:55 PM Chapter 5 Calibration To externally calibrate your board, be sure to use a very accurate external reference. The reference should be several times more accurate than the board itself. For example, to calibrate a 16-bit board, the external reference should be at least ±0.001% (±10 ppm) accurate.
PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM Appendix A Specifications This appendix lists the specifications of your 611X E board. These specifications are typical at 25° C unless otherwise noted. PCI-6110E/6111E Analog Input Input Characteristics Number of channels PCI-6110E ...................................4 differential PCI-6111E ...................................2 differential Resolution...........................................12 bits, 1 in 4,096 Max sampling rate ......................
PCI_E.book Page 2 Thursday, June 25, 1998 12:55 PM Appendix A Specifications Input coupling .................................... DC/AC Max working voltage for all analog input channels + input ......................................... Should remain within ±11 V for ranges ≥ ±10 V; should remain within ±42 V for ranges < ±10 V – input ......................................... Should remain within ±11 V Overvoltage protection ....................... ±42 V Inputs protected + input ..........................
90 Days 24 Hours 0.51% 0.51% 0.11% 0.057% 0.057% 0.057% 0.057% 0.057% Full Scale ±50 ±20 ±10 © National Instruments Corporation ±5 ±2 ±1 ±0.5 ±0.2 A-3 0.059% 0.059% 0.059% 0.059% 0.059% 0.11% 0.51% 0.51% 1 Year 0.2 mV 0.4 mV 0.7 mV 1.3 mV 3 mV 5.7 mV 20 mV 35 mV (mV) 0.39 mV 0.67 mV 1 mV 2 mV 5.1 mV 10 mV 20 mV 51 mV Single Pt. 0.035 mV 0.059 mV 0.088 mV 0.18 mV 0.44 mV 0.88 mV 1.8 mV 4.4 mV Averaged 0.0005% 0.0005% 0.0005% 0.0005% 0.0005% 0.0005% 0.
PCI_E.book Page 4 Thursday, June 25, 1998 12:55 PM Appendix A Specifications Transfer Characteristics INL .................................................... ±0.5 LSB typ, ±1 LSB max DNL ................................................... ±0.3 LSB typ, ±0.75 LSB max Spurious free dynamic range (SFDR) . See table, analog input characteristics Effective number of bits (ENOB) ....... 11.0 bits, DC to 100 kHz Offset error ........................................
PCI_E.book Page 5 Thursday, June 25, 1998 12:55 PM Appendix A Specifications Postgain .......................................±50 µV/° C Gain temperature coefficient ...............±20 ppm/° C Onboard calibration reference Level ............................................5.000 V (±2.5 mV) (actual value stored in EEPROM) Temperature coefficient ...............±0.6 ppm/° C max Long-term stability.......................±6 ppm/ 1, 000 h Analog Output Output Characteristics Number of channels ...............
PCI_E.book Page 6 Thursday, June 25, 1998 12:55 PM Appendix A Specifications Output impedance .............................. 50 Ω ±5% Current drive ...................................... ±5 mA min Output stability .................................. Any passive load Protection .......................................... Short-circuit to ground Power-on state.................................... 0 V Dynamic Characteristics Slew rate ............................................ 300 V/µs Noise................
PCI_E.book Page 7 Thursday, June 25, 1998 12:55 PM Appendix A Specifications Digital logic levels Level Min Max Input low voltage 0.0 V 0.8 V Input high voltage 2.0 V 5.0 V Input low current (V = 0 V) — –320 µA Input high current (V = 5 V) — 10 µA Output low voltage (I — 0.4 V 4.35 V — in in OL Output high voltage (I = 24 mA) OH = 13 mA) Power-on state ....................................Input (High-Z) Data transfers......................................
PCI_E.book Page 8 Thursday, June 25, 1998 12:55 PM Appendix A Specifications Data transfers ..................................... DMA, interrupts, programmed I/O DMA modes ....................................... Scatter-gather Triggers Analog Trigger Source PCI-6110E ................................... All analog input channels, external trigger (PFI0/TRIG1) PCI-6111E ................................... All analog input channels, external trigger (PFI0/TRIG1) Level ......................................
PCI_E.book Page 9 Thursday, June 25, 1998 12:55 PM Appendix A Specifications RTSI Trigger Lines ......................................7 Bus Interface Type ...................................................Master, slave Power Requirement +5 VDC (±5%) PCI-6110E ...................................2.5 A PCI-6111E ...................................2.0 A Power available at I/O connector ........+4.65 to +5.25 VDC at 1 A Physical Dimensions (not including connectors) .................31.2 by 10.6 cm (12.
PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM Appendix Cable Connector Descriptions B This appendix describes the cable connectors on your 611X E board. Figure B-1 shows the pin assignments for the 68-pin 611X E connector. This connector is available when you use the SH6868EP cable assemblies with the 611X E board.
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PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM Appendix C Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of your 611X E board. General Information What is the 611X E board? The 611X E board is a switchless and jumperless enhanced MIO board that uses the DAQ-STC for timing.
PCI_E.book Page 2 Thursday, June 25, 1998 12:55 PM Appendix C Common Questions What type of 5 V protection does the 611X E board have? The 611X E board has 5 V lines equipped with a self-resetting 1 A fuse. Installation and Configuration How do you set the base address for the 611X E board? The base address of the 611X E board is assigned automatically through the PCI bus protocol. This assignment is completely transparent to you.
PCI_E.book Page 3 Thursday, June 25, 1998 12:55 PM Appendix C Common Questions Can I synchronize a one-channel analog input data acquisition with a one-channel analog output waveform generation on my 611X E board? Yes. One way to accomplish this is to use the waveform generation timing pulses to control the analog input data acquisition. To do this, follow steps 1 through 4 below, in addition to the usual steps for data acquisition and waveform generation configuration. 1.
PCI_E.book Page 4 Thursday, June 25, 1998 12:55 PM Appendix C Common Questions up/down control, single or pulse train generation, equivalent time sampling, buffered period, and buffered semiperiod measurement. What is the difference in timebases between the Am9513 counter/timer and the DAQ-STC? The DAQ-STC-based MIO boards have a 20 MHz timebase. The Am9513-based MIO boards have a 1 MHz or 5 MHz timebase.
PCI_E.book Page 5 Thursday, June 25, 1998 12:55 PM Appendix C Common Questions connector, route external signals to internal timing sources, or tie internal timing signals together. If you are using NI-DAQ with LabVIEW and you want to connect external signal sources to the PFI lines, you can use AI Clock Config, AI Trigger Config, AO Clock Config, AO Trigger and Gate Config, CTR Mode Config, and CTR Pulse Config advanced level VIs to indicate which function the connected signal will serve.
PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM Appendix Customer Communication D For your convenience, this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation. When you contact us, we need the information on the Technical Support Form and the configuration form, if your manual contains one, about your system configuration to answer your questions as quickly as possible.
PCI_E.book Page 2 Thursday, June 25, 1998 12:55 PM Fax-on-Demand Support Fax-on-Demand is a 24-hour information retrieval system containing a library of documents on a wide range of technical information. You can access Fax-on-Demand from a touch-tone telephone at 512 418 1111. E-Mail Support (Currently USA Only) You can submit technical support questions to the applications engineering team through e-mail at the Internet address listed below.
PCI_E.book Page 3 Thursday, June 25, 1998 12:55 PM Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
PCI_E.book Page 5 Thursday, June 25, 1998 12:55 PM PCI-6110E/6111E Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.
PCI_E.book Page 7 Thursday, June 25, 1998 12:55 PM Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: PCI-6110E/6111E User Manual Edition Date: April 1998 Part Number: 321759B-01 Please comment on the completeness, clarity, and organization of the manual.
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PCI_E.book Page 3 Thursday, June 25, 1998 12:55 PM Glossary C C Celsius CalDAC calibration DAC CH channel—pin or wire lead to which you apply or from which you read the analog or digital signal. Analog signals can be singleended or differential. For digital signals, you group channels to form ports.
PCI_E.book Page 4 Thursday, June 25, 1998 12:55 PM Glossary general A/D and D/A system, such as a system containing the National Instruments E Series boards.
PCI_E.book Page 5 Thursday, June 25, 1998 12:55 PM Glossary system memory. Programming the DMA controller and servicing interrupts can take several milliseconds in some cases. During this time, data accumulates in the FIFO for future retrieval. With a larger FIFO, longer latencies can be tolerated. In the case of analog output, a FIFO permits faster update rates, because the waveform data can be stored in the FIFO ahead of time.
PCI_E.book Page 6 Thursday, June 25, 1998 12:55 PM Glossary I INL integral nonlinearity–For an ADC, deviation of codes of the actual transfer function from a straight line.
PCI_E.book Page 7 Thursday, June 25, 1998 12:55 PM Glossary mV millivolts N NC normally closed, or not connected NI-DAQ National Instruments driver software for DAQ hardware noise an undesirable electrical signal—Noise comes from external sources such as the AC power line, motors, generators, transformers, fluorescent lights, CRT displays, computers, electrical storms, welders, radio transmitters, and internal sources such as semiconductors, resistors, and capacitors.
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PCI_E.book Page 10 Thursday, June 25, 1998 12:55 PM Glossary THD total harmonic distortion—the ratio of the total rms signal due to harmonic distortion to the overall rms signal, in decibel or a percentage thermocouple a temperature sensor created by joining two dissimilar metals. The junction produces a small voltage as a function of the temperature.
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PCI_E.book Page 2 Thursday, June 25, 1998 12:55 PM Index ComponentWorks software, 1-3 configuration PCI-6110E/6111E, 2-2 questions about, C-2 connectors. See I/O connectors.
PCI_E.book Page 3 Thursday, June 25, 1998 12:55 PM Index E data acquisition timing connections. See DAQ timing connections.
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