a.Book : a.Title Page 1 Wednesday, November 20, 1996 6:36 PM PC-LPM-16/PnP User Manual Multifunction I/O Board for the PC November 1996 Edition Part Number 320287C-01 Copyright 1990, 1996 National Instruments Corporation. All Rights Reserved.
a.Book : a.Title Page 2 Wednesday, November 20, 1996 6:36 PM Internet Support support@natinst.com E-mail: info@natinst.com FTP Site: ftp.natinst.com Web Address: http://www.natinst.com Bulletin Board Support BBS United States: (512) 794-5422 BBS United Kingdom: 01635 551422 BBS France: 01 48 65 15 59 Fax-on-Demand Support (512) 418-1111 Telephone Support (U.S.
a.Book : b.Warranty Page 3 Wednesday, November 20, 1996 6:36 PM Important Information Warranty The PC-LPM-16 and PC-LPM-16PnP are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
a.Book : c.Table of Contents Page v Wednesday, November 20, 1996 6:36 PM Table of Contents About This Manual Organization of This Manual .........................................................................................ix Conventions Used in This Manual.................................................................................x National Instruments Documentation ............................................................................xi Related Documentation................................
a.Book : c.Table of Contents Page vi Wednesday, November 20, 1996 6:36 PM Table of Contents Analog Input Circuitry .................................................................................... 3-5 Data Acquisition Timing Circuitry ................................................................. 3-6 Single-Channel Data Acquisition ..................................................... 3-7 Multichannel Scanning Data Acquisition ......................................... 3-7 Data Acquisition Rates ....
a.Book : c.Table of Contents Page vii Wednesday, November 20, 1996 6:36 PM Table of Contents Glossary Index Figures Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware ...............................................................1-4 Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. PC-LPM-16PnP Block Diagram ...........................................................3-2 PC I/O Interface Circuitry Block Diagram .............................
a.Book : c.Table of Contents Page viii Wednesday, November 20, 1996 6:36 PM Table of Contents Tables Table 4-1. Signal Connection Descriptions ............................................................ 4-3 Table C-1. Table C-2. Table C-3. Comparison of Characteristics .............................................................. C-1 PC Bus Interface Factory Settings ........................................................
a.Book : d.ATM Page ix Wednesday, November 20, 1996 6:36 PM About This Manual This manual describes the mechanical and electrical aspects of the PC-LPM-16PnP and contains information concerning its installation, operation, and programming. The PC-LPM-16PnP is a low-cost, lowpower analog input, digital, and timing I/O board for the IBM PC/XT, PC AT, Personal System/2 Models 25 and 30, and laptop compatible computers. This manual also applies to the PC-LPM-16, a non-Plug and Play board.
a.Book : d.ATM Page x Wednesday, November 20, 1996 6:36 PM About This Manual • Appendix C, Using Your PC-LPM-16 (Non-PnP) Board, describes the differences between the PC-LPM-16PnP and the PC-LPM-16 non-PnP boards, the PC-LPM-16 board configuration, and installing the PC-LPM-16 into your computer. • Appendix D, Register-Level Programming, describes in detail information related to register-level programming the PC-LPM-16/PnP.
a.Book : d.ATM Page xi Wednesday, November 20, 1996 6:36 PM About This Manual Non-PnP Non-PnP (non-Plug and Play) means that the board requires you to manually configure the product’s base address and interrupt level with switches and jumpers. You must perform this configuration before installing the board into your computer. PC PC refers to the IBM PC/XT, PC AT, Personal System/2 Models 25 and 30, and laptop compatible computers.
a.Book : d.ATM Page xii Wednesday, November 20, 1996 6:36 PM About This Manual installation and configuration instructions, specification information about your DAQ hardware, and application hints. • Software documentation—Examples of software documentation you may have are the LabVIEW, LabWindows/CVI documentation sets, and the NI-DAQ documentation.
a.Book : e.chapter 1 Page 1 Wednesday, November 20, 1996 6:36 PM Chapter 1 Introduction This chapter describes the PC-LPM-16/PnP, lists what you need to get started, software programming choices, and optional equipment, and explains how to unpack the PC-LPM-16/PnP. About the PC-LPM-16/PnP The PC-LPM-16/PnP is a low-cost, low-power analog input, digital, and timing I/O board for the PC.
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a.Book : e.chapter 1 Page 3 Wednesday, November 20, 1996 6:36 PM Chapter 1 Introduction included with the NI-DAQ software kit. The LabWindows/CVI Data Acquisition Library is functionally equivalent to the NI-DAQ software. Using LabVIEW or LabWindows/CVI software will greatly reduce the development time for your data acquisition and control application. NI-DAQ Driver Software The NI-DAQ driver software is included at no charge with all National Instruments DAQ hardware.
a.Book : e.chapter 1 Page 4 Wednesday, November 20, 1996 6:36 PM Chapter 1 Introduction Conventional Programming Environment (PC, Macintosh, or Sun SPARCstation) LabVIEW (PC, Macintosh, or Sun SPARCstation) LabWindows/CVI (PC or Sun SPARCstation) NI-DAQ Driver Software Personal Computer or Workstation DAQ or SCXI Hardware Figure 1-1.
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a.Book : e.chapter 1 Page 6 Wednesday, November 20, 1996 6:36 PM Chapter 1 Introduction The mating connector for the PC-LPM-16/PnP is a 50-position, polarized, ribbon socket connector with strain relief. National Instruments uses a polarized (keyed) connector to prevent inadvertent upside-down connection to the PC-LPM-16/PnP.
a.Book : f.chapter 2 Page 1 Wednesday, November 20, 1996 6:36 PM Chapter Installation and Configuration 2 This chapter describes the installation and configuration of the PC-LPM-16PnP. For information on installing and configuring the PC-LPM-16, a non-PnP board, refer to Appendix C, Using Your PC-LPM-16 (Non-PnP) Board. Hardware Installation You can install the PC-LPM-16PnP in any available expansion slot in your computer.
a.Book : f.chapter 2 Page 2 Wednesday, November 20, 1996 6:36 PM Chapter 2 Installation and Configuration Software Installation If you are using NI-DAQ, refer to your NI-DAQ release notes to install your driver software. Find the installation section for your operating system and follow the instructions given there. If you are using LabVIEW, refer to your LabVIEW release notes to install your application software.
a.Book : f.chapter 2 Page 3 Wednesday, November 20, 1996 6:36 PM Chapter 2 Installation and Configuration Base I/O Address and Interrupt Selection You can configure your PC-LPM-16PnP to use base addresses in the range of 100 to FFF0 hex. The PC-LPM-16PnP occupies 16 bytes of address space and must be located on a 16-byte boundary. Therefore, valid addresses include 100, 110, 120…, FFE0, FFF0 hex. This selection is software-configured and does not require you to manually change any settings on the board.
a.Book : g.chapter 3 Page 1 Wednesday, November 20, 1996 6:36 PM Chapter Theory of Operation 3 This chapter includes an overview of the PC-LPM-16PnP board and explains the operation of each functional unit making up the board. This chapter also explains the basic operation of the PC-LPM-16PnP circuitry.
a.Book : g.chapter 3 Page 2 Wednesday, November 20, 1996 6:36 PM Theory of Operation PC I/O Channel Interface 12-Bit Sampling ADC 256-Word FIFO Input Mux 16-Channel Single-Ended Buffer Scanning Counter Plug and Play OUT0 EXTCONV* PC I/O Channel A/D Timing 1 MHz 16 CLK0 MSM82C53 GATE<0..2> CLK<1..2> 3 OUT<0..2> 3 2 OUT1 Interrupt Interface OUT1* EXTINT* I/O Connector Chapter 3 FROM A/D FIFO 8 Digital I/O 8 +12 V +12 V 0.5 A -12 V +5 V -12 V +5 V 1.0 A Figure 3-1.
a.Book : g.chapter 3 Page 3 Wednesday, November 20, 1996 6:36 PM Chapter 3 Theory of Operation PC I/O Channel Interface Circuitry The PC I/O channel interface circuitry consists of an address bus, a data bus, interrupt lines, and several control and support signals. The components making up the PC-LPM-16PnP PC I/O channel interface circuitry are shown in Figure 3-2.
a.Book : g.chapter 3 Page 4 Wednesday, November 20, 1996 6:36 PM Chapter 3 Theory of Operation request lines available: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, and IRQ9. The PC-LPM-16PnP generates interrupts in three different situations: • When an A/D conversion generates data that can be read from FIFO • When an active low-level signal is detected on the EXTINT* line • When a rising-edge signal is detected on counter 2 output The PC-LPM-16PnP individually enables and clears each one of these interrupts.
a.Book : g.chapter 3 Page 5 Wednesday, November 20, 1996 6:36 PM Chapter 3 Theory of Operation Analog Input Circuitry The analog input circuitry consists of an input multiplexer, a jumperselectable gain stage, and a 12-bit sampling ADC. The 12-bit output is sign-extended to 16 bits before it is stored in a 256-word deep FIFO memory. The input multiplexer stage is made up of a CMOS analog input multiplexer and has 16 analog input channels (channels 0 through 15).
a.Book : g.chapter 3 Page 6 Wednesday, November 20, 1996 6:36 PM Chapter 3 Theory of Operation ADC goes through a self-calibration cycle under software control. To properly use this ADC auto-calibration feature, you need an accurate input stage that does not introduce significant offset and gain errors. The analog input stage on the PC-LPM-16PnP maintains the required accuracy without trimpot adjustments.
a.Book : g.chapter 3 Page 7 Wednesday, November 20, 1996 6:36 PM Chapter 3 Theory of Operation Single-Channel Data Acquisition During single-channel data acquisition, the channel-select bits in Command Register 1 select the analog input channel before data acquisition begins. This multiplexer setting remains constant during the entire data acquisition process; therefore, all A/D conversion data is read from a single channel.
a.Book : g.chapter 3 Page 8 Wednesday, November 20, 1996 6:36 PM Chapter 3 Theory of Operation Digital I/O Circuitry The PC-LPM-16PnP has 16 digital I/O lines that are TTL-compatible. Pins DIN<0..7> of the I/O connector are digital input lines, and pins DOUT<0..7> are digital output lines. These lines are monitored or driven by the Digital Input Register or the Digital Output Register, respectively. Reading the Digital Input Register returns the current state of the DIN<0..7> lines.
a.Book : g.chapter 3 Page 9 Wednesday, November 20, 1996 6:36 PM Chapter 3 Theory of Operation Timing I/O Circuitry The PC-LPM-16PnP uses an MSM82C53 Counter/Timer integrated circuit for data acquisition timing and for general-purpose timing I/O functions. Three counters on the circuit are available for general use, but the board can use only one of them, counter 0, internally for data acquisition timing. Figure 3-5 shows a block diagram of both groups of timing I/O circuitry.
a.Book : g.chapter 3 Page 10 Wednesday, November 20, 1996 6:36 PM Chapter 3 Theory of Operation CLK Counter OUT GATE Figure 3-6. Counter Block Diagram Each counter has a clock input pin, a gate input pin, and an output pin labeled CLK, GATE, and OUT, respectively. The MSM82C53 counters are numbered zero through two, and their GATE, CLK, and OUT pins are labeled GATEN, CLKN, and OUTN, where N is the counter number.
a.Book : h.chapter 4 Page 1 Wednesday, November 20, 1996 6:36 PM Chapter 4 Signal Connections This chapter describes how to make input and output signal connections to your PC-LPM-16PnP board via the I/O connector. I/O Connector Figure 4-1 shows the pin assignments for the PC-LPM-16PnP I/O connector. This connector is located on the back panel of the board and is accessible from the back of your computer after you have properly installed the board.
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a.Book : h.chapter 4 Page 3 Wednesday, November 20, 1996 6:36 PM Chapter 4 Signal Connections Signal Connection Descriptions Table 4-1. Pin Signal Signal Connection Descriptions Reference Description 1–2 AIGND N/A Analog Input Ground—The pins are connected to the analog input ground signal. ACH<0..15> signals should be referenced to AIGND. 3–18 ACH<0..15> AGND Analog Input Channels 0 through 15— These channels are single-ended.
a.Book : h.chapter 4 Page 4 Wednesday, November 20, 1996 6:36 PM Chapter 4 Signal Connections Table 4-1. Signal Pin Signal Connection Descriptions (Continued) Reference Description 40 EXTCONV* DGND External Convert Signal—This input signal externally initiates an A/D conversion. 41 OUT0 DGND Output of Counter 0—This signal outputs the programmed waveform of counter 0. 42 GATE0 DGND Counter 0 Gate Input—This signal controls the starting, interruption, and restarting of counter 0.
a.Book : h.chapter 4 Page 5 Wednesday, November 20, 1996 6:36 PM Chapter 4 Signal Connections The connector pins can be grouped into categories of analog input signal pins, digital I/O signal pins, and timing I/O signal pins. Signal connection guidelines for each of these groups follow. Analog Input Signal Connections Pins 3 through 18 are analog input signal pins for the ADC. Pins 1 and 2 are analog common signals. You can use these pins for a general analog power ground tie to the PC-LPM-16PnP.
a.Book : h.chapter 4 Page 6 Wednesday, November 20, 1996 6:36 PM Chapter 4 Signal Connections ACH<0..15> 3 4 Signal Source 5 + + Vs1 V S3 VS2 - Operational Amplifier + - + 18 + Input Multiplexer 1, 2 VM - Measured Voltage AIGND - I/O Connector PC-LPM-16PnP Figure 4-2. Analog Input Signal Connections Digital I/O Signal Connections See Table 4-1 for the digital I/O pin descriptions.
a.Book : h.chapter 4 Page 7 Wednesday, November 20, 1996 6:36 PM Chapter 4 22 DIN 0 Signal Connections Digital Input TTL Signal 29 DIN 7 +5 V Port Debounced Switch* 19 +5 V Digital LED DGND Output 30 DOUT 0 Port I/O Connector PC-LPM-16PnP *Complex switch circuitry is not shown here in order to simplify the figure. Figure 4-3. Analog Input Signal Connections Figure 4-3 shows the connections of the digital input port and digital output port.
a.Book : h.chapter 4 Page 8 Wednesday, November 20, 1996 6:36 PM Chapter 4 Signal Connections fuse in series. Both fuses are self-resetting; simply remove the circuit causing the heavy current load and the fuse will reset itself. Power Rating The following table shows the maximum current for each power line at the I/O connector. Power Line Maximum Current +5 V (self-resetting fuse at 1.0 A) 1.0 A* +12 V (self-resetting fuse at 0.5 A) 0.5 A* -12 V 5.
a.Book : h.chapter 4 Page 9 Wednesday, November 20, 1996 6:36 PM Chapter 4 Signal Connections tw EXTCONV* V IH V t IL t t int w 200 ns min int 20 µs min (A/D interval) A/D Conversion Starts within 800 ns of this Edge Figure 4-4.
a.Book : h.chapter 4 Page 10 Wednesday, November 20, 1996 6:36 PM Chapter 4 Signal Connections +5 V 4.7 kW CLK OUT GATE Debounced Switch* Counter Signal Source 19 DGND I/O Connector PC-LPM-16PnP *Complex switch circuitry is not shown here in order to simplify the figure. Figure 4-5. Event-Counting Application with External Switch Gating Perform pulse-width measurement by level gating to trigger the counter. Apply the pulse to be measured to the counter GATE input.
a.Book : h.chapter 4 Page 11 Wednesday, November 20, 1996 6:36 PM Chapter 4 Signal Connections duration. In this case, program the counter to count falling edges at the CLK input while the gate is applied. The frequency of the input signal then equals the count value divided by the gate period. Figure 4-6 shows the connections for a frequency measurement application. You could also use a second counter to generate the gate signal in this application. +5 V 4.
a.Book : h.chapter 4 Page 12 Wednesday, November 20, 1996 6:36 PM Chapter 4 Signal Connections MSM82C53 digital input specifications (referenced to DGND): • VIH input logic high voltage 2.2 V min • VIL input logic low voltage 0.8 V max • Input load current ± 10.0 µA max MSM82C53 digital output specifications (referenced to DGND): • VOH output logic high voltage 3.7 V min • VOL output logic low voltage 0.45 V max • IOH output source current, at VOH 1.
a.Book : I.Appendix A Page 1 Wednesday, November 20, 1996 6:36 PM Appendix A Specifications This appendix lists the PC-LPM-16PnP specifications. These specifications are typical at 25° C unless otherwise specified. The operating temperature range is 0° to 70° C. PC-LPM-16PnP Board Analog Input Input Characteristics Number of channels ........................... 16 single-ended Type of ADC...................................... Successive approximation Resolution .........................................
a.Book : I.Appendix A Page 2 Wednesday, November 20, 1996 6:36 PM Appendix A Specifications Gain error (relative to calibration reference) After calibration 0 to 5 V and ± 5 V range ...............± 1.0 LSB typ, ± 2.0 LSB max All other ranges............................± 2.0 of reading typ, ± 4.0 max Note: LSB refers to the least significant bit of a 12-bit conversion value in the preceding specifications. LSB is equivalent to 2.44 mV in the 10 V range (0 to 10 V or ± 5 V) and 1.
a.Book : I.Appendix A Page 3 Wednesday, November 20, 1996 6:36 PM Appendix A Digital logic levels ............... Specifications Minimum Maximum Input low voltage 0V 0.8 V Input high voltage 2V 5.0 V Input low current (Vin = 0 V) — ±10 µA Input high current (Vin = 5 V) — ±10 µA Level Minimum Maximum Output low voltage (Iout = 4 mA) — 0.4 V Output high voltage (Iout = 4 mA) 3.7 V — Level Timing I/O Number of channels ...........................
a.Book : I.Appendix A Page 4 Wednesday, November 20, 1996 6:36 PM Appendix A Specifications Bus Interface Type.................................................... Slave Power Requirement +5 VDC (± 10%).................................. 50 mA typ +12 VDC (± 5%).................................. 15 mA typ -12 VDC (± 5%) .................................. 15 mA typ Note: These numbers do not include an additional 1 A from the 5 V power supply. The 50-pin I/O connector can draw 0.5 A from the +12 V supply.
a.Book : I.Appendix A Page 5 Wednesday, November 20, 1996 6:36 PM Appendix A Specifications sum of quantization uncertainty and A/D conversion error does not exceed a given amount. Integral nonlinearity in a ADC is an often ill-defined specification that is supposed to indicate a converter’s overall A/D transfer linearity.
a.Book : I.Appendix A Page 6 Wednesday, November 20, 1996 6:36 PM Appendix A Specifications To illustrate these definitions, Figure A-1 shows a portion of the analog-input-to-digital-output transfer curve for an ideal, ADC overlaid on the transfer curve of a hypothetical, typical, ADC. As shown in Figure A-1, the relative accuracy is the deviation of the code transition voltage from the center of the code for an ideal ADC, expressed in terms of LSBs.
Appendix MSM82C53 Data Sheet B This appendix contains a manufacturer data sheet for the MSM82C53* CMOS programmable interval timer (OKI Semiconductor). This timer is used on the PC-LPM-16PnP board. *Copyright ΟΚΙ Semiconductor 1995. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor Data Book Microprocessor, Eight Edition, January 1995.
Appendix B MSM82C53 Data Sheet PC-LPM-16/PnP User Manual B-2 © National Instruments Corporation
Appendix B © National Instruments Corporation B-3 MSM82C53 Data Sheet PC-LPM-16/PnP User Manual
Appendix B MSM82C53 Data Sheet PC-LPM-16/PnP User Manual B-4 © National Instruments Corporation
Appendix B © National Instruments Corporation B-5 MSM82C53 Data Sheet PC-LPM-16/PnP User Manual
Appendix B MSM82C53 Data Sheet PC-LPM-16/PnP User Manual B-6 © National Instruments Corporation
Appendix B © National Instruments Corporation B-7 MSM82C53 Data Sheet PC-LPM-16/PnP User Manual
Appendix B MSM82C53 Data Sheet PC-LPM-16/PnP User Manual B-8 © National Instruments Corporation
Appendix B © National Instruments Corporation B-9 MSM82C53 Data Sheet PC-LPM-16/PnP User Manual
Appendix B MSM82C53 Data Sheet PC-LPM-16/PnP User Manual B-10 © National Instruments Corporation
Appendix B © National Instruments Corporation B-11 MSM82C53 Data Sheet PC-LPM-16/PnP User Manual
Appendix B MSM82C53 Data Sheet PC-LPM-16/PnP User Manual B-12 © National Instruments Corporation
Appendix Using Your PC-LPM-16 (Non-PnP) Board C This appendix describes the differences between the PC-LPM-16PnP and the PC-LPM-16 non-PnP boards, the PC-LPM-16 board configuration, and installing the PC-LPM-16 into your computer. Differences between the PC-LPM-16PnP and the PC-LPM-16 The PC-LPM-16PnP is a Plug and Play upgrade from a legacy board, the PC-LPM-16. A National Instruments legacy product refers to an older board with switches and jumpers used to set the addresses.
Appendix C Using Your PC-LPM-16 (Non-PnP) Board Table C-1.
Appendix C Table C-1.
Appendix C Using Your PC-LPM-16 (Non-PnP) Board Configuration and Installation of the PC-LPM-16 (non-PnP) Board Configuration The PC-LPM-16 contains three jumpers and one DIP switch to configure the PC bus interface and analog input settings. Use the DIP switch to set the base I/O address. Jumper W3 selects the interrupt level. Jumpers W1 and W2 configure the analog input circuitry. The DIP switch and jumpers are shown in the parts locator diagram in Figure C-1.
Appendix C Using Your PC-LPM-16 (Non-PnP) Board 5 6 4 7 3 2 1 1 2 W3 Switch U26 3 4 W2 W1 5 6 Serial Number Assembly Number 7 Product Name Figure C-1.
Appendix C Using Your PC-LPM-16 (Non-PnP) Board Base I/O Address Selection The base I/O address for the PC-LPM-16 is determined by the switches at position U26 (see Figure C-2). The switches are set at the factory for the base I/O address hex 260. This factory setting is used as the default base I/O address value by National Instruments software packages for use with the PC-LPM-16. The PC-LPM-16 uses the base I/O address space hex 260 through 26F with the factory setting.
Appendix C Using Your PC-LPM-16 (Non-PnP) Board Each switch in U26 corresponds to one of the address lines A9 through A5. Slide the switch to the side labeled A9 to A5 to select a binary value of zero for the corresponding address bit. Slide the switch to the side of the switch labeled ON to select a binary value of one for the corresponding address bit. Figure C-2 shows two possible switch settings. U26 –Slide to this side for 0 A9 A8 A7 A6 A5 –Slide to this side for 1 a.
Appendix C Using Your PC-LPM-16 (Non-PnP) Board possible switch settings, the corresponding base I/O address, and the base I/O address space used for that setting. Table C-3.
Appendix C Table C-3. Using Your PC-LPM-16 (Non-PnP) Board Switch Settings with Corresponding Base I/O Address and Base I/O Address Space (Continued) Switch Setting Base I/O Address (hex) Base I/O Address Space Used (hex) A9 A8 A7 A6 A5 Note: 1 1 0 1 0 340 340–34F 1 1 0 1 1 360 360–36F 1 1 1 0 0 380 380–38F 1 1 1 0 1 3A0 3A0–3AF 1 1 1 1 0 3C0 3C0–3CF 1 1 1 1 1 3E0 3E0–3EF Base I/O address values hex 000 through 0FF are reserved for system use.
Using Your PC-LPM-16 (Non-PnP) Board W3 Appendix C IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 W2 Figure C-3. Interrupt Jumper Setting IRQ5 (Factory Setting) W3 If you do not want to use interrupts, set the jumper on W3 as shown in Figure C-4. This setting disables the PC-LPM-16 from asserting an interrupt line on the computer I/O channel. IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 W2 Figure C-4.
Appendix C W1 Using Your PC-LPM-16 (Non-PnP) Board W2 A A B B C C Figure C-5. Bipolar Input (±5 V) Jumper Configuration (Factory Setting) Bipolar Input Selection 2 (±2.5 V) Select the bipolar (± 2.5 V) input configuration by setting jumpers W1 and W2 as shown in Figure C-6. W1 W2 A A B B C C Figure C-6. Bipolar Input (±2.
Appendix C Using Your PC-LPM-16 (Non-PnP) Board Unipolar Input Selection 2 (0 to 5 V) Select the unipolar (0 to 5 V) input configuration by using the same setting as the ± 5 V range setting shown in Figure C-5. You can use this setting because the ADC is 12-bit. Therefore, 12-bit resolution data is obtained in both the 0 to +5 V signal range and the 0 to -5 V signal range while keeping the input configuration for ± 5 V input range.
a.Book : l.Appendix D Page 1 Wednesday, November 20, 1996 6:36 PM Appendix Register-Level Programming D This appendix describes in detail information related to register-level programming the PC-LPM-16/PnP. Note: If you plan to use a programming software package such as NI-DAQ, LabVIEW, or LabWindows/CVI with your PC-LPM-16/PnP, you need not read this appendix. Base Address For information on the base address, see Chapter 2, Installation and Configuration.
a.Book : l.Appendix D Page 2 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Table D-1.
a.Book : l.Appendix D Page 3 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Register Description Format The remainder of this appendix discusses each of the PC-LPM-16/PnP registers in the order shown in Table D-1. Each register group is introduced, followed by an individual register description. The individual register description includes the address, type, word size, and bit map of the register.
a.Book : l.Appendix D Page 4 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Command Register 1 Command Register 1 indicates the input channel to be read and the interrupt enable bits. Address: Base address + 00 (hex) Type: Write-only Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 SCANEN* CNTINTEN EXTINTEN FIFOINTEN MA3 MA2 MA1 MA0 Bit Name Description 7 SCANEN* Scan Enable Bit—This bit enables or disables multichannel scanning during data acquisition.
a.Book : l.Appendix D Page 5 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Command Register 1 (Continued) 6 CNTINTEN Counter Interrupt Enable Bit—With this bit, the counter 2 output can cause interrupts. The power-on value is 0. If this bit is set, an interrupt occurs when counter 2 output makes a low-to-high transition. Clear this interrupt by writing to the Timer Interrupt Clear Register. If this bit is cleared, interrupts from counter 2 output are ignored.
a.Book : l.Appendix D Page 6 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Command Register 1 (Continued) MA<3..0> Selected Channel 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 If SCANEN* is cleared, analog channels MA<3..0> through channel 0 are sampled. Sampling order, whether from channel 0 to MA<3..0> or from MA<3..0> to channel 0, is determined by the SCANORDER bit in Command Register 2.
a.Book : l.Appendix D Page 7 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Command Register 2 Command Register 2 contains only one bit that enables the auto-calibration operation of the ADC. Address: Base address + 07 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 0 0 0 0 0 SCANORDER DISABDAQ CALEN Bit Name Description 7–3 0 Reserved bits—These bits must be set to zero for future board compatibility.
a.Book : l.Appendix D Page 8 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Command Register 2 (Continued) Bit Name Description 0 CALEN Calibration Enable Bit—If this bit is set, the autocalibration of the 12 bit ADC is enabled. The poweron value is 0. To start the auto-calibration, first write one to this bit, then read this register. The result of the reading is ignored. An auto-calibration lasts about 10 ms.
a.Book : l.Appendix D Page 9 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Command Register 3 Command Register 3 contains other range setting configuration bits. Address: 05 (hex) Type: Write-only Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ARNG<1> ARNG<0> Bit Name Description 7–2 0 Reserved Bits—These bits must be set to zero. 1–0 ARNG<1..
a.Book : l.Appendix D Page 10 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Status Register 1 Status Register 1 indicates the status of the current A/D conversion. The bits in this register determine if a conversion is being performed, if data is available, if any errors have been found, and the interrupt status.
a.Book : l.Appendix D Page 11 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Status Register 1 (Continued) Bit Name Description 3 EXTINT* External Interrupt Status Bit—This bit reflects the status of the EXTINT* signal on the I/O connector. If the EXTINTEN bit in Command Register 1 is set and this bit is cleared, the external EXTINT* signal has caused the current interrupt.
a.Book : l.Appendix D Page 12 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming 0 DAVAIL Data Available Bit—This bit indicates whether conversion output is available. If this bit is set, the ADC is finished with the last conversion and the result can be read from the FIFO. This bit is cleared if the FIFO is empty. Writing to the ADCLR Register sets this bit on the PC-LPM-16 only. You need a FIFO (low and high bytes) reading to completely empty the PC-LPM-16 FIFO.
a.Book : l.Appendix D Page 13 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Status Register 2 Status Register 2 contains supplementary error information. This register is only on the PC-LPM-16PnP. Address: 01(hex) Type: Read-only Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 X X X X X X OVERFLOW OVERRUN Bit Name Description 7–2 X Don’t care bits. 1 OVERFLOW Overflow Bit—This bit indicates if an overflow error has occurred.
a.Book : l.Appendix D Page 14 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Analog Input Register Group The three registers that make up the Analog Input Register Group control the analog input circuitry and can be used to read the FIFO. Reading the FIFO Register returns stored A/D conversion results. Writing to the A/D Clear Register clears the data acquisition circuitry.
a.Book : l.Appendix D Page 15 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming A/D FIFO Low-Byte Register and A/D FIFO High-Byte Register The 13-bit A/D conversion results are sign-extended to 16-bit data in two’s complement format and are stored in a 16-word deep A/D FIFO buffer. Two 8-bit registers, the A/D FIFO Low-Byte Register and the A/D FIFO High-Byte Register, must be read to return an A/D conversion value stored in the A/D FIFO.
a.Book : l.Appendix D Page 16 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming A/D FIFO Low-Byte Register and A/D FIFO High-Byte Register (Continued) Bit Name Description D<15..8> A/D Conversion Data Bits 15 through 8—These bits contain the high byte of the 16-bit, sign-extended two’s complement result of a 13-bit A/D conversion. Values made up of D<15..0>, therefore, range from -4096 to +4095 decimal (F000 to 0FFF hex).
a.Book : l.Appendix D Page 17 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming A/D Clear Register Write to this register to reset the ADC. This operation clears the data FIFO. All error bits in the Status Register are cleared as well. For the PC-LPM-16 (non PnP only), writing to this register clears the data FIFO and loads a single conversion into the FIFO. After writing to the A/D Clear Register, it is necessary to read both the High- and Low-Byte FIFOs.
a.Book : l.Appendix D Page 18 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Counter/Timer (MSM82C53) Register Group The five registers making up the Counter/Timer Register Group access the onboard MSM82C53 counter/timer. The MSM82C53 has three counters: counter 0, counter 1, and counter 2. Counter 0 controls onboard data acquisition timing, and all three counters are available for general-purpose timing functions.
a.Book : l.Appendix D Page 19 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Counter 0 Data Register Use the Counter 0 Data Register to load and read back contents of MSM82C53 counter 0. Address: Base address + 08 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7–0 D<7..0> A/D Conversion Data Bits 7 through 0—8-bit counter 0 contents.
a.Book : l.Appendix D Page 20 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Counter 1 Data Register Use the Counter 1 Data Register to load and read back contents of MSM82C53 counter 1. Address: Base address + 09 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7–0 D<7..0> A/D Conversion Data Bits 7 through 0—8-bit counter 1 contents.
a.Book : l.Appendix D Page 21 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Counter Mode Register The Counter Mode Register determines the operation mode for each of the three counters on the MSM82C53 chip. The Counter Mode Register selects the counter involved, the counter’s read/load mode, its operation mode (that is, any of the six operation modes of the MSM82C53), and the counting mode (binary or BCD). The Counter Mode Register is an 8-bit register.
a.Book : l.Appendix D Page 22 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Counter Mode Register (Continued) 5–4 RL<1..0> Read/Write Select Bits—These bits select data written to or read from a counter, or these bits send a Counter Latch command.
a.Book : l.Appendix D Page 23 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Counter Mode Register (Continued) 3–1 0 M<2..0> BCD National Instruments Corporation Counter Mode Select Bits—These bits select the counting mode of the selected counter. The following table lists six available modes and the corresponding bit settings. Refer to Appendix B, MSM82C53 Data Sheet, for additional information.
a.Book : l.Appendix D Page 24 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Timer Interrupt Clear Register Write to the Timer Interrupt Clear Register to clear the interrupt request asserted when a low pulse is detected on the counter 2 output. Address: Base address + 06 (hex) Type: Write-only Word Size: 8-bit Bit Map: Not applicable, no bits used.
a.Book : l.Appendix D Page 25 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Digital Input Register Read the Digital Input Register to return the logic state of the I/O connector’s eight digital input lines. Address: Base address + 05 (hex) Type: Read-only Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7–0 D<7..
a.Book : l.Appendix D Page 26 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Programming Considerations Following are programming instructions for operating the circuitry on the PC-LPM-16/PnP. To program the PC-LPM-16/PnP, you must write to and read from the various registers on the board.
a.Book : l.Appendix D Page 27 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming This sequence leaves the PC-LPM-16/PnP circuitry in the following state: • Counter 0 output is high. • Multichannel scan is disabled. • All interrupts are disabled. • Analog input circuitry is initialized to channel 0. • The A/D FIFO is cleared. For additional details concerning the MSM82C53 counter/timer, see Appendix B, MSM82C53 Data Sheet.
a.Book : l.Appendix D Page 28 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Analog Input Circuitry Programming Sequence 1. Initiate an A/D conversion. A low to high transition on OUT0 or on EXTCONV* initiates A/D conversion. Clear the CALEN bit in Command Register 2 to enable counter 0 and the EXTCONV*. When an A/D conversion is initiated, the ADC stores the result in the A/D FIFO at the end of its conversion cycle.
a.Book : l.Appendix D Page 29 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming A/D FIFO Output Binary Modes The A/D conversion result stored in the A/D FIFO is a 16-bit two’s complement value. It is made of 13-bit magnitude and 3-bit sign extension. If the analog input range is unipolar 0 to +10 V or unipolar 0 to +5 V, use the positive values only, making the resolution 12-bit. If the analog input range is ±5 V or ±2.
a.Book : l.Appendix D Page 30 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Table D-3. Input Voltage Bipolar Input Mode A/D Conversion Values A/D Conversion Result A/D Conversion Result Range: -5 to +5 V Divided by 2 (13-bit values) (12-bit values) (Decimal) (Hex) (Decimal) (Hex) -5.0 -4,096 F000 -2,048 F800 -2.5 -2,048 F800 -1,024 FC00 0 0 0000 0 0000 2.5 2,048 0800 1,024 0400 4.
a.Book : l.Appendix D Page 31 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming after getting the required number of conversions. The number of conversions in a single data acquisition operation in this case is unlimited. Counter 0 is clocked by a 1 MHz clock upon start up. Each of these programming steps is explained as follows. 1. Select the Analog Input Channel. Write to Command Register 1 to select the analog input channel.
a.Book : l.Appendix D Page 32 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming during the programming. Write 0 to the A/D Clear Register to empty the FIFO (8-bit write), then read the low and high bytes from the A/D FIFO (PC-LPM-16 only). 4. Start and service the data acquisition operation. To start the data acquisition operation, write the most significant byte of the sample interval to the Counter 0 Data Register. This enables counter 0 to start counting.
a.Book : l.Appendix D Page 33 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Programming Multiple A/D Conversions Using External Timing You can use the external timing signal EXTCONV* for multiple A/D conversions. A low-to-high transition of EXTCONV* initiates an A/D conversion. Software can also initiate a data acquisition operation. Setting the DISABDAQ bit in Command Register 2 disables the EXTCONV* signal.
a.Book : l.Appendix D Page 34 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming service the data acquisition, perform the following sequence until you have read the desired number of conversion results: 1. Read the Status Register 2. If the DAVAIL bit is set, read the A/D FIFO Low-Byte Register first, then read the A/D FIFO High-Byte Register, to get the result. Interrupts can also be used to service the data acquisition operation.
a.Book : l.Appendix D Page 35 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming UP/DOWN bit in Command Register 2 is cleared—the software uses the following scan sequence: channel 3, channel 2, channel 1, channel 0, channel 3, channel 2, channel 1, channel 0, channel 3, and so on. Perform the following steps to select the analog input channel: 1. Note: Program the UP/DOWN bit in Command Register 2 if the bit is not already set to the desired value.
a.Book : l.Appendix D Page 36 Wednesday, November 20, 1996 6:36 PM Appendix D Register-Level Programming Programming the MSM82C53 Counter/Timer Counters 0, 1, and 2 of the MSM82C53 counter/timer (except the CLK0 signal of counter 1) are available for general-purpose timing applications. Counter 0 has a fixed 1 MHz clock input and can be used as the sample interval counter of A/D conversion. Write and read operations to the MSM82C53 are 8-bit operations.
a.Book : m.Appendix E Page 1 Wednesday, November 20, 1996 6:36 PM Appendix Customer Communication E For your convenience, this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation.
a.Book : m.Appendix E Page 2 Wednesday, November 20, 1996 6:36 PM Fax-on-Demand Support Fax-on-Demand is a 24-hour information retrieval system containing a library of documents on a wide range of technical information. You can access Fax-on-Demand from a touch-tone telephone at (512) 418-1111. E-Mail Support (currently U.S. only) You can submit technical support questions to the applications engineering team through e-mail at the Internet address listed below.
a.Book : m.Appendix E Page 3 Wednesday, November 20, 1996 6:36 PM Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
a.Book : m.Appendix E Page 5 Wednesday, November 20, 1996 6:36 PM PC-LPM-16/PnP Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.
a.Book : m.Appendix E Page 7 Wednesday, November 20, 1996 6:36 PM Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: PC-LPM-16/PnP User Manual Edition Date: November 1996 Part Number: 320287C-01 Please comment on the completeness, clarity, and organization of the manual.
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Index Numbers analog input jumper settings, PC-LPM-16, C-10 to C-12 bipolar input selection 1 (±5 V) C-10 to C-11 bipolar input selection 2 (±2.
Index B board configuration. See configuration. bulletin board support, E-1 bus interface specifications, A-4 base I/O address selection PC-LPM-16, C-5 to C-9 example switch settings (figure), C-7 PC bus interface factory settings (table), C-6 switch settings with corresponding base I/O address (table), C-8 to C-9 PC-LPM-16PnP, 2-3 BCD bits, D-23 bipolar input selection 1 (±5 V) C-10 to C-11 bipolar input selection 2 (±2.5 V) C-11 bits ARNG<1..
Index switch settings with corresponding base I/O address (table), C-8 to C-9 block diagram, revised, C-4 interrupt selection, C-9 to C-10 disabling interrupts (figure), C-10 IRQ5 factory setting (figure), C-10 overview, C-4 to C-5 parts locator diagram, revised, C-5 PC-LPM-16PnP. See also installation.
Index G digital I/O circuitry, 3-8 programming digital I/O circuitry, D-35 DISABDAQ bit, D-7, D-33 documentation conventions used in manual, x-xi National Instruments documentation, xi-xii organization of manual, ix-x related documentation, xii DOUT<0..
Index O interrupt selection PC-LPM-16, C-9 to C-10 disabling interrupts (figure), C-10 IRQ5 factory setting (figure), C-10 PC-LPM-16PnP, 2-3 I/O connector exceeding maximum ratings (warning), 4-1 pin assignments (figure), 4-2 operation of PC-LPM-16PnP. See theory of operation.
Index Plug and Play compatibility, 2-2 to 2-3 power connections, 4-7 power rating (table), 4-8 power requirement specifications, A-4 overview, D-3 Status Register 1, D-10 to D-12 Status Register 2, D-13 Counter/Timer (MSM82C53) Register Group Counter 0 Data Register, D-19, D-30 to D-32 Counter 1 Data Register, D-20 Counter 2 Data Register, D-20 Counter Mode Register, D-21 to D-23 overview, D-18 programming, D-36 Timer Interrupt Clear Register, D-24 Digital I/O Register Group Digital Input Register, D-25 D
Index T power rating (table), 4-8 signal descriptions (table), 4-3 to 4-4 timing connections, 4-8 to 4-12 data acquisition timing connections, 4-8 to 4-9 general purpose timing signal connections, 4-9 to 4-12 single-channel data acquisition, 3-7 software installation, 2-2 software programming choices, 1-2 to 1-4 LabVIEW and LabWindows/CVI application software, 1-2 to 1-3 NI-DAQ driver software, 1-3 to 1-4 register-level programming, 1-4 specifications analog input, A-1 to A-2 ADC errors (figure), A-6 ampl
