PC-DIO-96 User Manual Digital I/O Board for the IBM PC/XT/AT September 1995 Edition Part Number 320289B-01 © Copyright 1990, 1995 National Instruments Corporation. All Rights Reserved.
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Limited Warranty The PC-DIO-96 is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer.
Contents Chapter 1 About This Manual ............................................................................................................ v Organization of This Manual ........................................................................................ v Conventions Used in This Manual ................................................................................ vi National Instruments Documentation ............................................................................
Contents Chapter 4 Register-Level Programming ......................................................................................... 4-1 Introduction ................................................................................................................... 4-1 Register Map ................................................................................................................. 4-2 Register Descriptions .....................................................................................
Contents Figures Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware ........................................................................................................... 1-3 Figure Figure Figure Figure Figure Figure Figure PC-DIO-96 Parts Locator Diagram ................................................................... 2-2 Example Base I/O Address Switch Settings......................................................
Contents Chapter 1 About This Manual ............................................................................................................ v Organization of This Manual ........................................................................................ v Conventions Used in This Manual ................................................................................ vi National Instruments Documentation ............................................................................
Contents Chapter 4 Register-Level Programming ......................................................................................... 4-1 Introduction ................................................................................................................... 4-1 Register Map ................................................................................................................. 4-2 Register Descriptions .....................................................................................
Contents Figures Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware ........................................................................................................... 1-3 Figure Figure Figure Figure Figure Figure Figure PC-DIO-96 Parts Locator Diagram ................................................................... 2-2 Example Base I/O Address Switch Settings......................................................
About This Manual This manual describes the mechanical and electrical aspects of the PC-DIO-96 and contains information concerning its operation and programming. The PC-DIO-96 is a 96-bit parallel digital I/O interface designed around four OKI Semiconductor (OKI) 82C55A programmable peripheral interface (PPI) chips. The PC-DIO-96 also includes an Advanced Micro Devices (AMD) 8253 counter/timer which can be used to send periodic interrupts to the host system.
Preface • The Glossary contains an alphabetical list and description of terms used in this manual, including abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms. • The Index alphabetically lists the topics in this manual, including the page where you can find each one. Conventions Used in This Manual The following conventions are used in this manual: bold Bold text denotes menus, menu items, or dialog box buttons or options.
Preface National Instruments Documentation The PC-DIO-96 User Manual is one piece of the documentation set for your data acquisition (DAQ) system. You could have any of several types of manuals, depending on the hardware and software in your system. Use the different types of manuals you have as follows: • Getting Started with SCXI—If you are using SCXI, this is the first manual you should read.
Chapter 1 Introduction This chapter describes the PC-DIO-96, lists what you need to get started, describes software programming choices, optional equipment, and custom cables, and explains how to unpack the PC-DIO-96. About the PC-DIO-96 Thank you for purchasing the National Instruments PC-DIO-96. The PC-DIO-96 is a 96-bit, parallel, digital, I/O interface for the PC. Four 82C55A PPI chips control the 96 bits of digital I/O.
Introduction Chapter 1 What You Need to Get Started To set up and use your PC-DIO-96, you will need the following: PC-DIO-96 board PC-DIO-96 User Manual One of the following software packages and documentation: NI-DAQ for PC compatibles LabVIEW for Windows LabWindows/CVI for Windows Your computer Software Programming Choices There are several options to choose from when programming your National Instruments DAQ and SCXI hardware. You can use LabVIEW, LabWindows/CVI, or NI-DAQ. A 4.6.
Chapter 1 Introduction NI-DAQ Driver Software The NI-DAQ driver software is included at no charge with all National Instruments DAQ hardware. NI-DAQ is not packaged with SCXI or accessory products, except for the SCXI-1200. NI-DAQ has an extensive library of functions that you can call from your application programming environment.
Introduction Chapter 1 Register-Level Programming The final option for programming any National Instruments DAQ hardware is to write registerlevel software. Writing register-level programming software can be very time-consuming and inefficient, and is not recommended for most users. Even if you are an experienced register-level programmer, consider using NI-DAQ, LabVIEW, or LabWindows/CVI to program your National Instruments DAQ hardware.
Chapter 1 Introduction The CB-100 is useful for initial prototyping of an application or in situations where PC-DIO-96 interconnections are frequently changed. Once a final field wiring scheme has been developed, however, you may want to develop your own cable. This section contains information for the design of custom cables. The PC-DIO-96 I/O connector is a 100-pin, Centronics-style, male, ribbon-cable header connector.
Chapter 2 Configuration and Installation This chapter describes the PC-DIO-96 jumper configurations, installing the PC-DIO-96 board in your computer, signal connections to the PC-DIO-96 board, and cabling instructions. Board Configuration The PC-DIO-96 contains one DIP switch and one jumper to configure the base I/O address and interrupts, respectively. The DIP switch and jumper are shown in the parts locator diagram in Figure 2-1.
Configuration and Installation Chapter 2 U26 W1 Figure 2-1. PC-DIO-96 Parts Locator Diagram Base I/O Address Settings The base I/O address for the PC-DIO-96 is determined by the switches at position U26 (see Figure 2-1). The switches are set at the factory for the I/O address hex 180. With this default setting, the PC-DIO-96 uses the I/O address space hex 180 through 19F. Note: Verify that this space is not already used by other equipment installed in your computer.
Chapter 2 Configuration and Installation onboard registers. On the U26 DIP switches, press the side marked OFF to select a binary value of 1 for the corresponding address bit. Press the other side of the switch to select a binary value of 0 for the corresponding address bit. Figure 2-2 shows two possible switch settings. The black side indicates the side of the switch that is pushed down. U26 O N O F F 1 A9 2 3 4 5 A8 A7 A6 A5 A.
Configuration and Installation Chapter 2 Table 2-2.
Chapter 2 Configuration and Installation Interrupt Level Selection There is one set of jumpers for interrupt selection on the PC-DIO-96 board. W1 is used for selecting the interrupt level. The location of this jumper is shown in Figure 2-1. The PC-DIO-96 board can connect to any one of six interrupt lines of the PC I/O Channel: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, or IRQ9. Select the interrupt line by setting a jumper on W1. The default interrupt line is IRQ5.
Configuration and Installation Chapter 2 4. Insert the PC-DIO-96 in an unused 8-bit, 16-bit, or 32-bit slot. It may be a tight fit, but do not force the board into place. 5. Screw the mounting bracket of the PC-DIO-96 to the back panel rail of the computer. 6. Check the installation. 7. Replace the cover to the computer.
Chapter 2 Configuration and Installation I/O Connector Pin Description Figure 2-4 shows the pin assignments for the PC-DIO-96 digital I/O connector.
Configuration and Installation Chapter 2 I/O Connector Signal Connection Descriptions Pin Signal Name Description 1, 3, 5, 7, 9, 11, 13, 15 APC<7..0> Bidirectional Data Lines for Port C of PPI A—APC7 is the MSB, APC0 the LSB. 17, 19, 21, 23, 25, 27, 29, 31 APB<7..0> Bidirectional Data Lines for Port B of PPI A—APB7 is the MSB, APB0 the LSB. 33, 35, 37, 39, 41, 43, 45, 47 APA<7..0> Bidirectional Data Lines for Port A of PPI A—APA7 is the MSB, APA0 the LSB. 2, 4, 6, 8, 10, 12, 14, 16 BPC<7..
Chapter 2 Warning: Configuration and Installation During programming, note that each time a port is configured, output ports A and C are reset to 0, and output port B is undefined. Table 2-3.
Configuration and Installation Chapter 2 APC7 1 2 BPC7 APC6 3 4 BPC6 APC5 5 6 BPC5 APC4 7 8 BPC4 APC3 9 10 BPC3 APC2 11 12 BPC2 APC1 13 14 BPC1 APC0 15 16 BPC0 APB7 17 18 BPB7 APB6 19 20 BPB6 APB5 21 22 BPB5 APB4 23 24 BPB4 APB3 25 26 BPB3 APB2 27 28 BPB2 APB1 29 30 BPB1 APB0 31 32 BPB0 APA7 33 34 BPA7 APA6 35 36 BPA6 APA5 37 38 BPA5 APA4 39 40 BPA4 APA3 41 42 BPA3 APA2 43 44 BPA2 APA1 45 46 BPA1 APA0 47 48 BPA0 +5 V 49 50 GND
Chapter 2 Configuration and Installation CPC7 1 2 DPC7 CPC6 3 4 DPC6 CPC5 5 6 DPC5 CPC4 7 8 DPC4 CPC3 9 10 DPC3 CPC2 11 12 DPC2 CPC1 13 14 DPC1 CPC0 15 16 DPC0 CPB7 17 18 DPB7 CPB6 19 20 DPB6 CPB5 21 22 DPB5 CPB4 23 24 DPB4 CPB3 25 26 DPB3 CPB2 27 28 DPB2 CPB1 29 30 DPB1 CPB0 31 32 DPB0 CPA7 33 34 DPA7 CPA6 35 36 DPA6 CPA5 37 38 DPA5 CPA4 39 40 DPA4 CPA3 41 42 DPA3 CPA2 43 44 DPA2 CPA1 45 46 DPA1 CPA0 47 48 DPA0 +5 V 49 50 GND
Configuration and Installation Chapter 2 Digital I/O Signal Connections Pins 1 through 48 and pins 51 through 98 of the I/O connector are digital I/O signal pins. The following specifications and ratings apply to the digital I/O lines. Absolute maximum voltage rating -0.5 to +5.5 V with respect to GND Digital input specifications (referenced to GND): Input logic high voltage Input logic low voltage Maximum input current (0 < Vin < 5 V) 2.2 V minimum -0.3 V minimum -1.0 µA minimum 5.3 V maximum 0.
Chapter 2 Configuration and Installation +5 V LED 41 PPI A Port A APA<3..0> 43 45 47 67 69 TTL Signal PPI C Port B CPB<7..4> 71 73 +5 V Switch 50, 100 GND I/O Connector PC-DIO-96 Board Figure 2-7. Digital I/O Connections In Figure 2-7, PPI A, port A is configured for digital output, and PPI C, port B is configured for digital input. Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2-7.
Configuration and Installation Chapter 2 Timing Specifications This section lists the timing specifications for handshaking with the PC-DIO-96. The handshaking lines STB* and IBF synchronize input transfers. The handshaking lines OBF* and ACK* synchronize output transfers. The following signals are used in the timing diagrams later in this chapter: Name Type Description STB* Input Strobe Input—A low signal on this handshaking line loads data into the input latch.
Chapter 2 Configuration and Installation Mode 1 Input Timing The following figure illustrates the timing specifications for an input transfer in mode 1. T1 T2 T4 STB* T7 IBF T6 INTR RD* T5 T3 DATA Name Description T1 T2 T3 T4 T5 T6 T7 STB* pulse width STB* = 0 to IBF = 1 Data before STB* = 1 STB* = 1 to INTR = 1 Data after STB* = 1 RD* = 0 to INTR = 0 RD* = 1 to IBF = 0 Minimum Maximum 100 – 20 – 50 – – – 150 – 150 – 200 150 All timing values are in nanoseconds.
Configuration and Installation Chapter 2 Mode 1 Output Timing The following figure illustrates the timing specifications for an output transfer in mode 1. T3 WR* T4 OBF* T1 T6 INTR T5 ACK* DATA T2 Name Description T1 T2 T3 T4 T5 T6 WR* = 0 to INTR = 0 WR* = 1 to output WR* = 1 to OBF* = 0 ACK* = 0 to OBF* = 1 ACK* pulse width ACK* = 1 to INTR = 1 Minimum Maximum – – – – 100 – 250 200 150 150 – 150 All timing values are in nanoseconds.
Chapter 2 Configuration and Installation Mode 2 Bidirectional Timing The following figure illustrates the timing specifications for bidirectional transfers in mode 2.
Chapter 3 Theory of Operation This chapter contains a functional overview of the PC-DIO-96 board and explains the operation of each functional unit making up the PC-DIO-96. The block diagram in Figure 3-1 illustrates the key functional components of the PC-DIO-96 board.
Theory of Operation Chapter 3 Data Transceivers The data transceivers control the sending and receiving of data to and from the PC I/O channel. PC I/O Channel Control Circuitry The base address used by the board is determined by an onboard switch setting. The address on the PC I/O channel bus is monitored by the address decoder, which is part of the I/O channel control circuitry.
Chapter 3 Theory of Operation handshaking circuitry; however, either of these two lines can be configured for input and used as external interrupts. An interrupt occurs on the low-to-high transition of the signal line. Refer to Chapter 4, Register-Level Programming, Appendix B, OKI 82C55A Data Sheet, or Appendix C, AMD 8253 Data Sheet, for more detailed information. Digital I/O Connector All digital I/O is transmitted through a standard, 100-pin, male connector.
Chapter 4 Register-Level Programming This chapter describes in detail the address and function of each of the PC-DIO-96 control and status registers. This chapter also includes important information about register-level programming the PC-DIO-96. The PC-DIO-96 is a parallel digital I/O board designed around four 82C55A integrated circuits and one 8253 integrated circuit. The 82C55A is a general-purpose peripheral interface containing 24 programmable I/O pins.
Register-Level Programming Chapter 4 Register Map The following table lists the address map for the PC-DIO-96. Table 4-1.
Chapter 4 Register-Level Programming Register Descriptions The register descriptions for the devices on the PC-DIO-96, including the 82C55A, the 8253, and each of the interrupt control registers, are given on the pages that follow. Register Description for the 82C55A Figure 4-1 shows the two control word formats used to completely program the 82C55A. The control word flag determines which control word format is being programmed.
Register-Level Programming Warning: Chapter 4 During programming, note that each time a port is configured, output ports A and C are reset to 0, and output port B is undefined. Table 4-2 shows the control words for setting or resetting each bit in port C. Notice that bit 7 of the control word is cleared when programming the set/reset option for the bits of port C. Table 4-2.
Chapter 4 Register-Level Programming Register Description for the Interrupt Control Registers There are two interrupt control registers on the PC-DIO-96. One of these registers has individual enable bits for the two interrupt lines from each of the 82C55A devices. The other register has a master interrupt enable bit and two bits for the timed interrupt circuitry. Of the latter two bits, one bit enables counter interrupts, while the other selects counter 0 or counter 1.
Register-Level Programming Chapter 4 Interrupt Control Register 1 D7 D6 D5 D4 D3 D2 D1 D0 DIRQ1 DIRQ0 CIRQ1 CIRQ0 BIRQ1 BIRQ0 AIRQ1 AIRQ0 Bit Name Description 7 DIRQ1 PPI D Interrupt Request for Port B—If this bit and the INTEN bit in Interrupt Control Register 2 are both set, PPI D sends an interrupt, INTRB, to the host computer. If this bit is cleared, PPI D does not send the interrupt INTRB to the host computer, regardless of the setting of INTEN.
Chapter 4 Register-Level Programming Bit Name Description (continued) 1 AIRQ1 PPI A Interrupt Request for Port B—If this bit and the INTEN bit in Interrupt Control Register 2 are both set, PPI A sends an interrupt, INTRB, to the host computer. If this bit is cleared, PPI A does not send the interrupt INTRB to the host computer, regardless of the setting of INTEN.
Register-Level Programming Chapter 4 Interrupt Control Register 2 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X INTEN CTRIRQ CTR1 Bit Name Description 7–3 X Don’t Care Bit. 2 INTEN Global Interrupt Enable Bit—If this bit is set, the PC-DIO-96 can interrupt the host computer. If this bit is cleared, the PC-DIO-96 interrupt line is put into high-impedance mode, so other devices can use the interrupt channel selected by jumper W1.
Chapter 4 Register-Level Programming Programming Considerations for the 82C55A Modes of Operation for the 82C55A The three basic modes of operation for the 82C55A are as follows: • Mode 0—Basic I/O • Mode 1—Strobed I/O • Mode 2—Bidirectional bus The 82C55A also has a single bit set/reset feature for port C, which is programmed by the 8-bit control word. For additional information, refer to Appendix B, OKI 82C55A Data Sheet.
Register-Level Programming Chapter 4 Mode 2 This mode can be used for communication over a bidirectional 8-bit bus. Handshaking signals are used in a manner similar to mode 1. Mode 2 is available for use in group A only (port A and the upper nibble of port C). Other features of this mode include the following: • One 8-bit bidirectional port (port A) and a 5-bit control/status port (port C). • Latched inputs and outputs. • Interrupt generation and enable/disable functions.
Chapter 4 Register-Level Programming Table 4-3.
Register-Level Programming porta portb portc cnfg = = = = Chapter 4 BASE_ADDRESS BASE_ADDRESS BASE_ADDRESS BASE_ADDRESS + + + + APORTAoffset; APORTBoffset; APORTCoffset; ACNFGoffset; /* EXAMPLE 1*/ outp(cnfg,0x80); outp(porta,0x12); outp(portb,0x34); outp(portc,0x56); /* /* /* /* Ports Write Write Write A, B, and C are data to port A. data to port B. data to port C. outputs. */ */ */ */ /* EXAMPLE 2*/ outp(cnfg,0x90); /* Port A is input; ports B and C are outputs. */ /* Write data to port B.
Chapter 4 Register-Level Programming The control word written to the CNFG Register to configure port B for input in mode 1 is shown as follows. Notice that port B does not have extra input or output lines from port C. D7 D6 D5 D4 D3 D2 D1 D0 1 X X X X 1 1 X During a mode 1 data read transfer, the status of the handshaking lines and interrupt signals can be obtained by reading port C. The port C status-word bit definitions for an input transfer are shown as follows.
Register-Level Programming Chapter 4 At the digital I/O connector, port C has the following pin assignments when in mode 1 input. Notice that the status of STBA* and the status of STBB* are not included in the port C status word. Group A Group B PC7 I/O PC6 I/O PC5 IBFA PC4 STBA* PC3 INTRA PC2 STBB* PC1 IBFB PC0 INTRB Mode 1 Input Programming Example The following example shows how to configure PPI A for various combinations of mode 1 input.
Chapter 4 Register-Level Programming Mode 1—Strobed Output The control word written to the CNFG Register to configure port A for output in mode 1 is shown as follows. Bits PC4 and PC5 of port C can be used as extra input or output lines. D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1/0 X X X Port C bits PC4 and PC5 1 = input 0 = output The control word written to the CNFG Register to configure port B for output in mode 1 is shown as follows.
Register-Level Programming Chapter 4 Bit Name Description (continued) 2 INTEB Interrupt Enable Bit for Port B—Setting this bit enables interrupts from port B of the 82C55A. This bit is controlled by setting/resetting PC2. 1 OBFB* Output Buffer for Port B—A low setting indicates that the CPU has written data to port B. 0 INTRB Interrupt Request Status for Port B—When INTEB and OBFB* are high, this bit is high, indicating that an interrupt request is pending for port B.
Chapter 4 Register-Level Programming outp(cnfg,0xA0); while (!(inp(portc) & 0x80)); /* Port A is an output in mode 1.*/ /* Wait until OBFA* is set, indicating that the data last written to port A has been read.*/ /* Write data to port A. */ outp(porta,0x12); /* EXAMPLE 2–port B output */ outp(cnfg,0x84); while (!(inp(portc) & 0x02)); /* Port B is an output in mode 1.*/ /* Wait until OBFB* is set, indicating that the data last written to port B has been read.*/ /* Write the data to port B.
Register-Level Programming Chapter 4 Port C status-word bit definitions for bidirectional data path (port A only): D7 D6 D5 D4 D3 D2 D1 D0 OBFA* INTE1 IBFA INTE2 INTRA I/O I/O I/O Bit Name Description 7 OBFA* Output Buffer for Port A—A low setting indicates that the CPU has written data to port A. 6 INTE1 Interrupt Enable Bit for Port A Output Interrupts—Setting this bit enables output interrupts from port A of the 82C55A. This bit is controlled by setting/resetting PC6.
Chapter 4 Register-Level Programming Mode 2 Programming Example The following example shows how to configure PPI A for mode 2 input and output and how to use the handshaking signals to control data flow. This code is strictly an example and is not intended to be used without modification in a practical situation.
Register-Level Programming Chapter 4 Main() { #define #define #define #define #define #define #define BASE_ADDRESS APORTAoffset APORTBoffset APORTCoffset ACNFGoffset IREG1offset IREG2offset 0x180 0x00 0x01 0x02 0x03 0x14 0x15 /* /* /* /* /* /* /* Board located at address 180 */ Offset for PPI A, port A */ Offset for PPI A, port B */ Offset for PPI A, port C */ Offset for PPI A, CNFG */ Offset for Interrupt Reg. 1 */ Offset for Interrupt Reg.
Chapter 4 outp(cnfg,0x84); outp(cnfg,0x05); outp(ireg1,0x02); outp(ireg2,0x04); Register-Level Programming /* Port B is an output in mode 1. */ /* Set PC2 to enable interrupts from 82C55A. */ /* Set AIRQ1 to enable PPI A, port B interrupts. */ /* Set INTEN bit. */ /* EXAMPLE 5–Set up interrupts for mode 2 output transfers. appropriate interrupt bits. */ outp(cnfg,0xC0); outp(cnfg,0x0D); outp(ireg1,0x01); outp(ireg2,0x04); /* Mode 2 output. */ /* Set PC6 to enable interrupts from 82C55A.
Register-Level Programming Chapter 4 Interrupt Programming Example for the 8253 An in-depth example of handling interrupts generated by the 8253 is presented as follows. The main program is presented in C, while sample interrupt routines are presented in assembly language.
Chapter 4 Register-Level Programming if (use_ctr1) { outp(ctr1, ((unsigned char) (ctr1_data & 0x00ff))); /* Send the least significant byte of the counter data for counter 1 */ outp(ctr1, ((unsigned char) ((ctr1_data & 0xff00) >> 8))); /* Send the most significant byte of the counter data for counter 1 */ } outp(ctr0, ((unsigned char) (ctr0_data & 0x00ff))); /* Send the least significant byte of the counter data for counter 0 */ outp(ctr0, ((unsigned char) ((ctr0_data & 0xff00) >> 8))); /* Send the most s
Register-Level Programming ; ; ; ; ; ; ; ; ; Chapter 4 on input, isr_block points to the data structure that will be used by the isr_handler function void isr_handler(void); the isr_handler() function will never be called from C.....
Chapter 4 Register-Level Programming mov mov mov mov ax,[bp+8] word ptr isrb_addr[0],ax ax,[bp+10] word ptr isrb_addr[2],ax ; ; ; ; Get ofs into Save address Get seg into Save address ax in variable ax in variable ; set interrupt vector--save the current vector before writing out new one mov cmp ja add jmp ax,[bp+6] al,7 short slave al,008h short setvec ; ; ; ; ; Get interrupt level Check to see if it belongs to master or slave interrupt chip Offset for master vector list Go set the vector add mo
Register-Level Programming Chapter 4 ; restore saved registers ii_exit: pop pop pop pop pop pop pop sti ret _install_isr ; ; ; ; ; ; es ds dx cx bx ax bp endp remove_isr bp reg ret addr ofs ret addr seg _remove_isr proc cli push push push push push push mov mov at [bp+0] at [bp+2] at [bp+4] far ax bx cx dx ds es ax,seg _DATA ds,ax ; see if our vector is installed--if not, do not remove the vector cmp jz mov mov int mov mov cmp jne cmp jne vect_num,0 ; See if vect_num was ever set short ri_exit ;
Chapter 4 Register-Level Programming mov in jmp or out jmp in jmp or out jmp mov mov lds int cx,int_mask al,maskm $+2 al,cl maskm,al $+2 al,masks $+2 al,ch masks,al $+2 al,vect_num ah,25h dx,int_addr 21h ; ; ; ; ; ; ; ; ; ; ; ; Get the old mask value Get current master mask Delay--wait for data transfer OR in old mask value Send out new setting Delay--wait for data transfer Get current slave mask Delay--wait for data transfer OR in old mask value Send out new setting Delay--wait for data transfer al ho
Register-Level Programming Chapter 4 ; acknowledge the interrupt ih_0: mov mov mov cmp je out jmp ax,seg _DATA ds,ax al,eoi slave_ack,0 short ih_1 acks,al $+2 ; ; ; ; ; out ackm,al ; Send master acknowledge Signify end of interrupt See if we need to acknowledge slave Jump if not Send slave acknowledge Delay--wait for data transfer ih_1: ; restore saved registers pop pop sti iret _isr_handler _TEXT ds ax endp ends end Interrupt Handling The INTEN bit of Interrupt Register 2 must be set to enab
Appendix A Specifications This appendix lists the specifications of the PC-DIO-96. These specifications are typical at 25° C, unless otherwise stated. The operating temperature range is 0° to 70° C. Digital I/O Number of channels ..................................................... 96 I/O Compatibility ............................................................... TTL Absolute max voltage rating ........................................-0.5 to +5.5 V with respect to GND Handshaking .......................
Specifications Appendix A Pins 1–48, 51–98...................................................... Level Output high voltage (I out = -2.5 mA) Output low voltage (I out = 2.5 mA) Output current (V OL = 0.5 V) Output current (V OH = 2.7 V) Min Max 3.7 V 5.0 V 0.0 V 0.4 V 4 mA — 4 mA — Environment Operating Temperature ................................................0° to 70° C Storage Temperature ....................................................-55° to 150° C Relative humidity ................
Appendix A Specifications Table A-1.
Appendix B OKI 82C55A Data Sheet* This appendix contains the manufacturer data sheet for the OKI 82C55A (OKI Semiconductor) CMOS programmable peripheral interface. This interface is used on the PC-DIO-96 board. * Copyright © OKI Semiconductor 1993. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor Data Book Microprocessor, Seventh Edition, March 1993.
OKI 82C55A Data Sheet PC-DIO-96 User Manual Appendix B B-2 © National Instruments Corporation
Appendix B © National Instruments Corporation OKI 82C55A Data Sheet B-3 PC-DIO-96 User Manual
OKI 82C55A Data Sheet PC-DIO-96 User Manual Appendix B B-4 © National Instruments Corporation
Appendix B © National Instruments Corporation OKI 82C55A Data Sheet B-5 PC-DIO-96 User Manual
OKI 82C55A Data Sheet PC-DIO-96 User Manual Appendix B B-6 © National Instruments Corporation
Appendix B © National Instruments Corporation OKI 82C55A Data Sheet B-7 PC-DIO-96 User Manual
OKI 82C55A Data Sheet PC-DIO-96 User Manual Appendix B B-8 © National Instruments Corporation
Appendix B © National Instruments Corporation OKI 82C55A Data Sheet B-9 PC-DIO-96 User Manual
OKI 82C55A Data Sheet PC-DIO-96 User Manual Appendix B B-10 © National Instruments Corporation
Appendix B © National Instruments Corporation OKI 82C55A Data Sheet B-11 PC-DIO-96 User Manual
OKI 82C55A Data Sheet PC-DIO-96 User Manual Appendix B B-12 © National Instruments Corporation
Appendix B © National Instruments Corporation OKI 82C55A Data Sheet B-13 PC-DIO-96 User Manual
OKI 82C55A Data Sheet PC-DIO-96 User Manual Appendix B B-14 © National Instruments Corporation
Appendix B © National Instruments Corporation OKI 82C55A Data Sheet B-15 PC-DIO-96 User Manual
OKI 82C55A Data Sheet PC-DIO-96 User Manual Appendix B B-16 © National Instruments Corporation
Appendix B © National Instruments Corporation OKI 82C55A Data Sheet B-17 PC-DIO-96 User Manual
.c1.Appendix C .c1.AMD 8253 Data Sheet* This appendix contains the manufacturer data sheet for the AMD 8253 integrated circuit (Advanced Micro Devices, Inc.). This circuit is used on the PC-DIO-96 board. * Copyright © Advanced Micro Devices, Inc. 1987. Reprinted with permission of copyright owner. All rights reserved. Advanced Micro Devices, Inc. 1987-1988 Data Book MOS Microprocessors and Peripherals.
AMD 8253 Data Sheet PC-DIO-96 User Manual Appendix C C-2 © National Instruments Corporation
Appendix C © National Instruments Corporation AMD 8253 Data Sheet C-3 PC-DIO-96 User Manual
AMD 8253 Data Sheet PC-DIO-96 User Manual Appendix C C-4 © National Instruments Corporation
Appendix C © National Instruments Corporation AMD 8253 Data Sheet C-5 PC-DIO-96 User Manual
AMD 8253 Data Sheet PC-DIO-96 User Manual Appendix C C-6 © National Instruments Corporation
Appendix C © National Instruments Corporation AMD 8253 Data Sheet C-7 PC-DIO-96 User Manual
AMD 8253 Data Sheet PC-DIO-96 User Manual Appendix C C-8 © National Instruments Corporation
Appendix C © National Instruments Corporation AMD 8253 Data Sheet C-9 PC-DIO-96 User Manual
AMD 8253 Data Sheet PC-DIO-96 User Manual Appendix C C-10 © National Instruments Corporation
Appendix C © National Instruments Corporation AMD 8253 Data Sheet C-11 PC-DIO-96 User Manual
AMD 8253 Data Sheet PC-DIO-96 User Manual Appendix C C-12 © National Instruments Corporation
Appendix C © National Instruments Corporation AMD 8253 Data Sheet C-13 PC-DIO-96 User Manual
AMD 8253 Data Sheet PC-DIO-96 User Manual Appendix C C-14 © National Instruments Corporation
Appendix D Customer Communication ___________________________________________________ For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation. Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster. National Instruments provides comprehensive technical assistance around the world.
Technical Support Form ___________________________________________________ Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
PC-DIO-96 Hardware and Software Configuration Form ___________________________________________________ Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.
Documentation Comment Form ___________________________________________________ National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: PC-DIO-96 User Manual Edition Date: September 1995 Part Number: 320289B-01 Please comment on the completeness, clarity, and organization of the manual. If you find errors in the manual, please record the page numbers and describe the errors.
Glossary ___________________________________________________ ° Ω % A AMD AWG BCD C DMA EISA hex Hz in.
