Network Card User Manual
Table Of Contents
- PC-DIO-24 User Manual
- Contents
- About This Manual
- Chapter 1 Introduction
- Chapter 2 Configuration and Installation
- Chapter 3 Theory of Operation
- Chapter 4 Register-Level Programming
- Appendix A Specifications
- Appendix B I/O Connector
- Appendix C OKI 82C55A Data Sheet*
- Appendix D Customer Communication
- Glossary
- Index
- Figures
- Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware
- Figure 2-1. PC-DIO-24 Parts Locator Diagram
- Figure 2-2. Example Base I/O Address Switch Settings
- Figure 2-3. Jumper Settings–PC6, PC4, PC2, and N/C
- Figure 2-4. Interrupt Jumper Setting for IRQ5 (Factory Setting)
- Figure 2-5. Digital I/O Connector Pin Assignments
- Figure 3-1. PC-DIO-24 Block Diagram
- Figure 4-1. Control-Word Formats
- Figure B-1. PC-DIO-24 I/O Connector
- Tables
- Table 2-1. PC-DIO-24 Factory-Set Jumper and Switch Settings
- Table 2-2. Port C Signal Assignments
- Table 4-1. PC-DIO-24 Address Map
- Table 4-2. Port C Set/Reset Control Words
- Table 4-3. Mode 0 I/O Configurations
- Table 4-4. Interrupt Enable Signals for All Mode Combinations
- Table A-1. Maximum Average Transfer Rates for the PC-DIO-24
Register-Level Programming Chapter 4
PC-DIO-24 User Manual 4-8 © National Instruments Corporation
During a mode 1 data read transfer, the status of the handshaking lines and interrupt signals can
be obtained by reading port C. The port C status-word bit definitions for an input transfer are
shown as follows.
The following are the port C status-word bit definitions for input (port A and port B).
76543210
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
Bit Name Description
7–6 I/O Input/Output—Extra I/O status lines when port A is in mode 1
input.
5 IBFA Input Buffer Full for Port A—High indicates that data has been
loaded into the input latch for port A.
4 INTEA Interrupt Enable Bit for Port A—Enables interrupts from the
82C55A for port A. Controlled by bit set/reset of PC4.
3 INTRA Interrupt Request Status for Port A—When INTEA is high and
IBFA is high, this bit is high, indicating that an interrupt request is
asserted.
2 INTEB Interrupt Enable Bit for Port B—Enables interrupts from the
82C55A for port B. Controlled by bit set/reset of PC2.
1 IBFB Input Buffer Full for Port B—High indicates that data has been
loaded into the input latch for port B.
0 INTRB Interrupt Request Status for Port B—When INTEB is high and
IBFB is high, this bit is high, indicating that an interrupt request is
asserted.
At the digital I/O connector, port C has the following pin assignments when in mode 1 input.
Notice that the status of STBA* and STBB* are not included in the port C status word.
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
I/O
I/O
IBFA
STBA*
INTRA
STBB*
IBFB
INTRB
Group A
Group B