DAQ NI PCI-6110/6111 User Manual Mulitfunction I/O Devices for PCI Bus Computers NI PCI-6110/6111 User Manual July 2003 Edition Part Number 321759E-01
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Important Information Warranty The NI PCI-6110 and the NI PCI-6111 are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
Compliance FCC/Canada Radio Frequency Interference Compliance Determining FCC Class The Federal Communications Commission (FCC) has rules to protect wireless communications from interference. The FCC places digital electronics into two classes. These classes are known as Class A (for use in industrial-commercial locations only) or Class B (for use in residential or commercial locations). All National Instruments (NI) products are FCC Class A products.
Contents About This Manual Conventions ...................................................................................................................ix National Instruments Documentation ............................................................................x Related Documentation..................................................................................................xi Chapter 1 Introduction About the NI PCI-6110/6111......................................................................
Contents Chapter 4 Connecting Signals I/O Connector ................................................................................................................ 4-1 I/O Connector Signal Descriptions ................................................................. 4-3 Connecting Analog Input Signals.................................................................................. 4-8 Types of Signal Sources ................................................................................................
Contents GPCTR1_OUT Signal ......................................................................4-35 GPCTR1_UP_DOWN Signal ...........................................................4-35 FREQ_OUT Signal ...........................................................................4-37 Field Wiring Considerations ..........................................................................................4-37 Chapter 5 Calibration Loading Calibration Constants ...................................................
About This Manual This manual describes the electrical and mechanical aspects of the National Instruments PCI-6110/6111 data acquisition (DAQ) device and contains information concerning its operation and programming. The device is a high-performance multifunction analog, digital, and timing I/O device for PCI bus computers. Supported functions include analog input (AI), analog output (AO), digital I/O (DIO), and timing I/O (TIO).
About This Manual NI-DAQ NI-DAQ refers to the NI-DAQ driver software for Macintosh or PC compatible computers unless otherwise noted. NI PCI-6110/6111 This phrase refers to either the NI PCI-6110 or NI PCI-6111 device. PCI PCI stands for Peripheral Component Interconnect. PCI is a high-performance expansion bus architecture originally developed by Intel to replace ISA and EISA.
About This Manual Related Documentation The following documents contain information that you might find helpful: • The NI Developer Zone tutorial, Field Wiring and Noise Considerations for Analog Signals, located at ni.com/zone • PCI Local Bus Specification Revision 2.2 • DAQ Quick Start Guide, located at ni.com/manuals • DAQ-STC Technical Reference Manual, located at ni.com/manuals • NI-DAQ User Manual for PC Compatibles, located at ni.
1 Introduction This chapter describes the NI PCI-6110/6111, lists what you need to get started, describes the optional software and optional equipment, and explains how to unpack the device. About the NI PCI-6110/6111 Thank you for buying an NI PCI-6110/6111. The NI PCI-6110/6111 is a Plug and Play, multifunction analog, digital, and timing I/O device for PCI bus computers.
Chapter 1 Introduction What You Need to Get Started To set up and use the NI PCI-6110/6111, you will need the following items: ❑ NI PCI-6110/6111 ❑ NI PCI-6110/6111 User Manual ❑ NI-DAQ ❑ The computer ❑ (Optional) One of the following software packages and documentation: – LabVIEW (Windows or Mac OS) – Measurement Studio (Windows) – VI Logger (Windows) Software Programming Choices When programming the National Instruments DAQ hardware, you can use NI application development environment (ADE) softwa
Chapter 1 Introduction LabVIEW, Measurement Studio, or VI Logger Conventional Programming Environment NI-DAQ DAQ Hardware Personal Computer or Workstation Figure 1-1. The Relationship Between the Programming Environment, NI-DAQ, and the Hardware To download a free copy of the most recent version of NI-DAQ, click Download Software at ni.com. National Instruments ADE Software LabVIEW features interactive graphics, a state-of-the-art interface, and a powerful graphical programming language.
Chapter 1 Introduction developers, Measurement Studio offers a set of Visual C++ classes and tools to integrate those classes into Visual C++ applications. The libraries, ActiveX controls, and classes are available with Measurement Studio and NI-DAQ. VI Logger is an easy-to-use yet flexible tool specifically designed for data logging applications. Using dialog windows, you can configure data logging tasks to easily acquire, log, view, and share your data.
Chapter 1 Introduction The following list gives recommended part numbers for connectors that mate to the I/O connector on the NI PCI-6110/6111: • Honda 68-position, solder cup, female connector • Honda backshell Unpacking The NI PCI-6110/6111 is shipped in an antistatic package to prevent electrostatic damage to the device. Electrostatic discharge (ESD) can damage several components on the device. Caution Never touch the exposed pins of connectors.
Chapter 1 Introduction Do not operate the product in an explosive atmosphere or where there may be flammable gases or fumes. Operate the product only at or below the pollution degree stated in the Appendix A, Specifications. Pollution is foreign matter in a solid, liquid, or gaseous state that can reduce dielectric strength or surface resistivity. The following is a description of pollution degrees: • Pollution Degree 1 means no pollution or only dry, nonconductive pollution occurs.
Chapter 1 Introduction Examples of Installation Category II are measurements on household appliances, portable tools, and similar equipment. • Installation Category III is for measurements performed in the building installation. This category is a distribution level referring to hardwired equipment that does not rely on standard building insulation. Examples of Installation Category III include measurements on distribution circuits and circuit breakers.
2 Installing and Configuring the NI PCI-6110/6111 This chapter explains how to install and configure the NI PCI-6110/6111. Installing the Software Note It is important to install the software before installing the NI PCI-6110/6111 to ensure that the device is properly detected. 1. Install the ADE, such as LabVIEW or Measurement Studio, according to the instructions on the CD and the release notes. 2.
Chapter 2 Installing and Configuring the NI PCI-6110/6111 6. If required, screw the mounting bracket of the NI PCI-6110/6111 to the back panel rail of the computer. 7. Visually verify the installation by making sure the device is not touching other devices or components and is fully inserted into the slot. 8. Replace the cover. 9. Plug in and power on the computer. The NI PCI-6110/6111 is now installed. You are now ready to configure the device.
3 Hardware Overview This chapter presents an overview of the hardware functions on the NI PCI-6110/6111. Figures 3-1 and 3-2 show block diagrams for the NI PCI-6110 and the NI PCI-6111, respectively.
Hardware Overview CH0+ CH0- + AI CH0 Mux CH0 Amplifier – CH1+ CH1- CH0 12-Bit ADC 12 CH0 Latch + AI CH1 Mux CH1 Amplifier – CH1 12-Bit ADC 12 CH1 Latch Data (32) Generic Bus Interface PCI Mini Bus MITE Interface Address/Data Data (16) AI Control EEPROM 2 Trigger Level DACs Trigger Control ADC FIFO Calibration Mux I/O Connector Data (16) IRQ DMA Analog Trigger Circuitry Analog Input Timing/Control DMA/IRQ Counter/ Timing I/O DAQ - STC Bus Interface Digital I/O Analog Output T
Chapter 3 Hardware Overview input of the PGIA. For more information about DIFF input mode, refer to the Connecting Analog Input Signals section of Chapter 4, Connecting Signals, which contains diagrams showing the signal paths for DIFF input mode. Input Polarity and Input Range The NI PCI-6110/6111 has bipolar inputs only. Bipolar input means that the input voltage range is between –Vref /2 and +Vref /2. These devices have a bipolar input range of 20 V (±10 V).
Chapter 3 Hardware Overview Considerations for Selecting Input Ranges The range you select depends on the expected range of the incoming signal. A large input range can accommodate a large signal variation but reduces the voltage resolution. Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range. For best results, match the input range as closely as possible to the expected range of the input signal.
Chapter 3 Hardware Overview ADC Analog Input CH0 + Analog Input CH1 + PGIA – ADC PGIA – ADC Analog Input CH2 + Analog Input CH3 + Mux PGIA Analog Trigger Circuit DAQ-STC – ADC PGIA – PFI0/TRIG1 Figure 3-3. Analog Trigger Block Diagram for the NI PCI-6110 Analog Input CH0 Analog Input CH1 ADC + PGIA – Mux ADC + Analog Trigger Circuit DAQ-STC PGIA – PFI0/TRIG1 Figure 3-4.
Chapter 3 Hardware Overview In below-low-level analog triggering mode, the trigger is generated when the signal value is less than lowValue, as shown in Figure 3-5. HighValue is unused. lowValue Trigger Figure 3-5. Below-Low-Level Analog Triggering Mode In above-high-level analog triggering mode, the trigger is generated when the signal value is greater than highValue, as shown in Figure 3-6. LowValue is unused. highValue Trigger Figure 3-6.
Chapter 3 Hardware Overview highValue lowValue Trigger Figure 3-7. Inside-Region Analog Triggering Mode In high-hysteresis analog triggering mode, the trigger is generated when the signal value is greater than highValue, with the hysteresis specified by lowValue, as shown in Figure 3-8. highValue lowValue Trigger Figure 3-8.
Chapter 3 Hardware Overview The analog trigger circuit generates an internal digital trigger based on the AI signal and user-defined trigger levels. This digital trigger can be used by any DAQ-STC timing section, including the AI, AO, and general-purpose counter/timer sections. For example, the AI section can be configured to acquire n scans after the AI signal crosses a specific threshold.
Chapter 3 Hardware Overview RTSI Trigger <0..6> STARTSCAN PFI<0..9> Scan Interval Counter TC GPCTR0_OUT Figure 3-10. STARTSCAN Signal Routing This figure shows that STARTSCAN can be generated from a number of sources, including the external signals RTSI<0..6> and PFI<0..9> and the internal signals Sample Interval Counter TC and GPCTR0_OUT.
Chapter 3 Hardware Overview Programmable Function Inputs The 10 PFIs are connected to the signal routing multiplexer for each timing signal, and software can select a PFI as the external source for a given timing signal. Any PFI can be used as an input by any timing signal, and multiple timing signals can simultaneously use the same PFI. This flexible routing scheme reduces the need to change physical connections to the I/O connector for different applications.
Chapter 3 Hardware Overview RTSI Triggers The seven RTSI trigger lines on the RTSI bus provide a flexible interconnection scheme for the device sharing the RTSI bus. These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals. This signal connection scheme is shown in Figure 3-11.
4 Connecting Signals This chapter describes how to make input and output signal connections to the NI PCI-6110/6111 through the device I/O connector. Table 4-1 shows the cables that can be used with the I/O connectors to connect to different accessories. Table 4-1.
Chapter 4 Connecting Signals ACH0– ACH1+ 34 68 ACH1GND 32 66 31 65 ACH2–1 ACH3+1 ACH3GND1 NC NC NC NC NC NC DAC0OUT DAC1OUT NC 33 67 30 64 29 63 28 62 27 61 26 60 25 59 24 58 ACH0+ ACH0GND ACH1– ACH2+1 ACH2GND1 ACH3–1 NC NC NC NC NC 23 57 22 56 21 55 NC NC AOGND 20 54 AOGND DIO4 DGND DIO1 19 53 18 52 17 51 DGND DIO0 DIO6 DGND 16 50 15 49 14 48 DGND DIO2 +5 V DGND DGND PFI0/TRIG1 PFI1/TRIG2 DGND +5 V DGND PFI5/UPDATE* PFI6/WFTRIG DGND PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 13 47 12 46 11 4
Chapter 4 DIO0 25 50 DGND AOGND 24 49 23 48 NC DAC1OUT DAC0OUT 22 47 21 46 20 45 19 44 NC NC NC Connecting Signals FREQ_OUT GPCTR0_OUT PFI9/GPCTR0_GATE PFI8/GPCTR0_SOURCE PFI7/STARTSCAN PFI6/WFTRIG 18 43 PFI5/UPDATE* GPCTR1_OUT 17 42 PFI4/GPCTR1_GATE NC NC 16 41 15 40 PFI3/GPCTR1_SOURCE PFI2/CONVERT* NC NC NC PFI0/TRIG1 ACH3–1 14 39 13 38 PFI1/TRIG2 PFI0/TRIG1 12 37 11 36 EXTSTROBE* 10 35 9 34 8 33 ACH3+1 ACH2–1 ACH2+1 ACH1– ACH1+ ACH0– ACH0+ ACH<0..3>GND ACH<0..
Chapter 4 Connecting Signals Table 4-2. Signal Descriptions for I/O Connector Pins (Continued) Signal Name Reference Direction Description ACH<0..3>– ACH<0..3>GND Input Analog Input Channels 0 through 3 (–)—These pins are routed to the (–) terminal of the respective channel amplifier. ACH<2..3>– signals are no connects on the NI PCI-6111. DAC0OUT AOGND Output Analog Channel 0 Output—This pin supplies the voltage output of AO channel 0.
Chapter 4 Connecting Signals Table 4-2. Signal Descriptions for I/O Connector Pins (Continued) Signal Name PFI2/CONVERT* PFI3/GPCTR1_SOURCE PFI4/GPCTR1_GATE Reference DGND DGND DGND Direction Description Input PFI2/Convert—As an input, this is a PFI. Output As an output, this is the CONVERT* signal. A high-to-low edge on CONVERT* indicates that an A/D conversion is occurring. Input PFI3/Counter 1 Source—As an input, this is a PFI. Output As an output, this is the GPCTR1_SOURCE signal.
Chapter 4 Connecting Signals Table 4-2. Signal Descriptions for I/O Connector Pins (Continued) Signal Name Reference Direction Description GPCTR0_OUT DGND Output Counter 0 Output—This output is from the general-purpose counter 0 output. FREQ_OUT DGND Output Frequency Output—This output is from the frequency generator output. Table 4-3.
Chapter 4 Connecting Signals Table 4-3. I/O Signal Summary for the NI PCI-6110/6111 (Continued) Signal Name Signal Impedance Type and Input/ Direction Output Protection (Volts) On/Off Source (mA at V) Rise Sink Time (mA at V) (ns) Bias PFI3/GPCTR1_SOURCE DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu GPCTR1_OUT DO — 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI5/UPDATE* DIO — Vcc +0.5 3.
Chapter 4 Connecting Signals Connecting Analog Input Signals The NI PCI-6110/6111 channels are configured as pseudodifferential inputs. The input signal of each channel, ACH<0..3>+, is tied to the positive input of the PGIA, and each reference signal ACH<0..3>–, is tied to the negative input of the PGIA. The inputs are differential only in the sense that ground loops are broken. The reference signal, ACH<0..
Chapter 4 Connecting Signals The PGIA applies gain and common-mode voltage rejection and presents high input impedance to the AI signals connected to the NI PCI-6110/6111. Signals are routed to the positive and negative inputs of the PGIA. The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier. The amplifier output voltage is referenced to the device ground.
Chapter 4 Connecting Signals Differential Measurements The following sections discuss the use of differential (DIFF) measurements and considerations for measuring both floating and ground-referenced signal sources. Table 4-4 summarizes the recommended DIFF signal connections and includes input examples for both types of signal sources. Table 4-4.
Chapter 4 Connecting Signals Differential Connections for Ground-Referenced Signal Sources Figure 4-4 shows how to connect a ground-referenced signal source to a channel on the NI PCI-6110/6111. ACH0+ GroundReferenced Signal Source CommonMode Noise and Ground Potential + Instrumentation Amplifier + Vs PGIA – ACH0– – + + Measured Voltage Vm – Vcm – ACH0GND I/O Connector ACH0 Connections Shown Figure 4-4.
Chapter 4 Connecting Signals Differential Connections for Nonreferenced or Floating Signal Sources Figure 4-5 shows how to connect a floating signal source to a channel on the NI PCI-6110/6111. ACH0+ Floating Signal Source + + Vs 100pf Instrumentation Amplifier 1MΩ – PGIA + ACH0– – Bias Current Return Paths Bias Resistor (see text) 10nf Vm – Measured Voltage ACH0GND I/O Connector ACH0 Connections Shown Figure 4-5.
Chapter 4 Connecting Signals Like any amplifier, the common-mode rejection ratio (CMRR) of the PGIA is limited at high frequency. This limitation has been compensated for in the design of the NI PCI-6110/6111 by using a common-mode choke on each channel. The purpose of the 10 nF capacitance on the ACH<0..3>– connection is to provide an impedance for this choke to work against at high frequency, thus improving the high-frequency CMRR.
Chapter 4 Connecting Signals Analog Output Signal Connections The AO signals are DAC0OUT, DAC1OUT, and AOGND. DAC0OUT is the voltage output signal for AO channel 0, DAC1OUT is the voltage output signal for AO channel 1, and AOGND is the ground reference signal for the AO channels. Figure 4-6 shows how to make AO connections to the NI PCI-6110/6111. DAC0OUT Channel 0 + Load VOUT 0 – AOGND – Load VOUT 1 DAC1OUT + Channel 1 Analog Output Channels NI PCI-6110/6111 Figure 4-6.
Chapter 4 Connecting Signals Digital I/O Signal Connections The DIO signals are DIO<0..7> and DGND. DIO<0..7> are the signals making up the DIO port, and DGND is the ground reference signal for the DIO port. You can program all lines individually to be inputs or outputs. Caution Exceeding the maximum input voltage ratings, which are listed in Table 4-3, can damage the NI PCI-6110/6111 and the computer. NI is not liable for any damage resulting from such signal connections.
Chapter 4 Connecting Signals Figure 4-7 shows DIO<0..3> configured for digital input and DIO<4..7> configured for digital output. Digital input applications include receiving TTL signals and sensing external device states, such as the switch state shown in Figure 4-7. Digital output applications include sending TTL signals and driving external devices, such as the LED shown in Figure 4-7.
Chapter 4 Connecting Signals All digital timing connections are referenced to DGND. Figure 4-8 illustrates how to connect an external TRIG1 source and an external CONVERT* source to two NI PCI-6110/6111 PFI pins. PFI0/TRIG1 PFI7/STARTSCAN TRIG1 Source STARTSCAN Source DGND I/O Connector NI PCI-6110/6111 Figure 4-8. Timing I/O Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins.
Chapter 4 Connecting Signals In edge-detection mode, the minimum pulse width required is 10 ns. This setting applies for both rising-edge and falling-edge polarity settings. Edge-detect mode does not have a maximum pulse-width requirement. In level-detection mode, the PFIs themselves do not impose a minimum or maximum pulse-width requirement, but the particular timing signal being controlled can impose limits. These requirements are listed later in this chapter.
Chapter 4 Connecting Signals TRIG1 n/a TRIG2 STARTSCAN CONVERT* Scan Counter 3 2 1 0 2 2 2 1 0 Figure 4-10. Typical Pretriggered Acquisition TRIG1 Signal Any PFI pin can receive as an input the TRIG1 signal, which is available as an output on the PFI0/TRIG1 pin. Refer to Figures 4-9 and 4-10 for the relationship of TRIG1 to the DAQ sequence. As an input, the TRIG1 signal is configured in the edge-detection mode.
Chapter 4 Connecting Signals Figures 4-11 and 4-12 show the timing requirements for TRIG1. tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 4-11. TRIG1 Input Signal Timing tw tw = 25 to 50 ns Figure 4-12. TRIG1 Output Signal Timing The device also uses TRIG1 to initiate pretriggered DAQ operations. In most pretriggered applications, TRIG1 is generated by a software trigger.
Chapter 4 Connecting Signals the selected edge of TRIG2 is received, the device acquires a fixed number of scans and the acquisition stops. This mode acquires data both before and after receiving TRIG2. As an output, TRIG2 reflects the posttrigger in a pretriggered acquisition sequence even if another PFI is externally triggering the acquisition. TRIG2 is not used in posttriggered data acquisition. The output is an active high pulse with a pulse width of 25 to 50 ns.
Chapter 4 Connecting Signals STARTSCAN Signal Any PFI pin can receive as an input the STARTSCAN signal, which is available as an output on the PFI7/STARTSCAN pin. Refer to Figures 4-9 and 4-10 for the relationship of STARTSCAN to the DAQ sequence. As an input, STARTSCAN is configured in the edge-detection mode. You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge. The selected edge of STARTSCAN initiates a scan.
Chapter 4 Connecting Signals tw tw = 25 to 50 ns a. Star of Scan Start Pulse CONVERT* STARTSCAN toff = 10 ns minimum toff b. Scan in Progress, Two Conversions per Scan Figure 4-16. STARTSCAN Output Signal Timing The CONVERT* pulses are masked off until the device generates the STARTSCAN signal. If you are using internally generated conversions, the first CONVERT* appears when SI2 reaches zero. If you select an external CONVERT*, the first external pulse after STARTSCAN generates a conversion.
Chapter 4 Connecting Signals If you are performing an internally timed acquisition, NI-DAQ generates three extra points to clock the data for you. However, if you perform an externally clocked acquisition, NI-DAQ does not know when the last point is taken, so you must provide the three extra pulses. CONVERT* Signal Any PFI pin can receive as an input the CONVERT* signal, which is available as an output on the PFI2/CONVERT* pin.
Chapter 4 Connecting Signals tw tw = 50 to 100 ns Figure 4-18. CONVERT* Output Signal Timing The ADC switches to hold mode within 20 ns of the selected edge. This hold-mode delay time is a function of temperature and does not vary from one conversion to the next. The SI2 on the NI PCI-6110/6111 normally generates CONVERT* unless you select some external source. The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished.
Chapter 4 Connecting Signals SISOURCE Signal Any PFI pin can receive as an input the SISOURCE signal, which is not available as an output on the I/O connector. The SI2 uses SISOURCE as a clock to time the generation of the STARTSCAN signal. You must configure the PFI pin you select as the source for SISOURCE in the level-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low.
Chapter 4 Connecting Signals Figure 4-20 shows the timing for SCANCLK. CONVERT* td SCANCLK tw td = 50 to 100 ns tw = 450 ns Figure 4-20. SCANCLK Signal Timing EXTSTROBE* Signal EXTSTROBE* is an output-only signal that generates either a single pulse or a sequence of eight pulses in the hardware-strobe mode. An external device can use this signal to latch signals or to trigger events. In the single-pulse mode, software controls the level of EXTSTROBE*. A 10 µs and a 1.
Chapter 4 Connecting Signals WFTRIG Signal Any PFI pin can externally input the WFTRIG signal, which is available as an output on the PFI6/WFTRIG pin. As an input, WFTRIG is configured in the edge-detection mode. You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge. The selected edge of WFTRIG starts the waveform generation for the DACs. The update interval counter (UI) is started if you select internally generated UPDATE*.
Chapter 4 Connecting Signals UPDATE* Signal Any PFI pin can externally input the UPDATE* signal, which is available as an output on the PFI5/UPDATE* pin. As an input, UPDATE* is configured in the edge-detection mode. You can select any PFI pin as the source for UPDATE* and configure the polarity selection for either rising or falling edge. The selected edge of UPDATE* updates the outputs of the DACs. In order to use UPDATE*, you must set the DACs to posted-update mode.
Chapter 4 Connecting Signals The NI PCI-6110/6111UI normally generates UPDATE* unless you select some external source. The WFTRIG signal starts the UI, and the UI can be stopped by software or the internal Buffer Counter. D/A conversions generated by either an internal or external UPDATE* signal do not occur when gated by the software command register gate. UISOURCE Signal Any PFI pin can externally input the UISOURCE signal, which is not available as an output on the I/O connector.
Chapter 4 Connecting Signals GPCTR0_SOURCE Signal Any PFI pin can externally input the GPCTR0_SOURCE signal, which is available as an output on the PFI8/GPCTR0_SOURCE pin. As an input, GPCTR0_SOURCE is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR0_SOURCE and configure the polarity selection for either rising or falling edge.
Chapter 4 Connecting Signals As an output, GPCTR0_GATE reflects the actual gate signal connected to general-purpose counter 0, even if the gate is being externally generated by another PFI. This output is set to high-impedance at startup. Figure 4-28 shows the timing requirements for the GPCTR0_GATE signal. tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 4-28. GPCTR0_GATE Signal Timing GPCTR0_OUT Signal This signal is available only as an output on the GPCTR0_OUT pin.
Chapter 4 Connecting Signals GPCTR0_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I/O connector. The general-purpose counter 0 counts down when this pin is at a logic low and counts up when it is at a logic high. You can disable this input so that software controls the up-down functionality and leaves the DIO6 pin free for general use.
Chapter 4 Connecting Signals GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal, which is available as an output on the PFI4/GPCTR1_GATE pin. As an input, GPCTR1_GATE is configured in edge-detection mode. You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge.
Chapter 4 Connecting Signals GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin. The GPCTR1_OUT signal monitors the TC of general-purpose counter 1. You have two software-selectable output options—pulse on TC and toggle output polarity on TC. The output polarity is software-selectable for both options. This output is set to high-impedance at startup. Figure 4-32 shows the timing requirements for GPCTR1_OUT.
Chapter 4 Connecting Signals tsc SOURCE tsp VIH VIL tgsu GATE tsp tgh VIH VIL tgw tout OUT VOH VOL Source Clock Period Source Pulse Width Gate Setup Time Gate Hold Time Gate Pulse Width Output Delay Time tsc tsp tgsu tgh tgw tout 50 ns minimum 23 ns minimum 10 ns minimum 0 ns minimum 10 ns minimum 80 ns maximum Figure 4-33. GPCTR Timing Summary The GATE and OUT signal transitions shown in Figure 4-33 are referenced to the rising edge of the SOURCE signal.
Chapter 4 Connecting Signals The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the NI PCI-6110/6111. Figure 4-33 shows the OUT signal referenced to the rising edge of a source signal. Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal. FREQ_OUT Signal This signal is available only as an output on the FREQ_OUT pin.
Chapter 4 Connecting Signals separate them by a reasonable distance if they run in parallel, or run the lines at right angles to each other. • Do not run signal lines through conduits that also contain power lines. • Protect signal lines from magnetic fields caused by electric motors, welding equipment, breakers, or transformers by running them through special metal conduits.
5 Calibration This chapter discusses the calibration procedures for the NI PCI-6110/6111. NI-DAQ includes calibration functions for performing all of the steps in the calibration process. Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments. On the NI PCI-6110/6111, these adjustments take the form of writing values to onboard calibration DACs (CalDACs). Most applications require some form of device calibration.
Chapter 5 Calibration vary with time and temperature. It is better to self-calibrate when the device is installed in the environment in which it is used. Self-Calibration The NI PCI-6110/6111 can measure and correct for almost all of its calibration-related errors without any external signal connections. NI-DAQ provides a self-calibration method. This self-calibration process, which generally takes less than a minute, is the preferred method of assuring accuracy in your application.
A Specifications This appendix lists the specifications of the NI PCI-6110/6111. These specifications are typical at 25 °C unless otherwise noted. Analog Input Input Characteristics Number of channels NI PCI-6110.................................... 4 pseudodifferential NI PCI-6111.................................... 2 pseudodifferential Type of ADC Resolution ....................................... 12 bits, 1 in 4,096 Pipeline ........................................... 3 Sampling rate Maximum...........
Appendix A Specifications FIFO buffer size......................................8,192 samples Data transfers ..........................................DMA, interrupts, programmed I/O DMA modes ...........................................Scatter-gather (single transfer, demand transfer) Accuracy Information Table A-1.
Appendix A Specifications Amplifier Characteristics Input impedance ACH<0..3>+ to ACH<0..3>– Normal powered on ................. 1 MΩ in parallel with 100 pF Powered off.............................. 1 MΩ minimum Overload .................................. 1 MΩ Impedance to ground ACH<0..3>– to ground............ 10 nF Input bias current ................................... ±300 pA Input offset current................................. ±200 pA CMRR ....................................................
Appendix A Specifications Table A-2. Analog Input Characteristics Input Range Bandwidth1 (MHz) SFDR Typ2 (dB) SFDR Max (dB) CMRR3 (dB) System Noise4 (LSBrms) ±42 V 5.5 78 70 34 0.5 ±20 V 4.4 78 70 40 0.5 ±10 V 7.2 81 75 46 0.5 ±5 V 4.8 81 75 52 0.5 ±2 V 4.8 85 75 60 0.5 ±1 V 4.4 85 75 66 0.5 ±500 mV 4.4 85 75 70 0.6 ±200 mV 4.1 81 70 72 1.0 1 –3 dB frequency for input amplitude at 96% of the input range (–0.
Appendix A Specifications Analog Output Output Characteristics Number of channels ............................... 2 voltage Resolution .............................................. 16 bits, 1 in 65,536 Max update rate 1 channel ......................................... 4 MS/s, system dependent 2 channel ......................................... 2.5 MS/s, system dependent FIFO buffer size ..................................... 2,048 samples Data transfers .........................................
Appendix A Specifications Current drive...........................................±5 mA min Output stability .......................................Any passive load Protection................................................Short-circuit to ground Power-on output voltage.........................0, ±400 mV (before software loads calibration values) Dynamic Characteristics Settling time and slew rate Settling Time for Full-Scale Step Slew Rate 300 ns to ±0.01% 300 V/µs Noise ............................
Appendix A Specifications Digital logic levels Level Min Max Input low voltage 0.0 V 0.8 V Input high voltage 2.0 V 5.0 V Input low current (Vin = 0 V) — –320 µA Input high current (Vin = 5 V) — 10 µA Output low voltage (IOL = 24 mA) — 0.4 V Output high voltage (IOH = 13 mA) 4.35 V — Power-on state........................................ Input (high-impedance) Data transfers .........................................
Appendix A Specifications Min source pulse duration .....................10 ns, edge-detect mode Min gate pulse duration .........................10 ns, edge-detect mode Data transfers ..........................................DMA, interrupts, programmed I/O DMA modes ...........................................Scatter-gather (single transfer, demand transfer) Frequency Scaler Number of channels................................1 Resolution ...............................................
Appendix A Specifications Source..................................................... All analog input channels, external trigger (PFI0/TRIG1) Level Internal source, ACH<0..3>............ ± Full-scale External source, PFI0/TRIG1 ......... ±10 V, external Slope....................................................... Positive or negative (software-selectable) Resolution .............................................. 8 bits, 1 in 256 Hysteresis ...............................................
Appendix A Specifications Protection Digital trigger ..................................–0.5 V to (Vcc + 0.5) V Analog trigger On/disabled...............................±35 V Powered off ..............................±35 V RTSI Trigger Lines ..........................................7 Bus Interface Type ........................................................Master, slave Power Requirement +5 VDC (±5%) NI PCI-6110 ....................................2.5 A NI PCI-6111 ....................................
Appendix A Specifications Environmental Operating temperature............................ 0 to 45 °C Storage temperature ............................... –20 to 70 °C Humidity ................................................ 5 to 90% RH, noncondensing Maximum altitude .................................. 2000 m Pollution Degree (indoor use only) ........
Appendix A Specifications CE Compliance This product meets the essential requirements of applicable European Directives, as amended for CE marking, as follows: Low-Voltage Directive (safety)..............73/23/EEC Electromagnetic Compatibility Directive (EMC) .....................................89/336/EEC Note Refer to the Declaration of Conformity (DoC) for this product for any additional regulatory compliance information.
Cable Connector Descriptions B This appendix describes the cable connectors on the NI PCI-6110/6111. Figure B-1 shows the pin assignments for the 68-pin NI PCI-6110/6111 connector. This connector is available when you use the SH6868EP cable assemblies with the NI PCI-6110/6111. Figure B-2 shows the pin assignments for the NI PCI-6110/6111 when used with 50-pin accessories.
Appendix B Cable Connector Descriptions ACH0– ACH1+ ACH1GND ACH2–1 ACH3+1 ACH3GND1 NC NC NC NC NC NC DAC0OUT DAC1OUT NC DIO4 DGND DIO1 DIO6 DGND +5 V DGND DGND PFI0/TRIG1 PFI1/TRIG2 DGND +5 V DGND PFI5/UPDATE* PFI6/WFTRIG DGND PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 1 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 ACH0+ ACH0GND ACH1– ACH2+1 ACH2GND1 ACH3–1 NC
Appendix B Cable Connector Descriptions DIO0 25 50 DGND AOGND 24 49 23 48 NC DAC1OUT DAC0OUT 22 47 21 46 20 45 PFI8/GPCTR0_SOURCE PFI7/STARTSCAN NC NC 19 44 PFI5/UPDATE* GPCTR1_OUT NC 17 42 16 41 18 43 NC NC 15 40 14 39 13 38 NC NC NC PFI0/TRIG1 ACH3–1 12 37 11 36 ACH3+1 ACH2–1 10 35 9 34 8 33 ACH2+1 ACH1– 7 6 32 31 ACH1+ ACH0– 5 4 3 30 29 28 2 1 27 26 ACH0+ ACH<0..3>GND ACH<0..
C Common Questions This appendix contains a list of commonly asked questions and answers relating to usage and special features of the NI PCI-6110/6111. General Information What is the NI PCI-6110/6111? The NI PCI-6110/6111 is a switchless and jumperless enhanced Multifunction DAQ device that uses the DAQ-STC for timing. What is the DAQ-STC? The DAQ-STC is the system timing control application-specific integrated circuit (ASIC) designed by NI and is the backbone of the NI PCI-6110/6111.
Appendix C Common Questions What type of 5 V protection does the NI PCI-6110/6111 have? The NI PCI-6110/6111 has 5 V lines equipped with a self-resetting 1 A fuse. How do I use the NI PCI-6110/6111 with the NI-DAQ C API? The NI-DAQ User Manual for PC Compatibles describes the general programming flow and provides example code for using the NI-DAQ API. For a list of functions that support the NI PCI-6110/6111, you can refer to the NI-DAQ Function Reference Help (for NI-DAQ version 6.
Appendix C Common Questions Analog Input and Output Why is there a minimum sampling rate on the NI PCI-6110/6111? The NI PCI-6110/6111 makes use of a pipelined ADC in order to achieve its high sampling rates. Sampling at rates below 20 kS/s can result in improper digitalization, which would appear as noise in the acquired data. I connected a DIFF input signal, but the readings are random and drift rapidly. What’s wrong? Check the ground reference connections.
Appendix C Common Questions 2. Set up acquisition timing so that the timing signal for A/D conversion comes from PFI5, as follows: • If you are using NI-DAQ, call Select_Signal(deviceNumber, ND_IN_SCAN_START, ND_PFI_5, ND_HIGH_TO_LOW). • If you are using LabVIEW, invoke AI Clock Config.vi with clock source code set to PFI pin, high to low, and clock source string set to 5. 3. Initiate AI data acquisition, which starts only when the AO waveform generation starts. 4. Initiate AO waveform generation.
Appendix C Common Questions Do the counter/timer applications that I wrote previously work with the DAQ-STC? If you are using NI-DAQ with LabVIEW, some applications that were built using the CTR VIs still run. However, there are many differences between the counters of the NI PCI-6110/6111 and those of other devices: the counter numbers are different, timebase selections are different, and the DAQ-STC counters are 24-bit counters (unlike the 16-bit counters on devices without the DAQ-STC).
Appendix C Common Questions Table C-1.
Technical Support and Professional Services D Visit the following sections of the National Instruments Web site at ni.com for technical support and professional services: • Support—Online technical support resources include the following: – Self-Help Resources—For immediate answers and solutions, visit our extensive library of technical support resources available in English, Japanese, and Spanish at ni.com/support.
Appendix D Technical Support and Professional Services If you searched ni.com and could not find the answers you need, contact your local office or NI corporate headquarters. Phone numbers for our worldwide offices are listed at the front of this manual. You also can visit the Worldwide Offices section of ni.com/niglobal to access the branch office Web sites, which provide up-to-date contact information, support phone numbers, email addresses, and current events. NI PCI-6110/6111 User Manual D-2 ni.
Glossary l Symbol Prefix Value p pico 10 –12 n nano 10 –9 µ micro 10 – 6 m milli 10 –3 k kilo 10 3 M mega 10 6 G giga 10 9 T tera 10 12 Numbers/Symbols ° degrees > greater than ≥ greater than or equal to < less than ≤ less than or equal to / per % percent ± plus or minus + positive of, or plus – negative of, or minus Ω ohms © National Instruments Corporation G-1 NI PCI-6110/6111 User Manual
Glossary square root of +5 V +5 VDC source signal A A amperes A/D analog-to-digital AC alternating current ACH analog input channel signal ACH0GND analog input channel ground signal ADC analog-to-digital converter—an electronic device, often an integrated circuit, that converts an analog voltage to a digital number ADE application development environment AI analog input AIGATE analog input gate signal AIGND analog input ground signal ANSI American National Standards Institute AO an
Glossary C C Celsius CalDAC calibration DAC CH channel—pin or wire lead to which you apply or from which you read the analog or digital signal. Analog signals can be single-ended or differential. For digital signals, you group channels to form ports. Ports usually consist of either four or eight digital channels.
Glossary D D/A digital-to-analog DAC digital-to-analog converter—an electronic device, often an integrated circuit, that converts a digital number into a corresponding analog voltage or current DAC0OUT analog channel 0 voltage output signal DAC1OUT analog channel 1 voltage output signal DAQ data acquisition—a system that uses the computer to collect, receive, and generate electrical signals DAQ-STC data acquisition system timing controller—an application-specific integrated circuit (ASIC) for th
Glossary DOC the Canadian Department of Communications DoC Declaration of Conformity E edge detection a technique that locates an edge of an analog signal, such as the edge of a square wave EEPROM electrically erasable programmable read-only memory—ROM that can be erased with an electrical signal and reprogrammed EMC electromechanical compliance ENOB effective number of bits—a measure of the actual performance of an A/D converter after its various noise sources and nonlinearities are included.
Glossary FIFO first-in first-out memory buffer—FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be read or written. For example, an analog input FIFO stores the results of A/D conversions until the data can be read into system memory. Programming the DMA controller and servicing interrupts can take several milliseconds in some cases. During this time, data accumulates in the FIFO for future retrieval.
Glossary GPCTR1_UP_DOWN general-purpose counter 1 up down signal ground an electrically neutral wire that has the same potential as the surrounding earth; a common reference point for an electrical system H h hour hex hexadecimal Hz hertz I ICTR 8253 Programmable Interval Timer—applies to legacy DAQ products, such as the 1200 series INL integral nonlinearity—for an ADC, deviation of codes of the actual transfer function from a straight line interchannel delay amount of time that passes betwe
Glossary K kHz kilohertz L LabVIEW a graphical programming language LED light emitting diode library a file containing compiled object modules, each comprised of one of more functions, that can be linked to other object modules that make use of these functions. NIDAQ32.LIB is a library that contains NI-DAQ functions.
Glossary mux multiplexer—a switching device with multiple inputs that sequentially connects each of its inputs to its output, typically at high speeds, in order to measure several signals with a single analog input channel mV millivolts N NC not connected NI National Instruments NI-DAQ National Instruments driver software for DAQ hardware noise an undesirable electrical signal—Noise comes from external sources such as the AC power line, motors, generators, transformers, fluorescent lights, CRT d
Glossary PFI2/CONVERT* PFI2/convert PFI3/GPCTR1_SOURCE PFI3/general-purpose counter 1 source PFI4/GPCTR1_GATE PFI4/general-purpose counter 1 gate PFI5/UPDATE* PFI5/update PFI6/WFTRIG PFI6/waveform trigger PFI7/STARTSCAN PFI7/start of scan PFI8/GPCTR0_SOURCE PFI8/general-purpose counter 0 source PFI9/GPCTR0_GATE PFI9/general-purpose counter 0 gate PGIA Programmable Gain Instrumentation Amplifier Plug and Play devices devices that do not require DIP switches or jumpers to configure resourc
Glossary R RAM random access memory range the maximum and minimum parameters between which a sensor, instrument, or device operates with a specified set of characteristics referenced signal sources signal sources with voltage signals that are referenced to a system ground, such as the earth or a building ground. Also called grounded signal sources. resolution the smallest signal increment that can be detected by a measurement system.
Glossary scan rate reciprocal of the scan interval SCANCLK scan clock signal SCSI small computer system interface—a high-speed, peripheral-connect interface primarily used for hard disks, CD-ROM drives, tape drives, and other mass-storage devices to PCs settling time the amount of time required for a voltage to reach its final value within specified limits SFDR spurious-free dynamic range—the dynamic range from full-scale deflection to the highest spurious signal in the frequency domain SI2 samp
Glossary thermocouple a temperature sensor created by joining two dissimilar metals; the junction produces a small voltage as a function of the temperature TIO timing I/O toff an offset (delayed) pulse; the offset is t nanoseconds from the falling edge of the CONVERT* signal tout output delay time tP pulse period TRIG trigger signal trigger any event that causes or starts some form of data capture tsc source clock period tsp source pulse width TTL transistor-transistor logic tw pulse w
Glossary VIH volts, input high VIL volts, input low Vin volts in Vm measured voltage VOH volts, output high VOL volts, output low Vref reference voltage Vrms volts, root mean square Vs ground-referenced signal source W WFTRIG NI PCI-6110/6111 User Manual waveform generation trigger signal G-14 ni.
Index Symbols differential connections ground-referenced signal sources (figure), 4-11 nonreferenced or floating signal sources (figure), 4-12 signal summary (table), 4-6 specifications, A-1 working voltage range, 4-13 ACH<0..
Index NI PCI-6111, 3-2 analog trigger, 3-5 analog output number of channels, 3-4 output range, 3-4 questions about, C-3 signal connections, 4-14 specifications dynamic characteristics, A-6 output characteristics, A-5 stability, A-6 transfer characteristics, A-5 voltage output, A-5 analog trigger above-high-level analog triggering mode (figure), 3-6 avoiding false triggering (note), 3-4 below-low-level analog triggering mode (figure), 3-6 block diagrams NI PCI-6110, 3-5 NI PCI-6111, 3-5 high-hysteresis ana
Index typical posttriggered acquisition (figure), 4-18 typical pretriggered acquisition (figure), 4-19 counter/timer applications, C-5 custom cabling, 1-4 customer education, D-1 professional services, D-1 technical support, D-1 DAQ-STC. See DAQ-STC system timing controller data acquisition timing connections.
Index G drivers instrument, D-1 software, D-1 dynamic characteristics specifications analog input, A-3 analog output, A-6 general-purpose timing signal connections FREQ_OUT signal, 4-37 GPCTR0_GATE signal, 4-31 GPCTR0_OUT signal, 4-32 GPCTR0_SOURCE signal, 4-31 GPCTR0_UP_DOWN signal, 4-33 GPCTR1_GATE signal, 4-34 GPCTR1_OUT signal, 4-35 GPCTR1_SOURCE signal, 4-33 GPCTR1_UP_DOWN signal, 4-35 overview, 4-30 getting started, equipment, 1-2 GPCTR0_GATE signal See also PFI9/GPCTR0_GATE signal general-purpose
Index GPCTR1_OUT signal description (table), 4-5 general-purpose counter timing summary (figure), 4-36 general-purpose timing connections, 4-35 signal summary (table), 4-7 GPCTR1_SOURCE signal general-purpose counter timing summary (figure), 4-36 general-purpose timing connections, 4-33 relation to GPCTR1_OUT signal, 4-35 timing diagram, 4-33 GPCTR1_UP_DOWN signal digital I/O lines, 3-8 general-purpose timing connections, 4-35 ground-referenced signal sources description, 4-9 differential connections, 4-11
Index K questions about analog input and output, C-3 general information, C-1 installing and configuring, C-2 timing and digital I/O, C-4 requirements for getting started, 1-2 software programming choices, 1-2 unpacking, 1-5 NI-DAQ overview, 1-2 questions about, C-2 noise avoiding, 4-37 rejecting common-mode, 4-12 KnowledgeBase, D-1 L LabVIEW application software, 1-3 loading calibration constants, 5-1 lowValue, 3-5, 3-6, 3-7 M manual.
Index PFI2/CONVERT* signal See also CONVERT* signal description (table), 4-5 signal summary (table), 4-6 PFI3/GPCTR1_SOURCE signal See also GPCTR1_SOURCE signal description (table), 4-5 signal summary (table), 4-7 PFI4/GPCTR1_GATE signal See also GPCTR1_GATE signal description (table), 4-5 signal summary (table), 4-7 PFI5/UPDATE* signal See also UPDATE* signal description (table), 4-5 signal summary (table), 4-7 PFI6/WFTRIG signal See also WFTRIG signal description (table), 4-5 signal summary (table), 4-7
Index R digital I/O, 4-15 field wiring considerations, 4-37 I/O connector connector details (table), 4-1 exceeding maximum ratings (caution), 4-1 pin assignments 50-pin connector (figure), 4-3 68-pin connector (figure), 4-2 signal descriptions (table), 4-3 signal summary (table), 4-6 power connections, 4-16 timing connections DAQ timing connections AIGATE signal, 4-25 CONVERT* signal, 4-24 EXTSTROBE* signal, 4-27 overview, 4-18 SCANCLK signal, 4-26 SISOURCE signal, 4-26 STARTSCAN signal, 4-22 TRIG1 signal
Index waveform generation timing connections overview, 4-27 UISOURCE signal, 4-30 UPDATE* signal, 4-29 WFTRIG signal, 4-28 types of signal sources floating, 4-9 ground-referenced, 4-9 SISOURCE signal timing connections, 4-26 timing diagram, 4-26 software drivers, D-1 software installation, 2-1 software programming choices LabVIEW, 1-3 Measurement Studio, 1-4 National Instruments application software, 1-3 NI-DAQ, 1-2 overview, 1-2 VI Logger, 1-4 software-programmable gain, 3-3 actual range and measurement p
Index EXTSTROBE* signal, 4-27 overview, 4-18 SCANCLK signal, 4-26 SISOURCE signal, 4-26 STARTSCAN signal, 4-22 TRIG1 signal, 4-19 TRIG2 signal, 4-20 typical posttriggered acquisition (figure), 4-18 typical pretriggered acquisition (figure), 4-19 general-purpose timing signal connections FREQ_OUT signal, 4-37 GPCTR0_GATE signal, 4-31 GPCTR0_OUT signal, 4-32 GPCTR0_SOURCE signal, 4-31 GPCTR0_UP_DOWN signal, 4-33 GPCTR1_GATE signal, 4-34 GPCTR1_OUT signal, 4-35 GPCTR1_SOURCE signal, 4-33 GPCTR1_UP_DOWN signal
Index W WFTRIG signal See also PFI6/WFTRIG signal timing connections, 4-28 using with UPDATE* signal, 4-30 wiring considerations, 4-37 working voltage range, 4-13 worldwide technical support, D-2 waveform generation timing connections overview, 4-27 questions about, C-3 UISOURCE signal, 4-30 UPDATE* signal, 4-29 WFTRIG signal, 4-28 Web professional services, D-1 technical support, D-1 © National Instruments Corporation I-11 NI PCI-6110/6111 User Manual
