DAQ M Series NI 6238/6239 User Manual Isolated Current Input/Current Output Devices NI 6238/6239 User Manual July 2006 371913A-01
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Important Information Warranty The NI 6238/6239 is warranted against defects in materials and workmanship for a period of three years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
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Contents About This Manual Conventions ...................................................................................................................xiii Related Documentation..................................................................................................xiv NI-DAQ...........................................................................................................xiv NI-DAQmx for Linux......................................................................................
Contents Chapter 4 Analog Input Analog Input Circuitry .................................................................................................. 4-1 Analog Input Range....................................................................................................... 4-2 Connecting Analog Current Input Signals .................................................................... 4-3 Method 1 .........................................................................................................
Contents AI Pause Trigger Signal ..................................................................................4-24 Using a Digital Source ......................................................................4-24 Routing AI Pause Trigger Signal to an Output Terminal .................4-25 Getting Started with AI Applications in Software.........................................................4-25 Chapter 5 Analog Output Analog Output Circuitry ..........................................................
Contents Chapter 7 Counters Counter Input Applications ........................................................................................... 7-3 Counting Edges ............................................................................................... 7-3 Single Point (On-Demand) Edge Counting ...................................... 7-3 Buffered (Sample Clock) Edge Counting......................................... 7-4 Non-Cumulative Buffered Edge Counting .......................................
Contents Counter Timing Signals .................................................................................................7-26 Counter n Source Signal..................................................................................7-26 Routing a Signal to Counter n Source...............................................7-27 Routing Counter n Source to an Output Terminal ............................7-27 Counter n Gate Signal .............................................................................
Contents Chapter 8 PFI Using PFI Terminals as Timing Input Signals .............................................................. 8-2 Exporting Timing Output Signals Using PFI Terminals............................................... 8-3 Using PFI Terminals as Static Digital Inputs and Outputs............................................ 8-3 Connecting PFI Input Signals........................................................................................ 8-3 PFI Filters ....................................
Contents Chapter 11 Bus Interface DMA Controllers ...........................................................................................................11-1 PXI Considerations ........................................................................................................11-2 PXI Clock and Trigger Signals........................................................................11-2 PXI and PXI Express.......................................................................................
About This Manual The NI 6238/6239 User Manual contains information about using the NI 6238 and NI 6239 M Series data acquisition (DAQ) devices with NI-DAQmx 8.1 and later. National Instruments 6238/6239 devices feature up to eight differential analog input (AI) channels, two analog output (AO) channels, two counters, six lines of digital input (DI), and four lines of digital output (DO).
About This Manual italic Italic text denotes variables, emphasis, a cross-reference, or an introduction to a key concept. Italic text also denotes text that is a placeholder for a word or value that you must supply. monospace Text in this font denotes text or characters that you should enter from the keyboard, sections of code, programming examples, and syntax examples.
About This Manual The C Function Reference Help describes functions and attributes. The NI-DAQmx for Linux Configuration Guide provides configuration instructions, templates, and instructions for using test panels. Note All NI-DAQmx documentation for Linux is installed at /usr/local/natinst/nidaqmx/docs.
About This Manual tools. Refer to the following locations on the Contents tab of the LabVIEW Help for information about NI-DAQmx: • Getting Started»Getting Started with DAQ—Includes overview information and a tutorial to learn how to take an NI-DAQmx measurement in LabVIEW using the DAQ Assistant. • VI and Function Reference»Measurement I/O VIs and Functions—Describes the LabVIEW NI-DAQmx VIs and properties.
About This Manual .NET Languages without NI Application Software The NI Measurement Studio Help contains function reference and measurement concepts for using the Measurement Studio NI-DAQmx .NET and Visual C++ class libraries. This help collection is integrated into the Visual Studio .NET documentation. In Visual Studio .NET, select Help»Contents. Note You must have Visual Studio .NET installed to view the NI Measurement Studio Help.
1 Getting Started M Series NI 6238/6239 devices feature eight differential analog input (AI) channels, two analog output (AO) channels, two counters, six lines of digital input (DI), and four lines of digital output (DO). If you have not already installed your device, refer to the DAQ Getting Started Guide. For NI 6238 and NI 6239 device specifications, refer to the NI 6238/6239 Specifications on ni.com/manuals.
Chapter 1 Getting Started Device Specifications Refer to the NI 6238/6239 Specifications, available on the NI-DAQ Device Document Browser or ni.com/manuals, for more detailed information on NI 6238/6239 devices. Device Accessories and Cables NI offers a variety of accessories and cables to use with your DAQ device. Refer to Appendix A, Device-Specific Information, or ni.com for more information. NI 6238/6239 User Manual 1-2 ni.
2 DAQ System Overview Figure 2-1 shows a typical DAQ system, which includes sensors, transducers, cables that connect the various devices to the accessories, the M Series device, programming software, and PC. The following sections cover the components of a typical DAQ system. Sensors and Transducers Cables and Accessories DAQ Hardware DAQ Software Personal Computer Figure 2-1.
Chapter 2 DAQ System Overview A Isolation Barrier Analog Input I/O Connector AI GND A Digital Routing and Clock Generation Analog Output AO GND A Bus Interface Bus Digital Isolators Counters RTSI PFI/Static DI P0.GND P0 PFI/Static DO P1 P1.GND Figure 2-2. General NI 6238/6239 Block Diagram DAQ-STC2 The DAQ-STC2 implements a high-performance digital engine for NI 6238/6239 data acquisition hardware.
Chapter 2 DAQ System Overview Calibration Circuitry The M Series analog inputs and outputs can self calibrate to correct gain and offset errors. You can calibrate the device to minimize AI and AO errors caused by time and temperature drift at run time. No external circuitry is necessary; an internal reference ensures high accuracy and stability over time and temperature changes. Factory-calibration constants are permanently stored in an onboard EEPROM and cannot be modified.
Chapter 2 DAQ System Overview Cables and Accessories NI offers a variety of products to use with NI 6238/6239 devices, including cables, connector blocks, and other accessories, as follows: • Cables and cable assemblies – Shielded – Unshielded ribbon • Screw terminal connector blocks, shielded and unshielded • RTSI bus cables For more specific information about these products, refer to ni.com.
Chapter 2 DAQ System Overview Programming Devices in Software National Instruments measurement devices are packaged with NI-DAQ driver software, an extensive library of functions and VIs you can call from your application software, such as LabVIEW or LabWindows/CVI, to program all the features of your NI measurement devices. Driver software has an application programming interface (API), which is a library of VIs, functions, classes, attributes, and properties for creating applications for your device.
3 Connector Information The I/O Connector Signal Descriptions and RTSI Connector Pinout sections contain information on M Series connectors. Refer to Appendix A, Device-Specific Information, for device I/O connector pinouts. I/O Connector Signal Descriptions Table 3-1 describes the signals found on the I/O connectors. Not all signals are available on all devices. Table 3-1.
Chapter 3 Connector Information Table 3-1. I/O Connector Signals (Continued) Signal Name AO GND Reference Direction — — Description Analog Output Ground—AO GND is the reference for AO <0..1>. AI GND and AO GND are connected on the device. Note: AI GND and AO GND are isolated from earth ground, chassis ground, P0.GND, and P1.GND. PFI <0..5>/P0.<0..5> P0.
Chapter 3 Connector Information Table 3-1. I/O Connector Signals (Continued) Signal Name Reference Direction Description CAL+ — — External Calibration Positive Reference—CAL+ supplies the positive reference during external calibration of the NI 6238/6239. CAL– — — External Calibration Negative Reference—CAL– supplies the negative reference during external calibration of the NI 6238/6239.
4 Analog Input Figure 4-1 shows the analog input circuitry of NI 6238 and NI 6239 devices. Isolation Barrier I/O Connector AI <0..7>+ Mux AI <0..7>– AI Terminal Configuration Selection NI-PGIA ADC Digital Isolators AI FIFO AI Data Input Range Selection AI GND Figure 4-1. NI 6238/6239 Analog Input Circuitry Analog Input Circuitry I/O Connector You can connect analog input signals to the M Series device through the I/O connector.
Chapter 4 Analog Input for all input ranges. The NI-PGIA can amplify or attenuate an AI signal to ensure that you use the maximum resolution of the ADC. M Series devices use the NI-PGIA to deliver high accuracy even when sampling multiple channels with small input ranges at fast rates. M Series devices can sample channels in any order at the maximum conversion rate, and you can individually program each channel in a sample with a different input range.
Chapter 4 Analog Input (20 mA – (–20 mA)) = 610 nA 216 M Series devices use a calibration method that requires some codes (typically about 5% of the codes) to lie outside of the specified range. This calibration method improves absolute accuracy, but it increases the nominal resolution of input ranges by about 5% over what the formulas shown above would indicate. Choose an input range that matches the expected input range of your signal.
Chapter 4 Analog Input Isolation Barrier AI + + AI – – + V – AI GND AI GND Figure 4-2. Analog Current Input Connection Method 1 Method 2 Method 2, shown in Figure 4-3, ties the AI – input to AI GND. When measuring current up to 20 mA, this type of connection ensures that the voltage level on both the positive and negative side are within the common-mode input range for NI 6238/6239 devices. Isolation Barrier AI + + AI – – AI GND Figure 4-3.
Chapter 4 Analog Input Note that AI GND must always be connected to some voltage level. AI GND is the reference that NI 6238/6239 devices measure against. The NI 6238 and NI 6239 are isolated devices with isolation ratings up to 60 VDC/30 Vrms. This allows for current measurement at high voltage levels provided that the common-mode input range requirement is satisfied. For example, in Figure 4-4, the node connected to AI GND can be at 50 V above the earth ground.
Chapter 4 Analog Input Instrumentation Amplifier Iin+ Current Sense Resistor Iin– + PGIA Vm Measured Voltage AI GND – Vm = Iin • R × Gain Figure 4-5. NI 6238/6239 PGIA Analog input ground-reference setting refers to the reference that the PGIA measures against.
Chapter 4 Analog Input Caution The maximum input voltages rating of AI signals with respect to AI GND (and for differential signals with respect to each other) and earth/chassis ground are listed in the Maximum Working Voltage section of the NI 6238/6239 Specifications. Exceeding the maximum input voltage or maximum working voltage of AI signals distorts the measurement results. Exceeding the maximum input voltage or maximum working voltage rating also can damage the device and the computer.
Chapter 4 Analog Input Multichannel Scanning Considerations M Series devices can scan multiple channels at high rates and digitize the signals accurately. However, you should consider several issues when designing your measurement system to ensure the high accuracy of your measurements. In multichannel scanning applications, accuracy is affected by settling time.
Chapter 4 Analog Input For example, suppose all channels in a system use a –20 to 20 mA input range. The signals on channels 0, 2, and 4 vary between 18 and 19 mA. The signals on channels 1, 3, and 5 vary between –18 and 0 mA. Scanning channels in the order 0, 2, 4, 1, 3, 5 will produce more accurate results than scanning channels in the order 0, 1, 2, 3, 4, 5. Avoid Scanning Faster Than Necessary Designing your system to scan at slower speeds gives the PGIA more time to settle to a more accurate level.
Chapter 4 Analog Input Analog Input Data Acquisition Methods When performing analog input measurements, you either can perform software-timed or hardware-timed acquisitions. Hardware-timed acquisitions can be buffered or non-buffered. Software-Timed Acquisitions With a software-timed acquisition, software controls the rate of the acquisition. Software sends a separate command to the hardware to initiate each ADC conversion.
Chapter 4 Analog Input samples has been written out, the generation stops. If you use a reference trigger, you must use finite sample mode. Continuous acquisition refers to the acquisition of an unspecified number of samples. Instead of acquiring a set number of data samples and stopping, a continuous acquisition continues until you stop the operation. Continuous acquisition is also referred to as double-buffered or circular-buffered acquisition.
Chapter 4 Analog Input mainly to AI signal routing to the device, although they also apply to signal routing in general. Minimize noise pickup and maximize measurement accuracy by using individually shielded, twisted-pair wires to connect AI signals to the device. With this type of wire, the signals attached to the positive and negative input channels are twisted together and then covered with a shield. You then connect this shield only at one point to the signal source ground.
Chapter 4 Analog Input M Series devices use ai/SampleClock and ai/ConvertClock to perform interval sampling. As Figure 4-8 shows, ai/SampleClock controls the sample period, which is determined by the following equation: 1/Sample Period = Sample Rate Channel 0 Channel 1 Convert Period Sample Period Figure 4-8.
Chapter 4 Analog Input When this calculation results in the sampling rate exceeding 35 kHz, there is not enough time between samples to acquire both channels and still add a 10 μs delay per channel, so the Convert Clock rate becomes the sampling rate multiplied by the number of channels being acquired. For example, on the PCI-6220 M Series device, a sampling rate of 40 kHz for two channels would result in a Convert Clock rate of 80 kHz. Maximum settling time for the amplifier is also very important.
Chapter 4 Analog Input example, four. The value decrements with each pulse on ai/SampleClock, until the value reaches zero. The sample counter is then loaded with the number of posttriggered samples, in this example, three. ai/StartTrigger ai/ReferenceTrigger n/a ai/SampleClock ai/ConvertClock Scan Counter 3 2 1 0 2 2 2 1 0 Figure 4-10.
Chapter 4 Analog Input You can specify an internal or external source for ai/SampleClock. You also can specify whether the measurement sample begins on the rising edge or falling edge of ai/SampleClock. Using an Internal Source One of the following internal signals can drive ai/SampleClock. • Counter n Internal Output • AI Sample Clock Timebase (divided down) • A pulse initiated by host software A programmable internal counter divides down the sample clock timebase.
Chapter 4 Analog Input Other Timing Requirements Your DAQ device only acquires data during an acquisition. The device ignores ai/SampleClock when a measurement acquisition is not in progress. During a measurement acquisition, you can cause your DAQ device to ignore ai/SampleClock using the ai/PauseTrigger signal. A counter on your device internally generates ai/SampleClock unless you select some external source.
Chapter 4 Analog Input • RTSI <0..7> • Input PFI <0..5> • PXI_STAR ai/SampleClockTimebase is not available as an output on the I/O connector. ai/SampleClockTimebase is divided down to provide one of the possible sources for ai/SampleClock. You can configure the polarity selection for ai/SampleClockTimebase as either rising or falling edge. AI Convert Clock Signal Caution Setting the conversion rate higher than the maximum rate specified for your device will result in errors.
Chapter 4 Analog Input finished. It then reloads itself in preparation for the next ai/SampleClock pulse. Using an External Source Use one of the following external signals as the source of ai/ConvertClock: • Input PFI <0..5> • RTSI <0..7> • PXI_STAR Note Refer to the NI 6238/6239 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>.
Chapter 4 Analog Input ai/ConvertClockTimebase ai/SampleClock ai/ConvertClock Delay From Sample Clock Convert Period Figure 4-12. ai/SampleClock and ai/ConvertClock Other Timing Requirements The sample and conversion level timing of M Series devices work such that clock signals are gated off unless the proper timing requirements are met. For example, the device ignores both ai/SampleClock and ai/ConvertClock until it receives a valid ai/StartTrigger signal.
Chapter 4 Analog Input ai/SampleClock ai/ConvertClock Channel Measured 0 1 2 3 0 1 2 3 0 1 … Sample #1 Sample #2 Sample #3 • One External Signal Driving Both Clocks Figure 4-13. Single External Signal Driving ai/SampleClock and ai/ConvertClock Simultaneously AI Convert Clock Timebase Signal The AI Convert Clock Timebase (ai/ConvertClockTimebase) signal is divided down to provide on of the possible sources for ai/ConvertClock.
Chapter 4 Analog Input AI Start Trigger Signal Use the AI Start Trigger (ai/StartTrigger) signal to begin a measurement acquisition. A measurement acquisition consists of one or more samples. If you do not use triggers, begin a measurement with a software command.
Chapter 4 Analog Input complete description of the use of ai/StartTrigger and ai/ReferenceTrigger in a pretriggered DAQ operation. AI Reference Trigger Signal Use a reference trigger (ai/ReferenceTrigger) signal to stop a measurement acquisition. To use a reference trigger, specify a buffer of finite size and a number of pretrigger samples (samples that occur before the reference trigger).
Chapter 4 Analog Input Using a Digital Source To use ai/ReferenceTrigger with a digital source, specify a source and an edge. The source can be any of the following signals: • Input PFI <0..5> • RTSI <0..7> • PXI_STAR The source also can be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.
Chapter 4 Analog Input Routing AI Pause Trigger Signal to an Output Terminal You can route ai/PauseTrigger out to RTSI <0..7>. Note Pause triggers are only sensitive to the level of the source, not the edge. Getting Started with AI Applications in Software You can use the M Series device in the following analog input applications.
5 Analog Output NI 6238/6239 devices have two AO channels controlled by a single clock and capable of waveform generation. Figure 5-1 shows the analog current output circuitry of NI 6238 and NI 6239 devices. V-I Converter Isolation Barrier AO POWER SUPPLY DAC0 AO 0 Digital Isolators V-I Converter AO FIFO DAC1 AO Sample Clock AO 1 AO GND Figure 5-1.
Chapter 5 Analog Output DACs. It allows you to download the points of a waveform to your M Series device without host computer interaction. AO Sample Clock The AO Sample Clock signal reads a sample from the DAC FIFO and generates the AO voltage. Isolation Barrier and Digital Isolators The digital isolators across the isolation barrier provide a ground break between the isolated analog front end and the earth/chassis/building ground.
Chapter 5 Analog Output Non-Buffered In non-buffered acquisitions, data is written directly to the DACs on the device. Typically, hardware-timed, non-buffered operations are used to write single samples with good latency and known time increments between them. Buffered In a buffered acquisition, data is moved from a PC buffer to the DAQ device’s onboard FIFO using DMA or interrupts before it is written to the DACs one sample at a time.
Chapter 5 Analog Output the buffer at a fast enough rate to keep up with the generation, the buffer will underflow and cause an error. Analog Output Triggering Analog output supports two different triggering actions: • Start trigger • Pause trigger A digital trigger can initiate these actions. NI 6238/6239 devices support digital triggering, but do not support analog triggering. Refer to the AO Start Trigger Signal and AO Pause Trigger Signal sections for more information on these triggering actions.
Chapter 5 Analog Output Maximum Working Voltage section of the NI 6238/6239 Specifications. Exceeding the maximum input supply voltage or maximum working voltage of AO signals distorts the measurement results. Exceeding the maximum input supply voltage or maximum working voltage rating also can damage the device and the computer. Exceeding the maximum output voltage can cause injury and harm the user. NI is not liable for any damage or injuries resulting from such signal connections.
Chapter 5 Analog Output Using a Digital Source To use ao/StartTrigger, specify a source and an edge. The source can be one of the following signals: • A pulse initiated by host software • Input PFI <0..5> • RTSI <0..7> • ai/ReferenceTrigger • ai/StartTrigger • PXI_STAR Note Refer to the NI 6238/6239 Specifications for the minimum allowable pulse width and the propagation delay of PFI <0..5>. The source also can be one of several internal signals on your DAQ device.
Chapter 5 Analog Output onboard clock, the generation resumes as soon as the pause trigger is deasserted, as shown in Figure 5-4. Pause Trigger Sample Clock Figure 5-4. ao/PauseTrigger with the Onboard Clock Source If you are using any signal other than the onboard clock as the source of your sample clock, the generation resumes as soon as the pause trigger is deasserted and another edge of the sample clock is received, as shown in Figure 5-5. Pause Trigger Sample Clock Figure 5-5.
Chapter 5 Analog Output You also can specify whether the samples are paused when ao/PauseTrigger is at a logic high or low level. Routing AO Pause Trigger Signal to an Output Terminal You can route ao/PauseTrigger out to RTSI <0..7>. AO Sample Clock Signal Use the AO Sample Clock (ao/SampleClock) signal to initiate AO samples. Each sample updates the outputs of all of the DACs. You can specify an internal or external source for ao/SampleClock.
Chapter 5 Analog Output Other Timing Requirements A counter on your device internally generates ao/SampleClock unless you select some external source. ao/StartTrigger starts the counter and either the software or hardware can stop it after a finite generation completes. When using an internally generated ao/SampleClock, you also can specify a configurable delay from ao/StartTrigger to the first ao/SampleClock pulse. By default, this delay is two ticks of ao/SampleClockTimebase.
Chapter 5 Analog Output ao/SampleClockTimebase is not available as an output on the I/O connector. You might use ao/SampleClockTimebase if you want to use an external sample clock signal, but need to divide the signal down. If you want to use an external sample clock signal but do not need to divide the signal, then you should use ao/SampleClock rather than ao/SampleClockTimebase. Getting Started with AO Applications in Software You can use an M Series device in the following analog output applications.
Digital Input and Output 6 NI 6238/6239 devices have six static digital input lines, P0.<0..5>. These lines also can be used as PFI inputs. In addition, the NI 6238/6239 devices have four static digital output lines, P1.<0..3>. These lines also can be used as PFI output. The voltage input and output levels and the current drive level of the DI and DO lines are listed in the NI 6238/6239 Specifications. Refer to Chapter 8, PFI, for more information on PFI inputs and outputs.
Chapter 6 Digital Input and Output Connecting Digital I/O Signals The DI signals P0.<0..5> are referenced to P0.GND and DO signals P1.<0..3> are referenced to P1.GND. Figures 6-1 and 6-2 show P0.<0..5> and P1.<0..3> on the NI 6238 and the NI 6239 device, respectively. Digital input and output signals can range from 0 to 30 V. Refer to the NI 6238/6239 Specifications for more information. P1.VCC P1.0 P1.<0..3> Digital Isolators P1.1 P1.GND P1.GND P0.0 P0.GND P0.GND Figure 6-1.
Chapter 6 Digital Input and Output P1.VCC Buffer P1.0 P1.GND P1.<0..3> Digital Isolators P1.1 P1.GND P1.GND P0.0 P0.GND P0.GND Figure 6-2. NI 6239 Digital I/O Connections (DO Sink) Caution Exceeding the maximum input voltage or maximum working voltage ratings, which are listed in the NI 6238/6239 Specifications, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections.
Chapter 6 Digital Input and Output Table 6-1. NI 6238/6239 Logic Conventions Logic Device 0 1 NI 6238 (Source) P1.GND P1.VCC NI 6239 (Sink) P1.VCC P1.GND Getting Started with DIO Applications in Software You can use NI 6238/6239 devices in the following digital I/O applications: • Static digital input • Static digital output Note For more information about programming digital I/O applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.
7 Counters NI 6238/6239 devices have two general-purpose 32-bit counter/timers and one frequency generator, as shown in Figure 7-1. The general-purpose counter/timers can be used for many measurement and pulse generation applications. Caution When making measurements, take into account the minimum pulse width and time delay of the digital input and output lines. Refer to the NI 6238/6239 Specifications for more information.
Chapter 7 Counters Input Selection Muxes Counter 0 Counter 0 Source (Counter 0 Timebase) Counter 0 Gate Counter 0 Internal Output Counter 0 Aux Counter 0 HW Arm Counter 0 A Counter 0 B (Counter 0 Up_Down) Counter 0 TC Counter 0 Z Input Selection Muxes Counter 1 Counter 1 Source (Counter 1 Timebase) Counter 1 Gate Counter 0 Internal Output Counter 1 Aux Counter 1 HW Arm Counter 1 A Counter 1 B (Counter 1 Up_Down) Counter 0 TC Counter 1 Z Input Selection Muxes Frequency Generator Frequency Output
Chapter 7 Counters Counter Input Applications Counting Edges In edge counting applications, the counter counts edges on its Source after the counter is armed. You can configure the counter to count rising or falling edges on its Source input. You also can control the direction of counting (up or down). The counter values can be read on demand or with a sample clock.
Chapter 7 Counters Counter Armed Pause Trigger (Pause When Low) SOURCE Counter Value 0 0 1 2 3 4 5 Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger Buffered (Sample Clock) Edge Counting With buffered edge counting (edge counting using a sample clock), the counter counts the number of edges on the Source input after the counter is armed. The value of the counter is sampled on each active edge of a sample clock. A DMA controller transfers the sampled values to host memory.
Chapter 7 Counters Non-Cumulative Buffered Edge Counting Non-cumulative edge counting is similar to buffered (sample clock) edge counting. However, the counter resets after each active edge of the Sample Clock. You can route the Sample Clock to the Gate input of the counter. Figure 7-5 shows an example of non-cumulative buffered edge counting. Counter Armed Sample Clock (Sample on Rising Edge) SOURCE Counter Value 0 1 2 1 2 Buffer 2 3 1 2 3 2 3 1 2 3 3 Figure 7-5.
Chapter 7 Counters Pulse-Width Measurement In pulse-width measurements, the counter measures the width of a pulse on its Gate input signal. You can configure the counter to measure the width of high pulses or low pulses on the Gate signal. You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges on the Source signal while the pulse on the Gate signal is active.
Chapter 7 Counters The counter counts the number of edges on the Source input while the Gate input remains active. On each trailing edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory. Figure 7-7 shows an example of a buffered pulse-width measurement. GATE SOURCE 0 Counter Value 1 2 1 3 2 3 Buffer 3 3 2 2 Figure 7-7.
Chapter 7 Counters Single Period Measurement With single period measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between two active edges of the Gate input. On the second active edge of the Gate input, the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs. Software then can read the stored count. Figure 7-8 shows an example of a single period measurement.
Chapter 7 Counters Counter Armed GATE SOURCE 1 Counter Value 2 1 2 2 2 (Discard) 3 1 2 3 2 (Discard) 3 1 3 2 (Discard) 3 3 3 Buffer Figure 7-9. Buffered Period Measurement Note that if you are using an external signal as the Source, at least one Source pulse should occur between each active edge of the Gate signal. This condition ensures that correct values are returned by the counter. If this condition is not met, consider using duplicate count prevention.
Chapter 7 Counters Buffered Semi-Period Measurement In buffered semi-period measurement, on each edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory. The counter begins counting when it is armed. The arm usually occurs between edges on the Gate input. So the first value stored in the hardware save register does not reflect a full semi-period of the Gate input.
Chapter 7 Counters You can route the signal to measure (F1) to the Gate of a counter. You can route a known timebase (Ft) to the Source of the counter. The known timebase can be 80MHzTimebase. For signals that might be slower than 0.02 Hz, use a slower known timebase. You can configure the counter to measure one period of the gate signal. The frequency of F1 is the inverse of the period. Figure 7-11 illustrates this method.
Chapter 7 Counters T1 F1 Gate Ft Source Intervals Measured T2 … TK F1 1 2 ...N11... ...N2 … 1... ...NK Ft Buffered Period Measurement Average Period of F1 = Frequency of F1 = N1 + N2 + …NK K × 1 Ft K × Ft N1 + N2 + …NK Figure 7-12. Method 1b Method 2—Measure High Frequency with Two Counters In this method, you measure one pulse of a known width using your signal and derive the frequency of your signal from the result. This method is good for high frequency signals.
Chapter 7 Counters Width of Pulse (T) Pulse Pulse Gate 1 F1 Source 2 N … F1 Width of T = Pulse Pulse-Width Measurement N F1 Frequency of F1 = N T Figure 7-13. Method 2 Method 3—Measure Large Range of Frequencies Using Two Counters By using two counters, you can accurately measure a signal that might be high or low frequency. This technique is called reciprocal frequency measurement. In this method, you generate a long pulse using the signal to measure.
Chapter 7 Counters Signal to Measure (F1) SOURCE OUT COUNTER 0 Signal of Known Frequency (F2) SOURCE OUT COUNTER 1 GATE CTR_0_SOURCE (Signal to Measure) CTR_0_OUT (CTR_1_GATE) 0 1 2 3 … N Interval to Measure CTR_1_SOURCE Figure 7-14. Method 3 Then route the Counter 0 Internal Output signal to the Gate input of Counter 1. You can route a signal of known frequency (F2) to the Counter 1 Source input. F2 can be 80MHzTimebase. For signals that might be slower than 0.
Chapter 7 Counters 80 MHz Timebase. Your measurement may return 1600 ±1 cycles depending on the phase of the signal with respect to the timebase. As your frequency becomes larger, this error of ±1 cycle becomes more significant; Table 7-1 illustrates this point. Table 7-1.
Chapter 7 Counters Table 7-2. Frequency Measurement Method Comparison Measures High Frequency Signals Accurately Measures Low Frequency Signals Accurately Method Number of Counters Used Number of Measurements Returned 1 1 1 Poor Good 1b 1 Many Fair Good 2 1 or 2 1 Good Poor 3 2 1 Good Good For information on connecting counter signals, refer to the Default Counter Terminals section.
Chapter 7 Counters Ch A Ch B Counter Value 5 6 7 7 5 6 Figure 7-15. X1 Encoding X2 Encoding The same behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A, depending on which channel leads the other. Each cycle results in two increments or decrements, as shown in Figure 7-16. Ch A Ch B Counter Value 5 6 7 8 9 9 7 8 6 5 Figure 7-16.
Chapter 7 Counters Channel Z behavior—when it goes high and how long it stays high—differs with quadrature encoder designs. You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B. You must then ensure that channel Z is high during at least a portion of the phase you specify for reload. For instance, in Figure 7-18, channel Z is never high when channel A is high and channel B is low. Thus, the reload must occur in some other phase.
Chapter 7 Counters For information on connecting counter signals, refer to the Default Counter Terminals section. Two-Signal Edge-Separation Measurement Two-signal edge-separation measurement is similar to pulse-width measurement, except that there are two measurement signals—Aux and Gate. An active edge on the Aux input starts the counting and an active edge on the Gate input stops the counting. You must arm a counter to begin a two edge separation measurement.
Chapter 7 Counters Counter Armed Measured Interval AUX GATE SOURCE Counter Value 0 0 0 0 1 2 3 4 5 6 7 8 HW Save Register 8 8 8 Figure 7-20. Single Two-Signal Edge-Separation Measurement Buffered Two-Signal Edge-Separation Measurement Buffered and single two-signal edge-separation measurements are similar, but buffered measurement measures multiple intervals.
Chapter 7 Counters Counter Output Applications Simple Pulse Generation Single Pulse Generation The counter can output a single pulse. The pulse appears on the Counter n Internal Output signal of the counter. You can specify a delay from when the counter is armed to the beginning of the pulse. The delay is measured in terms of a number of active edges of the Source input. You can specify a pulse width. The pulse width is also measured in terms of a number of active edges of the Source input.
Chapter 7 Counters GATE (Start Trigger) SOURCE OUT Figure 7-23. Single Pulse Generation with Start Trigger Retriggerable Single Pulse Generation The counter can output a single pulse in response to each pulse on a hardware Start Trigger signal. The pulses appear on the Counter n Internal Output signal of the counter. You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of each pulse. You also can specify the pulse width.
Chapter 7 Counters Pulse Train Generation Continuous Pulse Train Generation This function generates a train of pulses with programmable frequency and duty cycle. The pulses appear on the Counter n Internal Output signal of the counter. You can specify a delay from when the counter is armed to the beginning of the pulse train. The delay is measured in terms of a number of active edges of the Source input. You specify the high and low pulse widths of the output signal.
Chapter 7 Counters Frequency Generation You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit. Using the Frequency Generator The frequency generator can output a square wave at many different frequencies. The frequency generator is independent of the two general-purpose 32-bit counter/timer modules on M Series devices. Figure 7-26 shows a block diagram of the frequency generator.
Chapter 7 Counters Frequency Output can be routed out to any output PFI <6..9> or RTSI <0..7> terminal. All PFI terminals are set to high-impedance at startup. In software, program the frequency generator as you would program one of the counters for pulse train generation. For information on connecting counter signals, refer to the Default Counter Terminals section. Frequency Division The counters can generate a signal with a frequency that is a fraction of an input signal.
Chapter 7 Counters frequency of the system. Figure 7-28 shows an example of pulse generation for ETS; the delay from the trigger to the pulse increases after each subsequent Gate active edge. GATE OUT D2 = D1 + ΔD D1 D3 = D1 + 2ΔD Figure 7-28. Pulse Generation for ETS For information on connecting counter signals, refer to the Default Counter Terminals section. Counter Timing Signals M Series devices feature the following counter timing signals.
Chapter 7 Counters performing. Table 7-3 lists how this terminal is used in various applications. Table 7-3.
Chapter 7 Counters Counter n Gate Signal The Counter n Gate signal can perform many different operations depending on the application including starting and stopping the counter, and saving the counter contents. Routing a Signal to Counter n Gate Each counter has independent input selectors for the Counter n Gate signal. Any of the following signals can be routed to the Counter n Gate input. • RTSI <0..7> • Input PFI <0..
Chapter 7 • ai/StartTrigger • PXI_STAR Counters In addition, Counter 1 Internal Output, Counter 1 Gate, Counter 1 Source, or Counter 0 Gate can be routed to Counter 0 Aux. Counter 0 Internal Output, Counter 0 Gate, Counter 0 Source, or Counter 1 Gate can be routed to Counter 1 Aux. Some of these options may not be available in some driver software. Counter n A, Counter n B, and Counter n Z Signals Counter n B can control the direction of counting in edge counting applications.
Chapter 7 Counters waiting for the Gate signal when it is armed. Counter output operations can use the arm signal in addition to a start trigger. Software can arm a counter or configure counters to be armed on a hardware signal. Software calls this hardware signal the Arm Start Trigger. Internally, software routes the Arm Start Trigger to the Counter n HW Arm input of the counter. Routing Signals to Counter n HW Arm Input Any of the following signals can be routed to the Counter n HW Arm input.
Chapter 7 Counters Routing Frequency Output to a Terminal You can route Frequency Output to any output PFI <6..9> terminal. All PFIs are set to high-impedance at startup. Default Counter Terminals By default, NI-DAQmx routes the counter/timer inputs and outputs to the PFI pins, shown in Table 7-4. Table 7-4. NI 6238/6239 Device Default NI-DAQmx Counter/Timer Pins Counter/Timer Signal Default Pin Number (Name) Port CTR 0 SRC 13 (PFI 0) P0.0 CTR 0 GATE 32 (PFI 1) P0.1 CTR 0 AUX 33 (PFI 2) P0.
Chapter 7 Counters Counter Triggering Counters support three different triggering actions—arm start, start, and pause. Arm Start Trigger To begin any counter input or output function, you must first enable, or arm, the counter. Software can arm a counter or configure counters to be armed on a hardware signal. Software calls this hardware signal the Arm Start Trigger. Internally, software routes the Arm Start Trigger to the Counter n HW Arm input of the counter.
Chapter 7 Counters Other Counter Features Cascading Counters You can internally route the Counter n Internal Output and Counter n TC signal of each counter to the Gate inputs of the other counter. By cascading two counters together, you can effectively create a 64-bit counter. By cascading counters, you also can enable other applications.
Chapter 7 Counters The filter setting for each input can be configured independently. On power up, the filters are disabled. Figure 7-29 shows an example of a low-to-high transition on an input that has its filter set to 125 ns (N = 5). RTSI, PFI, or PXI_STAR Terminal Filter Clock (40 MHz) 1 1 2 3 4 1 2 3 4 5 Filtered input goes high when terminal is sampled high on five consecutive filter clocks. Filtered Input Figure 7-29.
Chapter 7 Counters External Signal Prescaler Rollover (Used as Source by Counter) Counter Value 0 1 Figure 7-30. Prescaling Prescaling is intended to be used for frequency measurement where the measurement is made on a continuous, repetitive signal. The prescaling counter cannot be read; therefore, you cannot determine how many edges have occurred since the previous rollover. Prescaling can be used for event counting provided it is acceptable to have an error of up to seven (or one).
Chapter 7 Counters Rising Edge of Gate Counter detects rising edge of Gate on the next rising edge of Source. Gate Source Counter Value Buffer 6 7 1 7 2 1 2 7 Figure 7-31. Duplicate Count Prevention Example On the first rising edge of the Gate, the current count of 7 is stored. On the next rising edge of the Gate, the counter stores a 2 since two Source pulses occurred after the previous rising edge of Gate.
Chapter 7 Counters No Source edge, so no value written to buffer. Gate Source Counter Value 6 7 1 7 Buffer Figure 7-32. Duplicate Count Example Example Application That Prevents Duplicate Count With duplicate count prevention enabled, the counter synchronizes both the Source and Gate signals to the 80 MHz Timebase. By synchronizing to the timebase, the counter detects edges on the Gate even if the Source does not pulse.
Chapter 7 Counters counter value and Counter n Internal Output signals change synchronously to the 80 MHz Timebase. Note that duplicate count prevention should only be used if the frequency of the Source signal is 20 MHz or less. When To Use Duplicate Count Prevention You should use duplicate count prevention if the following conditions are true. • You are making a counter measurement • You are using an external signal (such as PFI <0..
Chapter 7 Counters Otherwise, the mode depends on the signal that drives Counter n Source. Table 7-6 describes the conditions for each mode. Table 7-6.
Chapter 7 Counters Source Synchronize Count Figure 7-35. Other Internal Source Mode External Source Mode In external source mode, the device generates a delayed Source signal by delaying the Source signal by several nanoseconds. The device synchronizes signals on the rising edge of the delayed Source signal, and counts on the following rising edge of the source, as shown in Figure 7-36. Source Synchronize Delayed Source Count Figure 7-36. External Source Mode NI 6238/6239 User Manual 7-40 ni.
8 PFI NI 6238/6239 devices have 10 Programmable Function Interface (PFI) signals—six input signals and four output signals. Each PFI <0..5>/P0.<0..5> can be configured as a timing input signal for AI or counter/timer functions or a static digital input. Each PFI input also has a programmable debouncing filter. Caution When making measurements, take into account the minimum pulse width and time delay of the digital input and output lines. Figure 8-1 shows the circuitry of one PFI input line.
Chapter 8 PFI Isolation Barrier Timing Signals Digital Isolators PFI <6..9>/P1.<0..3> Static DO Buffer Figure 8-2. NI 6238/6239 PFI Output Circuitry When a terminal is used as a timing input or output signal, it is called PFI x (where x is an integer from 0 to 9). When a terminal is used as a static digital input or output, it is called P0.x or P1.x. The voltage input and output levels and the current drive levels of the PFI signals are listed in the NI 6238/6239 Specifications.
Chapter 8 PFI Exporting Timing Output Signals Using PFI Terminals You can route any of the following timing signals to any PFI <6..9> terminal. • AI Hold Complete Event • Counter n Source • Counter n Gate • Counter n Internal Output • Frequency Output • PXI_STAR • RTSI <0..7> Note Short pulses on the signal might not be observable by the user or another instrument. Refer to the Digital Output (Port 1) section of the NI 6238/6239 Specifications for more information.
Chapter 8 PFI I/O Connector PFI 0 PFI 2 PFI 0 Source PFI 2 Source P0.GND M Series Device Figure 8-3. PFI Input Signals Connections PFI Filters You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal. When the filters are enabled, your device samples the input on each rising edge of a filter clock. M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency. Note NI-DAQmx only supports filters on counter inputs.
Chapter 8 PFI Table 8-1. Filters Filter Setting N (Filter Clocks Needed to Pass Signal) Pulse Width Guaranteed to Pass Filter Pulse Width Guaranteed to Not Pass Filter 125 ns 5 125 ns 100 ns 6.425 µs 257 6.425 µs 6.400 µs 2.55 ms ~101,800 2.55 ms 2.54 ms Disabled — — — The filter setting for each input can be configured independently. On power up, the filters are disabled. Figure 8-4 shows an example of a low-to-high transition on an input that has its filter set to 125 ns (N = 5).
Chapter 8 PFI Consult the device specifications for details. However, you should avoid these fault conditions by following these guidelines. • Do not connect any digital output line to any external signal source, ground signal, or power supply. • Understand the current requirements of the load connected to the digital output lines. Do not exceed the specified current output limits of the digital outputs. NI has several signal conditioning solutions for digital applications requiring high current drive.
Chapter 8 PFI P1.VCC P1.0 P1.<0..3> Digital Isolators P1.1 P1.GND P1.GND P0.0 P0.GND P0.GND Figure 8-5.
Chapter 8 PFI P1.VCC P1.0 Buffer P1.GND P1.<0..3> Digital Isolators P1.1 P1.GND P1.GND P0.0 P0.GND P0.GND Figure 8-6. NI 6239 Digital I/O Connections (DO Sink) Caution Exceeding the maximum input voltage or maximum working voltage ratings, which are listed in the NI 6238/6239 Specifications, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections. NI 6238/6239 User Manual 8-8 ni.
9 Isolation and Digital Isolators NI 6232/6233 devices are isolated data acquisition devices. As shown in Figure 9-1, the analog input, analog output, counters, and PFI/static DIO circuitry are referenced to an isolated ground. The bus interface circuitry, RTSI, digital routing, and clock generation are all referenced to a non-isolated ground. Refer to Table 9-1 for an example of the symbols for isolated ground and non-isolated ground. Table 9-1.
Chapter 9 Isolation and Digital Isolators The non-isolated ground is connected to the chassis ground of the PC or chassis where the device is installed. Each isolated ground is not connected to the chassis ground of the PC or chassis. The isolated ground can be at a higher or lower voltage relative to the non-isolated ground. All analog measurements are made relative to its isolated ground signal. Each isolated ground is an input to the NI 6238/6239 device.
Chapter 9 • Isolation and Digital Isolators Improved safety—Isolation creates an insulation barrier so you can make measurements at elevated voltages while protecting against large transient voltage spikes. Reducing Common-Mode Noise Isolated products require an isolated power supply to deliver power to the isolated side from the non-isolated side. Isolated power supplies work by switching voltages through a transformer with high-speed transistors.
10 Digital Routing and Clock Generation The digital routing circuitry has the following three main functions. • Manages the flow of data between the bus interface and the acquisition/generation sub-systems (analog input, analog output, digital I/O, and the counters). The digital routing circuitry uses FIFOs (if present) in each sub-system to ensure efficient data movement. • Routes timing and control signals.
Chapter 10 Digital Routing and Clock Generation Caution RTSI signals are not isolated from the chassis. 80 MHz Timebase The 80 MHz Timebase can be used as the Source input to the 32-bit general-purpose counter/timers. The 80 MHz Timebase can be generated from either of the following. • Onboard oscillator • External signal (by using the external reference clock) 20 MHz Timebase The 20 MHz Timebase normally generates many of the AI and AO timing signals.
Chapter 10 Digital Routing and Clock Generation 10 MHz Reference Clock The 10 MHz reference clock can be used to synchronize other devices to your M Series device. The 10 MHz reference clock can be routed to the RTSI <0..7> terminals. Other devices connected to the RTSI bus can use this signal as a clock input. The 10 MHz reference clock is generated by dividing down the onboard oscillator.
Chapter 10 Digital Routing and Clock Generation • Share trigger signals between devices Many National Instruments DAQ, motion, vision, and CAN devices support RTSI. In a PCI system, the RTSI bus consists of the RTSI bus interface and a ribbon cable. The bus can route timing and trigger signals between several functions on as many as five DAQ, vision, motion, or CAN devices in the computer. In a PXI system, the RTSI bus consists of the RTSI bus interface and the PXI trigger signals on the PXI backplane.
Chapter 10 Digital Routing and Clock Generation Table 10-1. RTSI Signal Descriptions RTSI Bus Signal Terminal RTSI 7 34 RTSI 6 32 RTSI 5 30 RTSI 4 28 RTSI 3 26 RTSI 2 24 RTSI 1 22 RTSI 0 20 Not Connected. Do not connect signals to these terminals. 1–18 GND 19, 21, 23, 25, 27, 29, 31, 33 Note: RTSI <0..7> and GND are earth/chassis ground-referenced. They are not isolated. Using RTSI as Outputs RTSI <0..7> are bidirectional terminals.
Chapter 10 Digital Routing and Clock Generation Using RTSI Terminals as Timing Input Signals You can use RTSI terminals to route external timing signals to many different M Series functions. Each RTSI terminal can be routed to any of the following signals.
Chapter 10 Digital Routing and Clock Generation Table 10-2. Filters Filter Setting N (Filter Clocks Needed to Pass Signal) Pulse Width Guaranteed to Pass Filter Pulse Width Guaranteed to Not Pass Filter 125 ns 5 125 ns 100 ns 6.425 µs 257 6.425 µs 6.400 µs 2.55 ms ~101,800 2.55 ms 2.54 ms Disabled — — — The filter setting for each input can be configured independently. On power up, the filters are disabled.
Chapter 10 Digital Routing and Clock Generation PXI_CLK10 PXI_CLK10 is a common low-skew 10 MHz clock reference clock for synchronization of multiple modules in a PXI measurement or control system. The PXI backplane is responsible for generating PXI_CLK10 independently to each peripheral slot in a PXI chassis. PXI Triggers A PXI chassis provides eight bused trigger lines to each module in a system.
Chapter 10 Digital Routing and Clock Generation input on each rising edge of a filter clock. M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency. Note NI-DAQmx only supports filters on counter inputs. The following is an example of low-to-high transitions of the input signal. High-to-low transitions work similarly. Assume that an input terminal has been low for a long time. The input terminal then changes from low-to-high, but glitches several times.
Chapter 10 Digital Routing and Clock Generation When a PFI input is routed directly to RTSI, or a RTSI input is routed directly to PFI, the M Series device does not use the filtered version of the input signal. Refer to the KnowledgeBase document, Digital Filtering with M Series and CompactDAQ, for more information about digital filters and counters. To access this KnowledgeBase, go to ni.com/info and enter the info code rddfms. NI 6238/6239 User Manual 10-10 ni.
11 Bus Interface The bus interface circuitry of NI 6238/6239 devices efficiently moves data between host memory and the measurement and acquisition circuits. NI 6238/6239 devices are available for the following platforms. • PCI • PXI NI 6238/6239 devices are jumperless for complete plug-and-play operation. The operating system automatically assigns the base address, interrupt levels, and other resources.
Chapter 11 Bus Interface Each DMA controller supports packing and unpacking of data through the FIFOs to connect different size devices and optimize PCI bus utilization and automatically handles unaligned memory buffers. PXI Considerations Note PXI clock and trigger signals are only available on PXI devices. Other devices use RTSI.
Chapter 11 Bus Interface Using PXI with CompactPCI Using PXI-compatible products with standard CompactPCI products is an important feature provided by PXI Hardware Specification Revision 2.1. If you use a PXI-compatible plug-in module in a standard CompactPCI chassis, you cannot use PXI-specific functions, but you can still use the basic plug-in device functions. For example, the RTSI bus on a PXI M Series device is available in a PXI chassis, but not in a CompactPCI chassis.
Chapter 11 Bus Interface Interrupt Request (IRQ) IRQ transfers rely on the CPU to service data transfer requests. The device notifies the CPU when it is ready to transfer data. The data transfer speed is tightly coupled to the rate at which the CPU can service the interrupt requests. If you are using interrupts to transfer data at a rate faster than the rate the CPU can service the interrupts, your systems may start to freeze.
12 Triggering A trigger is a signal that causes an action, such as starting or stopping the acquisition of data. When you configure a trigger, you must decide how you want to produce the trigger and the action you want the trigger to cause. NI 6238/6239 devices support internal software triggering, as well as external digital triggering.
Chapter 12 Triggering You also can program your DAQ device to perform an action in response to a trigger from a digital source. The action can affect the following. NI 6238/6239 User Manual • Analog input acquisition • Analog output generation • Counter behavior 12-2 ni.
A Device-Specific Information This appendix contains device pinouts, specifications, cable and accessory choices, and other information for the NI 6238 and NI 6239 M Series isolated devices. To obtain documentation for devices not listed here, refer to ni.com/manuals. NI 6238 NI 6238 Pinout Figure A-1 shows the pinout of the NI 6238. For a detailed description of each signal, refer to the I/O Connector Signal Descriptions section of Chapter 3, Connector Information.
Appendix A Device-Specific Information AI 0– AI 1+ AI 2+ AI 3– AI GND AI 4– AI 5+ AI 6+ AI 7+ AO POWER SUPPLY AO 0 AO GND PFI 1/P0.1 (Input) PFI 2/P0.2 (Input) PFI 4/P0.4 (Input) P1.VCC PFI 7/P1.1 (Output) PFI 9/P1.3 (Output) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 AI 0+/CAL+ AI 1– AI GND AI 2– AI 3+ AI 4+ AI 5– CAL– AI 6– AI 7– NC AO 1 PFI 0/P0.0 (Input) P0.GND PFI 3/P0.3 (Input) PFI 5/P0.5 (Input) PFI 6/P1.0 (Output) PFI 8/P1.
Appendix A Device-Specific Information Table A-1. NI 6238 Device Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) Port CTR 1 OUT 36 (PFI 7) P1.1 CTR 1 A 15 (PFI 3) P0.3 CTR 1 Z 34 (PFI 4) P0.4 CTR 1 B 16 (PFI 5) P0.5 Note For more information about default NI-DAQmx counter inputs, refer to Connecting Counter Signals in the NI-DAQmx Help or the LabVIEW 8.x Help.
Appendix A Device-Specific Information vision, and motion devices. Since PXI devices use PXI backplane signals for timing and synchronization, no cables are required. Cables In most applications, you can use the following cables: • SH37F-37M-x—37-pin female-to-male shielded I/O cable, UL Listed derated to 30 Vrms, 42.
Appendix A AI 0– AI 1+ AI 2+ AI 3– AI GND AI 4– AI 5+ AI 6+ AI 7+ AO POWER SUPPLY AO 0 AO GND PFI 1/P0.1 (Input) PFI 2/P0.2 (Input) PFI 4/P0.4 (Input) P1.GND PFI 7/P1.1 (Output) PFI 9/P1.3 (Output) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Device-Specific Information AI 0+/CAL+ AI 1– AI GND AI 2– AI 3+ AI 4+ AI 5– CAL– AI 6– AI 7– NC AO 1 PFI 0/P0.0 (Input) P0.GND PFI 3/P0.3 (Input) PFI 5/P0.5 (Input) PFI 6/P1.0 (Output) PFI 8/P1.
Appendix A Device-Specific Information Table A-2. NI 6239 Device Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) Port CTR 1 OUT 36 (PFI 7) P1.1 CTR 1 A 15 (PFI 3) P0.3 CTR 1 Z 34 (PFI 4) P0.4 CTR 1 B 16 (PFI 5) P0.5 Note For more information about default NI-DAQmx counter inputs, refer to Connecting Counter Signals in the NI-DAQmx Help or the LabVIEW 8.x Help.
Appendix A Device-Specific Information vision, and motion devices. Since PXI devices use PXI backplane signals for timing and synchronization, no cables are required. Cables In most applications, you can use the following cables: • SH37F-37M-x—37-pin female-to-male shielded I/O cable, UL Listed derated to 30 Vrms, 42.
B Troubleshooting This section contains some common questions about M Series devices. If your questions are not answered here, refer to the National Instruments KnowledgeBase at ni.com/kb. It contains thousands of documents that answer frequently asked questions about NI products. Analog Input I am seeing crosstalk when sampling multiple channels.
Appendix B Troubleshooting In an isolated device, leaving the AI GND terminal unconnected will cause the signal to drift and eventually rail. How can I use the AI Sample Clock and AI Convert Clock signals on an M Series device to sample the AI channel(s)? M Series devices use ai/SampleClock and ai/ConvertClock to perform interval sampling.
Appendix B Troubleshooting Counters When multiple sample clocks on my buffered counter measurement occur before consecutive edges on my source, I see weird behavior. Why? Duplicate count prevention ensures that the counter returns correct data for counter measurement in some applications where a slow or non-periodic external source is used. Refer to the Duplicate Count Prevention section of Chapter 7, Counters, for more information.
Technical Support and Professional Services C Visit the following sections of the National Instruments Web site at ni.com for technical support and professional services: • Support—Online technical support resources at ni.
Appendix C Technical Support and Professional Services • Calibration Certificate—If your product supports calibration, you can obtain the calibration certificate for your product at ni.com/calibration. If you searched ni.com and could not find the answers you need, contact your local office or NI corporate headquarters. Phone numbers for our worldwide offices are listed at the front of this manual. You also can visit the Worldwide Offices section of ni.
Glossary Numbers/Symbols % Percent. + Positive of, or plus. – Negative of, or minus. ± Plus or minus. < Less than. > Greater than. ≤ Less than or equal to. ≥ Greater than or equal to. / Per. º Degree. Ω Ohm. A A Amperes—the unit of electric current. A/D Analog-to-Digital. Most often used as A/D converter. AC Alternating current. accuracy A measure of the capability of an instrument or sensor to faithfully indicate the value of the measured signal.
Glossary AI 1. Analog input. 2. Analog input channel signal. AI GND Analog input ground signal. AI SENSE Analog input sense signal. analog A signal whose amplitude can have a continuous range of values. analog input signal An input signal that varies smoothly over a continuous range of values, rather than in discrete steps. analog output signal An output signal that varies smoothly over a continuous range of values, rather than in discrete steps.
Glossary ASIC Application-specific integrated circuit—A proprietary semiconductor component designed and manufactured to perform a set of specific functions for a specific customer. asynchronous 1. Hardware—A property of an event that occurs at an arbitrary time, without synchronization to a reference clock. 2. Software—A property of a function that begins an operation and returns prior to the completion or termination of the operation. B b Bit—One binary digit, either 0 or 1.
Glossary cascading Process of extending the counting range of a counter chip by connecting to the next higher counter. CE European emissions control standard. channel Pin or wire lead to which you apply or from which you read the analog or digital signal. For digital signals, you group channels to form ports. Ports usually consist of either four or eight digital channels. clock Hardware component that controls timing for reading from or writing to groups.
Glossary counter 1. Software. A memory location used to store a count of certain occurrences. 2. Hardware. A circuit that counts events. When it refers to an instrument, it refers to a frequency counter. counter/timer A circuit that counts external pulses or clock pulses (timing). D D GND Digital ground signal. D-SUB connector A serial connector.
Glossary data transfer A technique for moving digital data from one system to another. Options for data transfer are DMA, interrupt, and programmed I/O. For programmed I/O transfers, the CPU in the PC reads data from the DAQ device whenever the CPU receives a software signal to acquire a single data point. Interrupt-based data transfers occur when the DAQ device sends an interrupt to the CPU, telling the CPU to read the acquired data from the DAQ device.
Glossary digital signal A representation of information by a set of discrete values according to a prescribed law. These values are represented by numbers. digital trigger A TTL level signal having two discrete levels—a high and a low level. DIO Digital input/output. DMA Direct Memory Access—A method by which data can be transferred to/ from computer memory from/to a device or memory on the bus while the processor does something else.
Glossary F FIFO First-In-First-Out memory buffer—A data buffering technique that functions like a shift register where the oldest values (first in) come out first. Many DAQ products and instruments use FIFOs to buffer digital data from an A/D converter, or to buffer the data before or after bus transmission. The first data stored is the first data sent to the acceptor. FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be retrieved or output.
Glossary ft Feet. function 1. A built-in execution element, comparable to an operator, function, or statement in a conventional language. 2. A set of software instructions executed by a single line of code that may have input and/or output parameters and returns a value when executed. G glitch An unwanted signal excursion of short duration that is usually unavoidable. GND See ground. ground 1. A pin. 2. An electrically neutral wire that has the same potential as the surrounding earth.
Glossary impedance 1. The electrical characteristic of a circuit expressed in ohms and/or capacitance/inductance. 2. Resistance. in. Inch or inches. instrument driver A set of high-level software functions that controls a specific GPIB, VXI, or RS232 programmable instrument or a specific plug-in DAQ device. Instrument drivers are available in several forms, ranging from a function callable language to a virtual instrument (VI) in LabVIEW.
Glossary K kHz Kilohertz—A unit of frequency; 1 kHz = 103 = 1,000 Hz. kS 1,000 samples. L LabVIEW A graphical programming language. LED Light-Emitting Diode—A semiconductor light source. lowpass filter A filter that passes signals below a cutoff frequency while blocking signals above that frequency. LSB Least Significant Bit. M m Meter. M Series An architecture for instrumentation-class, multichannel data acquisition devices based on the earlier E Series architecture with added new features.
Glossary MITE MXI Interface To Everything—A custom ASIC designed by National Instruments that implements the PCI bus interface. The MITE supports bus mastering for high-speed data transfers over the PCI bus. module A board assembly and its associated mechanical parts, front panel, optional shields, and so on. A module contains everything required to occupy one or more slots in a mainframe. SCXI and PXI devices are modules.
Glossary NI-PGIA See instrumentation amplifier. non-referenced signal sources Signal sources with voltage signals that are not connected to an absolute reference or system ground. Also called floating signal sources. Some common example of non-referenced signal sources are batteries, transformers, or thermocouples.
Glossary power source An instrument that provides one or more sources of AC or DC power. Also known as power supply. ppm Parts per million. pretriggering The technique used on a DAQ device to keep a continuous buffer filled with data, so that when the trigger conditions are met, the sample includes the data leading up to the trigger condition. pulse A signal whose amplitude deviates from zero for a short period of time.
Glossary real time 1. Displays as it comes in; no delays. 2. A property of an event or system in which data is processed and acted upon as it is acquired instead of being accumulated and processed at a later time. 3. Pertaining to the performance of a computation during the actual time that the related physical process transpires so results of the computation can be used in guiding the physical process.
Glossary SCXI Signal Conditioning eXtensions for Instrumentation—The National Instruments product line for conditioning low-level signals within an external chassis near sensors so that only high-level signals are sent to DAQ devices in the noisy PC environment. sensor A device that responds to a physical stimulus (heat, light, sound, pressure, motion, flow, and so on), and produces a corresponding electrical signal. Primary characteristics of sensors are sensitivity, frequency range, and linearity.
Glossary source impedance A parameter of signal sources that reflects current-driving ability of voltage sources (lower is better) and the voltage-driving ability of current sources (higher is better). synchronous 1. Hardware—A property of an event that is synchronized to a reference clock. 2. Software—A property of a function that begins an operation and returns only when the operation is complete. A synchronous process is, therefore, locked and no other processes can run during this time.
Glossary trigger 1. Any event that causes or starts some form of data capture. 2. An external stimulus that initiates one or more instrument functions. Trigger stimuli include a front panel button, an external input voltage pulse, or a bus trigger command. The trigger may also be derived from attributes of the actual signal to be acquired, such as the level and slope of the signal. tsc Source clock period. tsp Source pulse width.
Glossary Vs Signal source voltage. virtual channel See channel. W waveform 1. The plot of the instantaneous amplitude of a signal as a function of time. 2. Multiple voltage readings taken at a specific sampling rate.
Index Symbols ai/PauseTrigger, 4-24 ai/ReferenceTrigger, 4-22 ai/SampleClock, 4-15 ai/SampleClockTimebase, 4-17 ai/StartTrigger, 4-21 analog input analog-to-digital converter, 4-2 charge injection, B-1 circuitry, 4-1 crosstalk when sampling multiple channels, B-1 data acquisition methods, 4-10 differential, troubleshooting, B-1 FIFO, 4-2 getting started with applications in software, 4-25 ground-reference settings, 4-5 I/O connector, 4-1 instrumentation amplifier, 4-1 MUX, 4-1 NI-PGIA, 4-1 range, 4-2 sampl
Index C triggering, 5-4 troubleshooting, B-2 ANSI C documentation, xvii AO FIFO, 5-1 AO Pause Trigger signal, 5-6 AO Sample Clock signal, 5-8 AO Sample Clock Timebase signal, 5-9 AO Start Trigger signal, 5-5 ao/PauseTrigger, 5-6 ao/SampleClock, 5-8 ao/SampleClockTimebase, 5-9 ao/StartTrigger, 5-5 applications counter input, 7-3 counter output, 7-21 edge counting, 7-3 arm start trigger, 7-32 avoiding scanning faster than necessary, 4-9 cables, 2-4, A-3, A-6 choosing for your device, 1-2 custom, 2-4 calibr
Index single pulse generation with start trigger, 7-21 synchronization modes, 7-38 timing signals, 7-26 triggering, 7-32 troubleshooting, B-3 counting edges, 7-3 crosstalk when sampling multiple channels, B-1 current connecting analog input signals, 4-3 connecting analog output, 5-4 custom cabling, 2-4 conventions used in the manual, xiii Counter n A signal, 7-29 Counter n Aux signal, 7-28 Counter n B signal, 7-29 Counter n Gate signal, 7-28 Counter n HW Arm signal, 7-29 Counter n Internal Output signal,
Index enabling duplicate count prevention in NI-DAQmx, 7-38 encoders, quadrature, 7-16 encoding X1, 7-16 X2, 7-17 X4, 7-17 equivalent time sampling, 7-25 examples (NI resources), C-1 exporting timing output signals using PFI terminals, 8-3 external reference clock, 10-2 source mode, 7-40 digital input and output, 6-1 isolation, 9-3 isolators, 9-1 routing, 10-1 signals, connecting, 6-2, 8-6 source, triggering, 12-1 digital I/O circuitry, 6-1 connecting signals, 6-2, 8-6 getting started with applications in
Index interrupt request, as a transfer method, 11-4 IRQ as a transfer method, 11-4 changing data transfer methods, 11-4 isolated DAQ devices, 9-1 benefits, 9-3 common-mode noise, 9-3 isolation barrier, 4-2, 5-2 isolators, 9-1 non-buffered hardware-timed, 5-3 pulse for ETS, 7-25 pulse train, 7-23 retriggerable single pulse, 7-22 simple pulse, 7-21 single pulse, 7-21 single pulse with start trigger, 7-21 software-timed, 5-2 getting started, 1-1 AI applications in software, 4-25 AO applications in software,
Index O using quadrature encoders, 7-16 using two pulse encoders, 7-18 measuring high frequency with two counters, 7-12 large range of frequencies using two counters, 7-13 low frequency with one counter, 7-10 averaged, 7-11 methods, data transfer, 11-3 minimizing output signal glitches (troubleshooting), B-2 multichannel scanning considerations, 4-8 multiple device synchronization, 10-3 other internal source mode, 7-39 other software, 1-1 output signals, glitches (troubleshooting), B-2 outputs, using RTS
Index S pulse-width measurement, 7-6 buffered, 7-6 single, 7-6 PXI and PXI Express, 11-2 clock, 11-2 clock and trigger signals, 10-7 considerations, 11-2 trigger signals, 11-2 triggers, 10-8 using with CompactPCI, 11-3 PXI Express chassis compatibility, 11-2 PXI_CLK10, 10-8 PXI_STAR filters, 10-8 trigger, 10-8 sample clock edge counting, 7-4 scanning speed, 4-9 semi-period measurement, 7-9 buffered, 7-10 single, 7-9 sensors, 2-3 settings, analog input ground-reference, 4-5 short high-quality cabling, 4-8
Index synchronizing multiple devices, 10-3 synchronous counting mode, 7-35 Counter n Z, 7-29 counter timing, 7-26 counters, 7-26 exporting timing output using PFI terminals, 8-3 FREQ OUT, 7-30 Frequency Output, 7-30 minimizing output glitches, B-2 simple pulse generation, 7-21 single period measurement, 7-8 pulse generation, 7-21 retriggerable, 7-22 with start trigger, 7-21 pulse-width measurement, 7-6 semi-period measurement, 7-9 two-signal edge-separation measurement, 7-19 software configuring AI ground
Index U W using PFI terminals as static digital I/Os, 8-3 as timing input, 8-2 to export timing output signals, 8-3 using RTSI as outputs, 10-5 terminals as timing input signals, 10-6 using short high-quality cabling, 4-8 waveform generation signals, 5-5 Web resources, C-1 wiring, field, 4-11 X X1 encoding, 7-16 X2 encoding, 7-17 X4 encoding, 7-17 V V-I Converter, 5-1 © National Instruments Corporation I-9 NI 6238/6239 User Manual
