DAQ M Series NI 6232/6233 User Manual NI 6232/6233 User Manual July 2006 371995A-01
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Important Information Warranty The NI 6232/6233 is warranted against defects in materials and workmanship for a period of three years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
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Contents About This Manual Conventions ...................................................................................................................xv Related Documentation..................................................................................................xvi NI-DAQ...........................................................................................................xvi NI-DAQmx for Linux......................................................................................
Contents Chapter 3 Connector Information I/O Connector Signal Descriptions................................................................................ 3-1 RTSI Connector Pinout ................................................................................................. 3-3 Chapter 4 Analog Input Analog Input Circuitry .................................................................................................. 4-1 Analog Input Range............................................................
Contents Using an External Source..................................................................4-23 Routing AI Sample Clock Signal to an Output Terminal .................4-23 Other Timing Requirements..............................................................4-23 AI Sample Clock Timebase Signal..................................................................4-24 AI Convert Clock Signal .................................................................................4-25 Using an Internal Source....
Contents AO Sample Clock Signal ................................................................................ 5-8 Using an Internal Source .................................................................. 5-9 Using an External Source ................................................................. 5-9 Routing AO Sample Clock Signal to an Output Terminal ............... 5-9 Other Timing Requirements ............................................................. 5-9 AO Sample Clock Timebase Signal.......
Contents Position Measurement .....................................................................................7-16 Measurements Using Quadrature Encoders......................................7-16 Measurements Using Two Pulse Encoders .......................................7-18 Two-Signal Edge-Separation Measurement....................................................7-19 Single Two-Signal Edge-Separation Measurement ..........................7-19 Buffered Two-Signal Edge-Separation Measurement ........
Contents Prescaling ........................................................................................................ 7-34 Duplicate Count Prevention ............................................................................ 7-35 Duplicate Count Prevention Example .............................................. 7-35 Duplicate Count Example................................................................. 7-36 Example Application That Prevents Duplicate Count......................
Contents Using RTSI Terminals as Timing Input Signals .............................................10-6 RTSI Filters .....................................................................................................10-6 PXI Clock and Trigger Signals ......................................................................................10-8 PXI_CLK10.....................................................................................................10-8 PXI Triggers .......................................
About This Manual The NI 6232/6233 User Manual contains information about using the National Instruments 6232/6233 M Series data acquisition (DAQ) devices with NI-DAQmx 8.0 and later. NI 6232/6233 devices feature eight analog input (AI) channels, four analog output (AO) channels, two counters, six lines of digital input (DI), and four lines of digital output (DO).
About This Manual monospace Text in this font denotes text or characters that you should enter from the keyboard, sections of code, programming examples, and syntax examples. This font is also used for the proper names of disk drives, paths, directories, programs, subprograms, subroutines, device names, functions, operations, variables, filenames, and extensions.
About This Manual The NI-DAQmx for Linux Configuration Guide provides configuration instructions, templates, and instructions for using test panels. Note All NI-DAQmx documentation for Linux is installed at /usr/local/ natinst/nidaqmx/docs. NI-DAQmx Base The NI-DAQmx Base Getting Started Guide describes how to install your NI-DAQmx Base software, your NI-DAQmx Base-supported DAQ device, and how to confirm that your device is operating properly.
About This Manual • Getting Started»Getting Started with DAQ—Includes overview information and a tutorial to learn how to take an NI-DAQmx measurement in LabVIEW using the DAQ Assistant. • VI and Function Reference»Measurement I/O VIs and Functions—Describes the LabVIEW NI-DAQmx VIs and properties.
About This Manual .NET and Visual C++ class libraries. This help collection is integrated into the Visual Studio .NET documentation. In Visual Studio .NET, select Help»Contents. Note You must have Visual Studio .NET installed to view the NI Measurement Studio Help. Device Documentation and Specifications The NI 6232/6233 Specifications contains all specifications for NI 6232/6233 M Series devices. NI-DAQ 7.
1 Getting Started M Series NI 6232/6233 devices feature sixteen analog input (AI) channels, two analog output (AO) channels, two counters, six lines of digital input (DI), and four lines of digital output (DO). If you have not already installed your device, refer to the DAQ Getting Started Guide. For NI 6232/6233 device specifications, refer to the NI 6232/6233 Specifications on ni.com/manuals. Before installing your DAQ device, you must install the software you plan to use with the device.
Chapter 1 Getting Started Device Specifications Refer to the NI 6232/6233 Specifications, available on the NI-DAQ Device Document Browser or ni.com/manuals, for more detailed information on the NI 6232/6233 device. Device Accessories and Cables NI offers a variety of accessories and cables to use with your DAQ device. Refer to Appendix A, Device-Specific Information, or ni.com for more information. NI 6232/6233 User Manual 1-2 ni.
2 DAQ System Overview Figure 2-1 shows a typical DAQ system, which includes sensors, transducers, cables that connect the various devices to the accessories, the M Series device, programming software, and a PC. The following sections cover the components of a typical DAQ system. Sensors and Transducers Cables and Accessories DAQ Hardware DAQ Software Personal Computer Figure 2-1.
Chapter 2 DAQ System Overview A Isolation Barrier Analog Input I/O Connector AI GND A Digital Routing and Clock Generation Analog Output AO GND A Bus Interface Bus Digital Isolators Counters RTSI PFI/Static DI P0.GND P0 PFI/Static DO P1 P1.GND Figure 2-2. General NI 6232/6233 Block Diagram DAQ-STC2 The DAQ-STC2 implements a high-performance digital engine for NI 6232/6233 data acquisition hardware.
Chapter 2 DAQ System Overview Calibration Circuitry The M Series analog inputs and outputs have calibration circuitry to correct gain and offset errors. You can calibrate the device to minimize AI and AO errors caused by time and temperature drift at run time. No external circuitry is necessary; an internal reference ensures high accuracy and stability over time and temperature changes. Factory-calibration constants are permanently stored in an onboard EEPROM and cannot be modified.
Chapter 2 DAQ System Overview Cables and Accessories NI offers a variety of products to use with NI 6232/6233 devices, including cables, connector blocks, and other accessories, as follows: • Cables and cable assemblies – Shielded – Unshielded ribbon • Screw terminal connector blocks, shielded and unshielded • RTSI bus cables For more specific information about these products, refer to ni.com.
Chapter 2 DAQ System Overview Programming Devices in Software National Instruments measurement devices are packaged with NI-DAQ driver software, an extensive library of functions and VIs you can call from your application software, such as LabVIEW or LabWindows/CVI, to program all the features of your NI measurement devices. Driver software has an application programming interface (API), which is a library of VIs, functions, classes, attributes, and properties for creating applications for your device.
3 Connector Information The I/O Connector Signal Descriptions and RTSI Connector Pinout sections contain information on M Series connectors. Refer to Appendix A, Device-Specific Information, for device I/O connector pinouts. I/O Connector Signal Descriptions Table 3-1 describes the signals found on the I/O connectors. Not all signals are available on all devices. Table 3-1.
Chapter 3 Connector Information Table 3-1. I/O Connector Signals (Continued) Signal Name AO GND Reference Direction — — Description Analog Output Ground—AO GND is the reference for AO <0..1>. AI GND and AO GND are connected on the device. Note: AI GND and AO GND are isolated from earth ground, chassis ground, P0.GND, and P1.GND. PFI <0..5>/P0.<0..5> P0.
Chapter 3 Connector Information RTSI Connector Pinout Refer to the RTSI Connector Pinout section of Chapter 10, Digital Routing and Clock Generation, for information on the RTSI connector.
4 Analog Input Figure 4-1 shows the analog input circuitry of NI 6232/6233 devices. I/O Connector Isolation Barrier AI <0..n> Mux DIFF, RSE, or NRSE NI-PGIA ADC Digital Isolators AI FIFO AI Data Input Range Selection AI GND AI Terminal Configuration Selection Figure 4-1. NI 6232/6233 Analog Input Circuitry Analog Input Circuitry I/O Connector You can connect analog input signals to the M Series device through the I/O connector.
Chapter 4 Analog Input Ground-Reference Settings The analog input ground-reference settings circuitry selects between differential and referenced single-ended modes. Each AI channel can use a different mode. Instrumentation Amplifier (NI-PGIA) The NI programmable gain instrumentation amplifier (PGIA) is a measurement and instrument class amplifier that minimizes settling times for all input ranges. The NI-PGIA can amplify or attenuate an AI signal to ensure that you use the maximum resolution of the ADC.
Chapter 4 Analog Input 16-bit ADC converts analog inputs into one of 65,536 (= 216) codes—that is, one of 65,536 possible digital values. These values are spread fairly evenly across the input range. So, for an input range of –10 V to 10 V, the voltage of each code of a 16-bit ADC is: (10 V – (–10 V)) = 305 mV 216 M Series devices use a calibration method that requires some codes (typically about 5% of the codes) to lie outside of the specified range.
Chapter 4 Analog Input Table 4-2. Analog Input Ground-Reference Settings AI Ground-Reference Settings Description DIFF In differential (DIFF) mode, the NI 6232/6233 device measures the difference in voltage between two AI signals. AI GND is the bias current return point for DIFF mode. RSE In referenced single-ended (RSE) mode, the NI 6232/6233 device measures the voltage of an AI signal relative to AI GND, which is isolated from earth/chassis ground.
Chapter 4 Analog Input Table 4-3 shows how signals are routed to the NI-PGIA. Table 4-3. Signals Routed to the NI-PGIA AI Ground-Reference Settings Signals Routed to the Positive Input of the NI-PGIA (Vin+) Signals Routed to the Negative Input of the NI-PGIA (Vin–) RSE and NRSE AI <0..15> AI GND DIFF AI <0..7> AI <8..15> For differential measurements, AI 0 and AI 8 are the positive and negative inputs of differential analog input channel 0.
Chapter 4 Analog Input Figure 4-3. Enabling Multimode Scanning in LabVIEW Multichannel Scanning Considerations M Series devices can scan multiple channels at high rates and digitize the signals accurately. However, you should consider several issues when designing your measurement system to ensure the high accuracy of your measurements. In multichannel scanning applications, accuracy is affected by settling time.
Chapter 4 Analog Input Settling times increase when scanning high-impedance signals due to a phenomenon called charge injection. Multiplexers contain switches, usually made of switched capacitors. When one of the channels, for example channel 0, is selected in a multiplexer, those capacitors accumulate charge. When the next channel, for example channel 1, is selected, the accumulated charge leaks backward through channel 1.
Chapter 4 Analog Input 1/50 LSB) of the ±10 V range. Some devices can take many microseconds for the circuitry to settle this much. To avoid this effect, you should arrange your channel scanning order so that transitions from large to small input ranges are infrequent. In general, you do not need this extra settling time when the PGIA is switching from a small input range to a larger input range.
Chapter 4 Analog Input Avoid Scanning Faster Than Necessary Designing your system to scan at slower speeds gives the PGIA more time to settle to a more accurate level. Here are two examples to consider. Example 1 Averaging many AI samples can increase the accuracy of the reading by decreasing noise effects. In general, the more points you average, the more accurate the final result will be. However, you may choose to decrease the number of points you average and slow down the scanning rate.
Chapter 4 Analog Input each ADC conversion. In NI-DAQmx, software-timed acquisitions are referred to as having on-demand timing. Software-timed acquisitions are also referred to as immediate or static acquisitions and are typically used for reading a single sample of data. Hardware-Timed Acquisitions With hardware-timed acquisitions, a digital hardware signal (ai/SampleClock) controls the rate of the acquisition. This signal can be generated internally on your device or provided externally.
Chapter 4 Analog Input be transferred to host memory. The device generates an error in this case. With continuous operations, if the user program does not read data out of the PC buffer fast enough to keep up with the data transfer, the buffer could reach an overflow condition, causing an error to be generated. Non-Buffered In non-buffered acquisitions, data is read directly from the FIFO on the device.
Chapter 4 Analog Input Table 4-4.
Chapter 4 Analog Input two reference planes. Isolated front ends require a ground-reference point to the signal that is being measured. Floating Signal Sources A floating signal source is not connected to the building ground system (earth or chassis ground), but has an isolated ground-reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolators, and isolation amplifiers.
Chapter 4 Analog Input Use DIFF input connections for any channel that meets any of the following conditions: • The input signal is low level (less than 1 V). • The leads connecting the signal to the device are greater than 3 m (10 ft). • The input signal requires a separate ground-reference point or return signal. • The signal leads travel through noisy environments. DIFF signal connections reduce noise pickup and increase common-mode noise rejection.
Chapter 4 Analog Input With this type of connection, the PGIA rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the device ground, shown as Vcm in the figure. Refer to the NI 6232/6233 Specifications for the usable range of Vcm.
Chapter 4 Analog Input AI + Isolation Barrier Floating Signal Source + Vs + Instrumentation Amplifier – PGIA AI – + Measured Vm Voltage – Digital Isolators – Input Multiplexers AI GND I/O Connector M Series Isolated Device Configured in DIFF Mode Figure 4-5. Differential Connections for Floating Signal Sources This figure shows AI GND connected to the ground reference point for the floating signal source.
Chapter 4 Analog Input signal connects to the positive input of the PGIA, and the ground connects to the negative input of the PGIA. You should only use single-ended input connections if the input signal meets the following conditions. • The input signal is high-level (greater than 1 V). • The leads connecting the signal to the device are less than 3 m (10 ft). • The input signal can share a common reference point with other signals.
Chapter 4 Analog Input Isolation Barrier AI <0..n> Floating or Grounded Signal Source Vs Programmable Gain Instrumentation Amplifier + + – – PGIA Input Multiplexers AI GND Vcm Vm + Measured Voltage – Digital Isolators I/O Connector Selected Channel in RSE or NRSE Configuration Figure 4-6. Single-Ended Connections for Floating Signal Sources (RSE Configuration) Refer to the NI 6232/6233 Specifications for the usable range of Vcm.
Chapter 4 • Analog Input Use individually shielded, twisted-pair wires to connect AI signals to the device. With this type of wire, the signals attached to the positive and negative input channels are twisted together and then covered with a shield. You then connect this shield only at one point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference.
Chapter 4 Analog Input 1/Sample Period = Sample Rate Channel 0 Channel 1 Convert Period Sample Period Figure 4-8. Interval Sampling ai/ConvertClock controls the Convert Period, which is determined by the following equation: 1/Convert Period = Convert Rate By default, the NI-DAQmx driver chooses the fastest Channel Clock rate possible while still allowing extra time for adequate amplifier settling time.
Chapter 4 Analog Input the PCI-6220 M Series device, a sampling rate of 40 kHz for two channels would result in a Convert Clock rate of 80 kHz. Maximum settling time for the amplifier is also very important. For example, to ensure accuracy to within ± 1 LSB on an NI 623x M Series device, the device requires a minimum amplifier settling time of 6 μs even though the maximum channel conversion rate is 4 μs. Higher source impedance also increases amplifier settling time.
Chapter 4 Analog Input ai/StartTrigger ai/ReferenceTrigger n/a ai/SampleClock ai/ConvertClock Scan Counter 3 2 1 0 2 2 2 1 0 Figure 4-10. Pretriggered Data Acquisition Example If an ai/ReferenceTrigger pulse occurs before the specified number of pretrigger samples are acquired, the trigger pulse is ignored. Otherwise, when the ai/ReferenceTrigger pulse occurs, the sample counter value decrements until the specified number of posttrigger samples have been acquired.
Chapter 4 Analog Input Using an Internal Source One of the following internal signals can drive ai/SampleClock. • Counter n Internal Output • AI Sample Clock Timebase (divided down) • A software pulse A programmable internal counter divides down the sample clock timebase. Several other internal signals can be routed to ai/SampleClock through RTSI. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information.
Chapter 4 Analog Input A counter on your device internally generates ai/SampleClock unless you select some external source. ai/StartTrigger starts this counter and either software or hardware can stop it when a finite acquisition completes. When using an internally generated ai/SampleClock, you also can specify a configurable delay from ai/StartTrigger to the first ai/SampleClock pulse. By default, this delay is set to two ticks of the ai/SampleClockTimebase signal.
Chapter 4 Analog Input sources for ai/SampleClock. You can configure the polarity selection for ai/SampleClockTimebase as either rising or falling edge. AI Convert Clock Signal Use the AI Convert Clock (ai/ConvertClock) signal to initiate a single A/D conversion on a single channel. A sample, controlled by the AI Sample Clock, consists of one or more conversions. You can specify either an internal or external signal as the source of ai/ConvertClock.
Chapter 4 Analog Input Using an External Source Use one of the following external signals as the source of ai/ConvertClock: • Input PFI <0..5> • RTSI <0..7> • PXI_STAR Routing AI Convert Clock Signal to an Output Terminal You can route ai/ConvertClock (as an active low signal) out to any output PFI <6..9> or RTSI <0..7> terminal. PFI <0..5> terminals are fixed inputs. PFI <6..9> terminals are fixed outputs.
Chapter 4 Analog Input Other Timing Requirements The sample and conversion level timing of M Series devices work such that clock signals are gated off unless the proper timing requirements are met. For example, the device ignores both ai/SampleClock and ai/ConvertClock until it receives a valid ai/StartTrigger signal. When the device recognizes an ai/SampleClock pulse, it ignores subsequent ai/SampleClock pulses until it receives the correct number of ai/ConvertClock pulses.
Chapter 4 Analog Input ai/ConvertClockTimebase is not available as an output on the I/O connector. AI Hold Complete Event Signal The AI Hold Complete Event (ai/HoldCompleteEvent) signal generates a pulse after each A/D conversion begins. You can route ai/HoldCompleteEvent out to any output PFI <6..9> or RTSI <0..7> terminal.
Chapter 4 Analog Input You also can specify whether the measurement acquisition begins on the rising edge or falling edge of ai/StartTrigger. Routing AI Start Trigger to an Output Terminal You can route ai/StartTrigger out to any output PFI <6..9> or RTSI <0..7> terminal. The output is an active high pulse. The device also uses ai/StartTrigger to initiate pretriggered DAQ operations. In most pretriggered applications, a software trigger generates ai/StartTrigger.
Chapter 4 Analog Input Reference Trigger Pretrigger Samples Posttrigger Samples Complete Buffer Figure 4-14. Reference Trigger Final Buffer Using a Digital Source To use ai/ReferenceTrigger with a digital source, specify a source and an edge. The source can be any of the following signals: • Input PFI <0..5> • RTSI <0..7> • PXI_STAR The source also can be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.
Chapter 4 Analog Input Using a Digital Source To use ai/SampleClock, specify a source and a polarity. The source can be any of the following signals: • Input PFI <0..5> • RTSI <0..7> • PXI_STAR The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information. Routing AI Pause Trigger Signal to an Output Terminal You can route ai/PauseTrigger out to RTSI <0..7>.
5 Analog Output NI 6232/6233 devices have two AO channels that are controlled by a single clock and are capable of waveform generation. Figure 5-1 shows the analog output circuitry of NI 6232/6233 devices. Isolation Barrier AO 0 DAC0 Digital Isolators AO 1 AO FIFO AO Data DAC1 AO Sample Clock Figure 5-1. NI 6232/6233 Analog Output Circuitry Analog Output Circuitry DACs Digital-to-analog converters (DACs) convert digital codes to analog voltages.
Chapter 5 Analog Output DACs. It allows you to download the points of a waveform to your M Series device without host computer interaction. AO Sample Clock The AO Sample Clock signal reads a sample from the DAC FIFO and generates the AO voltage. Isolation Barrier and Digital Isolators The digital isolators across the isolation barrier provide a ground break between the isolated analog front end and the earth/chassis/building ground.
Chapter 5 Analog Output Hardware-Timed Generations With a hardware-timed generation, a digital hardware signal controls the rate of the generation. This signal can be generated internally on your device or provided externally. Hardware-timed generations have several advantages over software-timed acquisitions: • The time between samples can be much shorter. • The timing between samples can be deterministic. • Hardware-timed acquisitions can use hardware triggering.
Chapter 5 Analog Output Regeneration is the repetition of the data that is already in the buffer. Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out. New data can be written to the PC buffer at any time without disrupting the output. With FIFO regeneration, the entire buffer is downloaded to the FIFO and regenerated from there. When the data is downloaded, new data cannot be written to the FIFO.
Chapter 5 AO 0 + Load Analog Output Channel 0 V OUT – Digital Isolators – Load V OUT AO 1 Channel 1 Isolation Barrier + I/O Connector AO GND Figure 5-2. Analog Output Connections Analog Output Timing Signals Figure 5-3 summarizes all of the timing options provided by the analog output timing engine.
Chapter 5 Analog Output PFI, RTSI PXI_STAR PFI, RTSI Ctr n Internal Output ao/Sample Clock Timebase PXI_STAR ao/Sample Clock Programmable Clock Divider 20 MHz Timebase 100 kHz Timebase PXI_CLK10 Figure 5-3. Analog Output Timing Options NI 6232/6233 devices feature the following AO (waveform generation) timing signals.
Chapter 5 Analog Output The source also can be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW 8.x Help for more information. You also can specify whether the waveform generation begins on the rising edge or falling edge of ao/StartTrigger. Routing AO Start Trigger Signal to an Output Terminal You can route ao/StartTrigger out to any output PFI <6..9> or RTSI <0..7> terminal. The output is an active high pulse. PFI <0..
Chapter 5 Analog Output deasserted and another edge of the sample clock is received, as shown in Figure 5-5. Pause Trigger Sample Clock Figure 5-5. ao/PauseTrigger with Other Signal Source Using a Digital Source To use ao/PauseTrigger, specify a source and a polarity. The source can be one of the following signals: • Input PFI <0..5> • RTSI <0..7> • PXI_STAR The source also can be one of several other internal signals on your DAQ device.
Chapter 5 Analog Output Using an Internal Source One of the following internal signals can drive ao/SampleClock. • AO Sample Clock Timebase (divided down) • Counter n Internal Output A programmable internal counter divides down the AO Sample Clock Timebase signal. Using an External Source Use one of the following external signals as the source of ao/SampleClock: • Input PFI <0..5> • RTSI <0..
Chapter 5 Analog Output ao/SampleClockTimebase ao/StartTrigger ao/SampleClock Delay From Start Trigger Figure 5-6. ao/SampleClock and ao/StartTrigger AO Sample Clock Timebase Signal The AO Sample Clock Timebase (ao/SampleClockTimebase) signal is divided down to provide a source for ao/SampleClock. You can route any of the following signals to be the AO Sample Clock Timebase (ao/SampleClockTimebase) signal: • 20 MHz Timebase • 100 kHz Timebase • PXI_CLK10 • Input PFI <0..5> • RTSI <0..
Chapter 5 • Finite generation • Continuous generation • Waveform generation Analog Output You can perform these generations through programmed I/O, interrupt, or DMA data transfer mechanisms. Some of the applications also use start triggers and pause triggers. Note For more information about programming analog output applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.
Digital Input and Output 6 NI 6232/6233 devices have six static digital input lines, P0.<0..5>. These lines also can be used as PFI inputs. The voltage input and output levels and the current drive level of the DI and DO lines are listed in the NI 6232/6233 Specifications. Refer to Chapter 8, PFI, for more information on PFI inputs and outputs. I/O Protection Each DI, DO, and PFI signal is protected against ESD events on NI 6232/6233 devices. Consult the device specifications for details.
Chapter 6 Digital Input and Output Connecting Digital I/O Signals The DI signals P0.<0..5> are referenced to P0.GND and DO signals P1.<0..3> are referenced to P1.GND. Figures 6-1 and 6-2 show P0.<0..5> and P1.<0..3> on the NI 6232 and the NI 6233 device, respectively. Digital input and output signals can range from 0 to 30 V. Refer to the NI 6232/6233 Specifications for more information. P1.VCC P1.0 P1.<0..3> Digital Isolators P1.1 P1.GND P1.GND P0.0 P0.GND P0.GND Figure 6-1.
Chapter 6 Digital Input and Output P1.VCC Buffer P1.0 P1.GND P1.<0..3> Digital Isolators P1.1 P1.GND P1.GND P0.0 P0.GND P0.GND Figure 6-2. NI 6233 Digital I/O Connections (DO Sink) Caution Exceeding the maximum input voltage or maximum working voltage ratings, which are listed in the NI 6232/6233 Specifications, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections.
Chapter 6 Digital Input and Output Table 6-1. NI 6232/6233 Logic Conventions Device Logic 0 1 NI 6232 (Source) DO P1.GND P1.VCC NI 6233 (Sink) DO P1.VCC P1.GND Getting Started with DIO Applications in Software You can use NI 6232/6233 devices in the following digital I/O applications: • Static digital input • Static digital output Note For more information about programming digital I/O applications and triggers in software, refer to the NI-DAQmx Help or the LabVIEW 8.x Help.
7 Counters NI 6232/6233 devices have two general-purpose 32-bit counter/timers and one frequency generator, as shown in Figure 7-1. The general-purpose counter/timers can be used for many measurement and pulse generation applications. Caution When making measurements, take into account the minimum pulse width and time delay of the digital input and output lines. Refer to the NI 6238/6239 Specifications for more information.
Chapter 7 Counters Input Selection Muxes Counter 0 Counter 0 Source (Counter 0 Timebase) Counter 0 Gate Counter 0 Internal Output Counter 0 Aux Counter 0 HW Arm Counter 0 A Counter 0 B (Counter 0 Up_Down) Counter 0 TC Counter 0 Z Input Selection Muxes Counter 1 Counter 1 Source (Counter 1 Timebase) Counter 1 Gate Counter 0 Internal Output Counter 1 Aux Counter 1 HW Arm Counter 1 A Counter 1 B (Counter 1 Up_Down) Counter 0 TC Counter 1 Z Input Selection Muxes Frequency Generator Frequency Output
Chapter 7 Counters Counter Input Applications Counting Edges In edge counting applications, the counter counts edges on its Source after the counter is armed. You can configure the counter to count rising or falling edges on its Source input. You also can control the direction of counting (up or down). The counter values can be read on demand or with a sample clock.
Chapter 7 Counters Counter Armed Pause Trigger (Pause When Low) SOURCE Counter Value 0 0 1 2 3 4 5 Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger Buffered (Sample Clock) Edge Counting With buffered edge counting (edge counting using a sample clock), the counter counts the number of edges on the Source input after the counter is armed. The value of the counter is sampled on each active edge of a sample clock. A DMA controller transfers the sampled values to host memory.
Chapter 7 Counters Non-Cumulative Buffered Edge Counting Non-cumulative edge counting is similar to buffered (sample clock) edge counting. However, the counter resets after each active edge of the Sample Clock. You can route the Sample Clock to the Gate input of the counter. Figure 7-5 shows an example of non-cumulative buffered edge counting. Counter Armed Sample Clock (Sample on Rising Edge) SOURCE Counter Value 0 1 2 1 2 Buffer 2 3 1 2 3 2 3 1 2 3 3 Figure 7-5.
Chapter 7 Counters Pulse-Width Measurement In pulse-width measurements, the counter measures the width of a pulse on its Gate input signal. You can configure the counter to measure the width of high pulses or low pulses on the Gate signal. You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges on the Source signal while the pulse on the Gate signal is active.
Chapter 7 Counters Buffered Pulse-Width Measurement Buffered pulse-width measurement is similar to single pulse-width measurement, but buffered pulse-width measurement takes measurements over multiple pulses. The counter counts the number of edges on the Source input while the Gate input remains active. On each trailing edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory.
Chapter 7 Counters of rising (or falling) edges occurring on the Source input between the two active edges of the Gate signal. You can calculate the period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter. Single Period Measurement With single period measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between two active edges of the Gate input.
Chapter 7 Counters Counter Armed GATE SOURCE 1 Counter Value 2 1 2 2 2 (Discard) 3 1 2 3 2 (Discard) 3 1 3 2 (Discard) 3 3 3 Buffer Figure 7-9. Buffered Period Measurement Note that if you are using an external signal as the Source, at least one Source pulse should occur between each active edge of the Gate signal. This condition ensures that correct values are returned by the counter. If this condition is not met, consider using duplicate count prevention.
Chapter 7 Counters Buffered Semi-Period Measurement In buffered semi-period measurement, on each edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory. The counter begins counting when it is armed. The arm usually occurs between edges on the Gate input. So the first value stored in the hardware save register does not reflect a full semi-period of the Gate input.
Chapter 7 Counters You can route the signal to measure (F1) to the Gate of a counter. You can route a known timebase (Ft) to the Source of the counter. The known timebase can be 80MHzTimebase. For signals that might be slower than 0.02 Hz, use a slower known timebase. You can configure the counter to measure one period of the gate signal. The frequency of F1 is the inverse of the period. Figure 7-11 illustrates this method.
Chapter 7 Counters T1 F1 Gate Ft Source Intervals Measured T2 … TK F1 1 2 ...N11... ...N2 … 1... ...NK Ft Buffered Period Measurement Average Period of F1 = Frequency of F1 = N1 + N2 + …NK K × 1 Ft K × Ft N1 + N2 + …NK Figure 7-12. Method 1b Method 2—Measure High Frequency with Two Counters In this method, you measure one pulse of a known width using your signal and derive the frequency of your signal from the result. This method is good for high frequency signals.
Chapter 7 Counters Width of Pulse (T) Pulse Pulse Gate 1 F1 Source 2 N … F1 Pulse-Width Measurement Width of T = Pulse N F1 Frequency of F1 = N T Figure 7-13. Method 2 Method 3—Measure Large Range of Frequencies Using Two Counters By using two counters, you can accurately measure a signal that might be high or low frequency. This technique is called reciprocal frequency measurement. In this method, you generate a long pulse using the signal to measure.
Chapter 7 Counters Signal to Measure (F1) SOURCE OUT COUNTER 0 Signal of Known Frequency (F2) SOURCE OUT COUNTER 1 GATE CTR_0_SOURCE (Signal to Measure) CTR_0_OUT (CTR_1_GATE) 0 1 2 3 … N Interval to Measure CTR_1_SOURCE Figure 7-14. Method 3 Then route the Counter 0 Internal Output signal to the Gate input of Counter 1. You can route a signal of known frequency (F2) to the Counter 1 Source input. F2 can be 80MHzTimebase. For signals that might be slower than 0.
Chapter 7 Counters Consider a frequency measurement on a 50 kHz signal using an 80 MHz Timebase. This frequency corresponds to 1600 cycles of the 80 MHz Timebase. Your measurement may return 1600 ±1 cycles depending on the phase of the signal with respect to the timebase. As your frequency becomes larger, this error of ±1 cycle becomes more significant. Table 7-1 illustrates this point. Table 7-1.
Chapter 7 Counters Table 7-2. Frequency Measurement Method Comparison Measures High Frequency Signals Accurately Measures Low Frequency Signals Accurately Method Number of Counters Used Number of Measurements Returned 1 1 1 Poor Good 1b 1 Many Fair Good 2 1 or 2 1 Good Poor 3 2 1 Good Good For information on connecting counter signals, refer to the Default Counter Terminals section.
Chapter 7 Counters Ch A Ch B Counter Value 5 6 7 7 5 6 Figure 7-15. X1 Encoding X2 Encoding The same behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A, depending on which channel leads the other. Each cycle results in two increments or decrements, as shown in Figure 7-16. Ch A Ch B Counter Value 5 6 7 8 9 9 7 8 6 5 Figure 7-16.
Chapter 7 Counters Channel Z behavior—when it goes high and how long it stays high—differs with quadrature encoder designs. You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B. You must then ensure that channel Z is high during at least a portion of the phase you specify for reload. For instance, in Figure 7-18, channel Z is never high when channel A is high and channel B is low. Thus, the reload must occur in some other phase.
Chapter 7 Counters For information on connecting counter signals, refer to the Default Counter Terminals section. Two-Signal Edge-Separation Measurement Two-signal edge-separation measurement is similar to pulse-width measurement, except that there are two measurement signals—Aux and Gate. An active edge on the Aux input starts the counting and an active edge on the Gate input stops the counting. You must arm a counter to begin a two edge separation measurement.
Chapter 7 Counters Counter Armed Measured Interval AUX GATE SOURCE Counter Value 0 0 0 0 1 2 3 4 5 6 7 8 HW Save Register 8 8 8 Figure 7-20. Single Two-Signal Edge-Separation Measurement Buffered Two-Signal Edge-Separation Measurement Buffered and single two-signal edge-separation measurements are similar, but buffered measurement measures multiple intervals.
Chapter 7 Counters Counter Output Applications Simple Pulse Generation Single Pulse Generation The counter can output a single pulse. The pulse appears on the Counter n Internal Output signal of the counter. You can specify a delay from when the counter is armed to the beginning of the pulse. The delay is measured in terms of a number of active edges of the Source input. You can specify a pulse width. The pulse width is also measured in terms of a number of active edges of the Source input.
Chapter 7 Counters GATE (Start Trigger) SOURCE OUT Figure 7-23. Single Pulse Generation with Start Trigger Retriggerable Single Pulse Generation The counter can output a single pulse in response to each pulse on a hardware Start Trigger signal. The pulses appear on the Counter n Internal Output signal of the counter. You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of each pulse. You also can specify the pulse width.
Chapter 7 Counters Pulse Train Generation Continuous Pulse Train Generation This function generates a train of pulses with programmable frequency and duty cycle. The pulses appear on the Counter n Internal Output signal of the counter. You can specify a delay from when the counter is armed to the beginning of the pulse train. The delay is measured in terms of a number of active edges of the Source input. You specify the high and low pulse widths of the output signal.
Chapter 7 Counters Frequency Generation You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit. Using the Frequency Generator The frequency generator can output a square wave at many different frequencies. The frequency generator is independent of the two general-purpose 32-bit counter/timer modules on M Series devices. Figure 7-26 shows a block diagram of the frequency generator.
Chapter 7 Counters Frequency Output can be routed out to any output PFI <6..9> or RTSI <0..7> terminal. All PFI terminals are set to high-impedance at startup. In software, program the frequency generator as you would program one of the counters for pulse train generation. For information on connecting counter signals, refer to the Default Counter Terminals section. Frequency Division The counters can generate a signal with a frequency that is a fraction of an input signal.
Chapter 7 Counters Nyquist frequency of the system. Figure 7-28 shows an example of pulse generation for ETS; the delay from the trigger to the pulse increases after each subsequent Gate active edge. GATE OUT D2 = D1 + ΔD D1 D3 = D1 + 2ΔD Figure 7-28. Pulse Generation for ETS For information on connecting counter signals, refer to the Default Counter Terminals section. Counter Timing Signals M Series devices feature the following counter timing signals.
Chapter 7 Counters Counter n Source Signal The selected edge of the Counter n Source signal increments and decrements the counter value depending on the application the counter is performing. Table 7-3 lists how this terminal is used in various applications. Table 7-3.
Chapter 7 Counters Routing Counter n Source to an Output Terminal You can route Counter n Source out to any output PFI <6..9> or RTSI <0..7> terminal. All PFIs are set to high-impedance at startup. Counter n Gate Signal The Counter n Gate signal can perform many different operations depending on the application including starting and stopping the counter, and saving the counter contents. Routing a Signal to Counter n Gate Each counter has independent input selectors for the Counter n Gate signal.
Chapter 7 Counters Routing a Signal to Counter n Aux Each counter has independent input selectors for the Counter n Aux signal. Any of the following signals can be routed to the Counter n Aux input. • RTSI <0..7> • Input PFI <0..5> • ai/ReferenceTrigger • ai/StartTrigger • PXI_STAR In addition, Counter 1 Internal Output, Counter 1 Gate, Counter 1 Source, or Counter 0 Gate can be routed to Counter 0 Aux.
Chapter 7 Counters Counter n HW Arm Signal The Counter n HW Arm signal enables a counter to begin an input or output function. To begin any counter input or output function, you must first enable, or arm, the counter. In some applications, such as buffered semi-period measurement, the counter begins counting when it is armed. In other applications, such as single pulse-width measurement, the counter begins waiting for the Gate signal when it is armed.
Chapter 7 Counters Routing Counter n Internal Output to an Output Terminal You can route Counter n Internal Output to any output PFI <6..9> or RTSI <0..7> terminal. All output PFIs are set to high-impedance at startup. Frequency Output Signal The Frequency Output (FREQ OUT) signal is the output of the frequency output generator. Routing Frequency Output to a Terminal You can route Frequency Output to any output PFI <6..9> terminal. All PFIs are set to high-impedance at startup.
Chapter 7 Counters You can use these defaults or select other sources and destinations for the counter/timer signals in NI-DAQmx. Refer to Connecting Counter Signals in the NI-DAQmx Help or the LabVIEW 8.x Help for more information on how to connect your signals for common counter measurements and generations. M Series default PFI lines for counter functions are listed in Physical Channels in the NI-DAQmx Help or the LabVIEW 8.x Help.
Chapter 7 Counters Pause Trigger You can use pause triggers in edge counting and continuous pulse generation applications. For edge counting acquisitions, the counter stops counting edges while the external trigger signal is low and resumes when the signal goes high or vice versa. For continuous pulse generations, the counter stops generating pulses while the external trigger signal is low and resumes when the signal goes high or vice versa.
Chapter 7 Counters Table 7-5. Filters Filter Setting N (Filter Clocks Needed to Pass Signal) Pulse Width Guaranteed to Pass Filter Pulse Width Guaranteed to Not Pass Filter 125 ns 5 125 ns 100 ns 6.425 µs 257 6.425 µs 6.400 µs 2.55 ms ~101,800 2.55 ms 2.54 ms Disabled — — — The filter setting for each input can be configured independently. On power up, the filters are disabled.
Chapter 7 Counters prescaling on each counter (prescaling can be disabled). Each prescaler consists of a small, simple counter that counts to eight (or two) and rolls over. This counter can run faster than the larger counters, which simply count the rollovers of this smaller counter. Thus, the prescaler acts as a frequency divider on the Source and puts out a frequency that is one-eighth (or one-half) of what it is accepting.
Chapter 7 Counters Rising Edge of Gate Counter detects rising edge of Gate on the next rising edge of Source. Gate Source Counter Value Buffer 6 7 1 2 7 1 2 7 Figure 7-31. Duplicate Count Prevention Example On the first rising edge of the Gate, the current count of 7 is stored. On the next rising edge of the Gate, the counter stores a 2 since two Source pulses occurred after the previous rising edge of Gate.
Chapter 7 Counters No Source edge, so no value written to buffer. Gate Source Counter Value 6 7 1 7 Buffer Figure 7-32. Duplicate Count Example Example Application That Prevents Duplicate Count With duplicate count prevention enabled, the counter synchronizes both the Source and Gate signals to the 80 MHz Timebase. By synchronizing to the timebase, the counter detects edges on the Gate even if the Source does not pulse.
Chapter 7 Counters Normally, the counter value and Counter n Internal Output signals change synchronously to the Source signal. With duplicate count prevention, the counter value and Counter n Internal Output signals change synchronously to the 80 MHz Timebase. Note that duplicate count prevention should only be used if the frequency of the Source signal is 20 MHz or less. When To Use Duplicate Count Prevention You should use duplicate count prevention if the following conditions are true.
Chapter 7 Counters In DAQmx, the device uses 80 MHz source mode if the user performs the following: • Performs a position measurement • Selects duplicate count prevention Otherwise, the mode depends on the signal that drives Counter n Source. Table 7-6 describes the conditions for each mode. Table 7-6.
Chapter 7 Counters Other Internal Source Mode In other internal source mode, the device synchronizes signals on the falling edge of the source, and counts on the following rising edge of the source, as shown in Figure 7-35. Source Synchronize Count Figure 7-35. Other Internal Source Mode External Source Mode In external source mode, the device generates a delayed Source signal by delaying the Source signal by several nanoseconds.
8 PFI NI 6232/6233 devices have 10 Programmable Function Interface (PFI) signals—six input signals and four output signals. Each PFI <0..5>/P0.<0..5> can be configured as a timing input signal for AI or counter/timer functions or a static digital input. Each PFI input also has a programmable debouncing filter. Caution When making measurements, take into account the minimum pulse width and time delay of the digital input and output lines. Refer to the NI 6238/6239 Specifications for more information.
Chapter 8 PFI Isolation Barrier Timing Signals Digital Isolators Static DO Buffer I/O Protection Output Enable PFI <6..9>/P1.<0..3> Note: One output enable is shared by all digital output signals. Figure 8-2. NI 6232/6233 PFI Output Circuitry When a terminal is used as a timing input or output signal, it is called PFI x (where x is an integer from 0 to 9). When a terminal is used as a static digital input or output, it is called P0.x or P1.x.
Chapter 8 PFI Exporting Timing Output Signals Using PFI Terminals You can route any of the following timing signals to any PFI <6..9> terminal. • AI Hold Complete Event • Counter n Source • Counter n Gate • Counter n Internal Output • Frequency Output • PXI_STAR • RTSI <0..7> Note Short pulses on the signal might not be observable by the user or another instrument. Refer to the Digital Output (Port 1) section of the NI 6232/6233 Specifications for more information.
Chapter 8 PFI I/O Connector PFI 0 PFI 2 PFI 0 Source PFI 2 Source D GND M Series Device Figure 8-3. PFI Input Signals Connections PFI Filters You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal. When the filters are enabled, your device samples the input on each rising edge of a filter clock. M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency. Note NI-DAQmx supports only filters on counter inputs.
Chapter 8 PFI Table 8-1. Filters Filter Setting N (Filter Clocks Needed to Pass Signal) Pulse Width Guaranteed to Pass Filter Pulse Width Guaranteed to Not Pass Filter 125 ns 5 125 ns 100 ns 6.425 µs 257 6.425 µs 6.400 µs 2.55 ms ~101,800 2.55 ms 2.54 ms Disabled — — — The filter setting for each input can be configured independently. On power up, the filters are disabled. Figure 8-4 shows an example of a low-to-high transition on an input that has its filter set to 125 ns (N = 5).
Chapter 8 PFI Consult the device specifications for details. However, you should avoid these fault conditions by following these guidelines. • Do not connect any digital output line to any external signal source, ground signal, or power supply. • Understand the current requirements of the load connected to the digital output lines. Do not exceed the specified current output limits of the digital outputs. NI has several signal conditioning solutions for digital applications requiring high current drive.
Chapter 8 PFI P1.VCC P1.0 P1.<0..3> Digital Isolators P1.1 P1.GND P1.GND P0.0 P0.GND P0.GND Figure 8-5.
Chapter 8 PFI P1.VCC P1.0 Buffer P1.GND P1.<0..3> Digital Isolators P1.1 P1.GND P1.GND P0.0 P0.GND P0.GND Figure 8-6. NI 6233 Digital I/O Connections (DO Sink) Caution Exceeding the maximum input voltage or maximum working voltage ratings, which are listed in the NI 6232/6233 Specifications, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections. NI 6232/6233 User Manual 8-8 ni.
9 Isolation and Digital Isolators NI 6232/6233 devices are isolated data acquisition devices. As shown in Figure 9-1, the analog input, analog output, counters, and PFI/static DIO circuitry are referenced to an isolated ground. The bus interface circuitry, RTSI, digital routing, and clock generation are all referenced to a non-isolated ground. Refer to Table 9-1 for an example of the symbols for isolated ground and non-isolated ground. Table 9-1.
Chapter 9 Isolation and Digital Isolators The non-isolated ground is connected to the chassis ground of the PC or chassis where the device is installed. The isolated ground is not connected to the chassis ground of the PC or chassis. The isolated ground can be at a higher or lower voltage relative to the non-isolated ground. All analog measurements are made relative to the isolated ground signal. The isolated ground is an input to the NI 6232/6233 device.
10 Digital Routing and Clock Generation The digital routing circuitry has the following three main functions. • Manages the flow of data between the bus interface and the acquisition/generation sub-systems (analog input, analog output, digital I/O, and the counters). The digital routing circuitry uses FIFOs (if present) in each sub-system to ensure efficient data movement. • Routes timing and control signals.
Chapter 10 Digital Routing and Clock Generation 80 MHz Timebase The 80 MHz Timebase can be used as the Source input to the 32-bit general-purpose counter/timers. The 80 MHz Timebase can be generated from either of the following. • Onboard oscillator • External signal (by using the external reference clock) 20 MHz Timebase The 20 MHz Timebase normally generates many of the AI and AO timing signals. The 20 MHz Timebase also can be used as the Source input to the 32-bit general-purpose counter/timers.
Chapter 10 Digital Routing and Clock Generation 10 MHz Reference Clock The 10 MHz reference clock can be used to synchronize other devices to your M Series device. The 10 MHz reference clock can be routed to the RTSI <0..7> terminals. Other devices connected to the RTSI bus can use this signal as a clock input. The 10 MHz reference clock is generated by dividing down the onboard oscillator.
Chapter 10 Digital Routing and Clock Generation • Share trigger signals between devices Many National Instruments DAQ, motion, vision, and CAN devices support RTSI. In a PCI system, the RTSI bus consists of the RTSI bus interface and a ribbon cable. The bus can route timing and trigger signals between several functions on as many as five DAQ, vision, motion, or CAN devices in the computer. In a PXI system, the RTSI bus consists of the RTSI bus interface and the PXI trigger signals on the PXI backplane.
Chapter 10 Digital Routing and Clock Generation Table 10-1. RTSI Signal Descriptions RTSI Bus Signal Terminal RTSI 7 34 RTSI 6 32 RTSI 5 30 RTSI 4 28 RTSI 3 26 RTSI 2 24 RTSI 1 22 RTSI 0 20 Not Connected. Do not connect signals to these terminals. 1–18 GND 19, 21, 23, 25, 27, 29, 31, 33 Note: RTSI <0..7> and GND are earth/chassis ground-referenced. They are not isolated. Using RTSI as Outputs RTSI <0..7> are bidirectional terminals.
Chapter 10 Digital Routing and Clock Generation Using RTSI Terminals as Timing Input Signals You can use RTSI terminals to route external timing signals to many different M Series functions. Each RTSI terminal can be routed to any of the following signals.
Chapter 10 Digital Routing and Clock Generation Table 10-2. Filters Filter Setting N (Filter Clocks Needed to Pass Signal) Pulse Width Guaranteed to Pass Filter Pulse Width Guaranteed to Not Pass Filter 125 ns 5 125 ns 100 ns 6.425 µs 257 6.425 µs 6.400 µs 2.55 ms ~101,800 2.55 ms 2.54 ms Disabled — — — The filter setting for each input can be configured independently. On power up, the filters are disabled.
Chapter 10 Digital Routing and Clock Generation PXI Clock and Trigger Signals Note PXI clock and trigger signals are only available on PXI devices. Other devices use RTSI. PXI_CLK10 PXI_CLK10 is a common low-skew 10 MHz clock reference clock for synchronization of multiple modules in a PXI measurement or control system. The PXI backplane is responsible for generating PXI_CLK10 independently to each peripheral slot in a PXI chassis.
Chapter 10 Digital Routing and Clock Generation An M Series device is not a Star Trigger controller. An M Series device may be used in the first peripheral slot of a PXI system, but the system will not be able to use the Star Trigger feature. PXI_STAR Filters You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal. When the filters are enabled, your device samples the input on each rising edge of a filter clock.
Chapter 10 Digital Routing and Clock Generation RTSI, PFI, or PXI_STAR Terminal Filter Clock (40 MHz) 1 1 2 3 4 1 2 3 4 5 Filtered input goes high when terminal is sampled high on five consecutive filter clocks. Filtered Input Figure 10-4. Filter Example Enabling filters introduces jitter on the input signal. For the 125 ns and 6.425 µs filter settings, the jitter is up to 25 ns. On the 2.55 ms setting, the jitter is up to 10.025 µs.
11 Bus Interface The bus interface circuitry of NI 6232/6233 devices efficiently moves data between host memory and the measurement and acquisition circuits. NI 6232/6233 devices are available for the following platforms. • PCI • PXI NI 6232/6233 devices are jumperless for complete plug-and-play operation. The operating system automatically assigns the base address, interrupt levels, and other resources.
Chapter 11 Bus Interface Each DMA controller supports packing and unpacking of data through the FIFOs to connect different size devices and optimize PCI bus utilization and automatically handles unaligned memory buffers. PXI Considerations Note PXI clock and trigger signals are only available on PXI devices. Other devices use RTSI.
Chapter 11 Bus Interface Using PXI with CompactPCI Using PXI-compatible products with standard CompactPCI products is an important feature provided by PXI Hardware Specification Revision 2.1. If you use a PXI-compatible plug-in module in a standard CompactPCI chassis, you cannot use PXI-specific functions, but you can still use the basic plug-in device functions. For example, the RTSI bus on a PXI M Series device is available in a PXI chassis, but not in a CompactPCI chassis.
Chapter 11 Bus Interface Interrupt Request (IRQ) IRQ transfers rely on the CPU to service data transfer requests. The device notifies the CPU when it is ready to transfer data. The data transfer speed is tightly coupled to the rate at which the CPU can service the interrupt requests. If you are using interrupts to transfer data at a rate faster than the rate the CPU can service the interrupts, your systems may start to freeze.
12 Triggering A trigger is a signal that causes an action, such as starting or stopping the acquisition of data. When you configure a trigger, you must decide how you want to produce the trigger and the action you want the trigger to cause. NI 6232/6233 devices support internal software triggering, as well as external digital triggering.
Chapter 12 Triggering NI 6232/6233 User Manual • Analog output generation • Counter behavior 12-2 ni.
A Device-Specific Information This appendix contains device pinouts, specifications, cable and accessory choices, and other information for the NI 6232 and NI 6233 M Series isolated devices. To obtain documentation for devices not listed here, refer to ni.com/manuals. NI 6232 NI 6232 Pinout Figure A-1 shows the pinout of the NI 6232. For a detailed description of each signal, refer to the I/O Connector Signal Descriptions section of Chapter 3, Connector Information.
Appendix A Device-Specific Information AI 8 AI 1 AI 2 AI 11 AI GND AI 12 AI 5 AI 6 AI 7 NC AO 0 AO GND PFI 1/P0.1 (Input) PFI 2/P0.2 (Input) PFI 4/P0.4 (Input) P1.VCC PFI 7/P1.1 (Output) PFI 8/P1.3 (Output) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 AI 0 AI 9 AI GND AI 10 AI 3 AI 4 AI 13 NC AI 14 AI 15 NC AO 1 PFI 0/P0.0 (Input) P0.GND PFI 3/P0.3 (Input) PFI 5/P0.5 (Input) PFI 6/P1.0 (Output) PFI 8/P1.2 (Output) P1.
Appendix A Device-Specific Information Table A-1. NI 6232 Device Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) Port CTR 1 OUT 36 (PFI 7) P1.1 CTR 1 A 15 (PFI 3) P0.3 CTR 1 Z 34 (PFI 4) P0.4 CTR 1 B 16 (PFI 5) P0.5 Note For more information about default NI-DAQmx counter inputs, refer to Connecting Counter Signals in the NI-DAQmx Help or the LabVIEW 8.x Help.
Appendix A Device-Specific Information vision, and motion devices. Since PXI devices use PXI backplane signals for timing and synchronization, no cables are required. Cables In most applications, you can use the following cables: • SH37F-37M-x—37-pin female-to-male shielded I/O cable, UL Listed derated to 30 Vrms, 42.
Appendix A AI 8 AI 1 AI 2 AI 11 AI GND AI 12 AI 5 AI 6 AI 7 NC AO 0 AO GND PFI 1/P0.1 (Input) PFI 2/P0.2 (Input) PFI 4/P0.4 (Input) P1.GND PFI 7/P1.1 (Output) PFI 8/P1.3 (Output) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Device-Specific Information AI 0 AI 9 AI GND AI 10 AI 3 AI 4 AI 13 NC AI 14 AI 15 NC AO 1 PFI 0/P0.0 (Input) P0.GND PFI 3/P0.3 (Input) PFI 5/P0.5 (Input) PFI 6/P1.0 (Output) PFI 8/P1.2 (Output) P1.
Appendix A Device-Specific Information Table A-2. NI 6233 Device Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) Port CTR 1 OUT 36 (PFI 7) P1.1 CTR 1 A 15 (PFI 3) P0.3 CTR 1 Z 34 (PFI 4) P0.4 CTR 1 B 16 (PFI 5) P0.5 Note For more information about default NI-DAQmx counter inputs, refer to Connecting Counter Signals in the NI-DAQmx Help or the LabVIEW 8.x Help.
Appendix A Device-Specific Information vision, and motion devices. Since PXI devices use PXI backplane signals for timing and synchronization, no cables are required. Cables In most applications, you can use the following cables: • SH37F-37M-x—37-pin female-to-male shielded I/O cable, UL Listed derated to 30 Vrms, 42.
B Troubleshooting This section contains some common questions about M Series devices. If your questions are not answered here, refer to the National Instruments KnowledgeBase at ni.com/kb. It contains thousands of documents that answer frequently asked questions about NI products. Analog Input I am seeing crosstalk or ghost voltages when sampling multiple channels.
Appendix B Troubleshooting reference the signal to the same ground level as the device reference. There are various methods of achieving this reference while maintaining a high common-mode rejection ratio (CMRR). These methods are outlined in the Connecting Analog Voltage Input Signals section of Chapter 4, Analog Input. AI GND is an AI common signal that routes directly to the ground connection point on the devices.
Appendix B Troubleshooting Analog Output I am seeing glitches on the output signal. How can I minimize it? When you use a DAC to generate a waveform, you may observe glitches on the output signal. These glitches are normal; when a DAC switches from one voltage to another, it produces glitches due to released charges. The largest glitches occur when the most significant bit of the DAC code changes.
Technical Support and Professional Services C Visit the following sections of the National Instruments Web site at ni.com for technical support and professional services: • Support—Online technical support resources at ni.
Appendix C Technical Support and Professional Services • Calibration Certificate—If your product supports calibration, you can obtain the calibration certificate for your product at ni.com/calibration. If you searched ni.com and could not find the answers you need, contact your local office or NI corporate headquarters. Phone numbers for our worldwide offices are listed at the front of this manual. You also can visit the Worldwide Offices section of ni.
Glossary Numbers/Symbols % Percent. + Positive of, or plus. – Negative of, or minus. ± Plus or minus. < Less than. > Greater than. Less than or equal to. Greater than or equal to. / Per. º Degree. Ω Ohm. A A Amperes—the unit of electric current. A/D Analog-to-Digital. Most often used as A/D converter. AC Alternating current. accuracy A measure of the capability of an instrument or sensor to faithfully indicate the value of the measured signal.
Glossary AI 1. Analog input. 2. Analog input channel signal. AI GND Analog input ground signal. AI SENSE Analog input sense signal. analog A signal whose amplitude can have a continuous range of values. analog input signal An input signal that varies smoothly over a continuous range of values, rather than in discrete steps. analog output signal An output signal that varies smoothly over a continuous range of values, rather than in discrete steps.
Glossary ASIC Application-specific integrated circuit—A proprietary semiconductor component designed and manufactured to perform a set of specific functions for a specific customer. asynchronous 1. Hardware—A property of an event that occurs at an arbitrary time, without synchronization to a reference clock. 2. Software—A property of a function that begins an operation and returns prior to the completion or termination of the operation. B b Bit—One binary digit, either 0 or 1.
Glossary cascading Process of extending the counting range of a counter chip by connecting to the next higher counter. CE European emissions control standard. channel Pin or wire lead to which you apply or from which you read the analog or digital signal. Analog signals can be single-ended or differential. For digital signals, you group channels to form ports. Ports usually consist of either four or eight digital channels.
Glossary counter/timer A circuit that counts external pulses or clock pulses (timing). D D GND Digital ground signal. D-SUB connector A serial connector. DAC Digital-to-Analog Converter—An electronic device, often an integrated circuit, that converts a digital number into a corresponding analog voltage or current. In the instrumentation world, DACs can be used to generate arbitrary waveform shapes, defined by the software algorithm that computes the digital data pattern, which is fed to the DAC.
Glossary data transfer A technique for moving digital data from one system to another. Options for data transfer are DMA, interrupt, and programmed I/O. For programmed I/O transfers, the CPU in the PC reads data from the DAQ device whenever the CPU receives a software signal to acquire a single data point. Interrupt-based data transfers occur when the DAQ device sends an interrupt to the CPU, telling the CPU to read the acquired data from the DAQ device.
Glossary digital signal A representation of information by a set of discrete values according to a prescribed law. These values are represented by numbers. digital trigger A TTL level signal having two discrete levels—a high and a low level. DIO Digital input/output. DMA Direct Memory Access—A method by which data can be transferred to/ from computer memory from/to a device or memory on the bus while the processor does something else.
Glossary F FIFO First-In-First-Out memory buffer—A data buffering technique that functions like a shift register where the oldest values (first in) come out first. Many DAQ products and instruments use FIFOs to buffer digital data from an A/D converter, or to buffer the data before or after bus transmission. The first data stored is the first data sent to the acceptor. FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be retrieved or output.
Glossary function 1. A built-in execution element, comparable to an operator, function, or statement in a conventional language. 2. A set of software instructions executed by a single line of code that may have input and/or output parameters and returns a value when executed. G glitch An unwanted signal excursion of short duration that is usually unavoidable. GND See ground. ground 1. A pin. 2. An electrically neutral wire that has the same potential as the surrounding earth.
Glossary in. Inch or inches. instrument driver A set of high-level software functions that controls a specific GPIB, VXI, or RS232 programmable instrument or a specific plug-in DAQ device. Instrument drivers are available in several forms, ranging from a function callable language to a virtual instrument (VI) in LabVIEW. instrumentation amplifier A circuit whose output voltage with respect to ground is proportional to the difference between the voltages at its two inputs.
Glossary K kHz Kilohertz—A unit of frequency; 1 kHz = 103 = 1,000 Hz. kS 1,000 samples. L LabVIEW A graphical programming language. LED Light-Emitting Diode—A semiconductor light source. lowpass filter A filter that passes signals below a cutoff frequency while blocking signals above that frequency. LSB Least Significant Bit. M m Meter. M Series An architecture for instrumentation-class, multichannel data acquisition devices based on the earlier E Series architecture with added new features.
Glossary MITE MXI Interface To Everything—A custom ASIC designed by National Instruments that implements the PCI bus interface. The MITE supports bus mastering for high-speed data transfers over the PCI bus. module A board assembly and its associated mechanical parts, front panel, optional shields, and so on. A module contains everything required to occupy one or more slots in a mainframe. SCXI and PXI devices are modules.
Glossary NI-PGIA See instrumentation amplifier. non-referenced signal sources Signal sources with voltage signals that are not connected to an absolute reference or system ground. Also called floating signal sources. Some common example of non-referenced signal sources are batteries, transformers, or thermocouples.
Glossary power source An instrument that provides one or more sources of AC or DC power. Also known as power supply. ppm Parts per million. pretriggering The technique used on a DAQ device to keep a continuous buffer filled with data, so that when the trigger conditions are met, the sample includes the data leading up to the trigger condition. pulse A signal whose amplitude deviates from zero for a short period of time.
Glossary R range The maximum and minimum parameters between which a sensor, instrument, or device operates with a specified set of characteristics. This may be a voltage range or a frequency range. real time 1. Displays as it comes in; no delays. 2. A property of an event or system in which data is processed and acted upon as it is acquired instead of being accumulated and processed at a later time. 3.
Glossary scan rate Reciprocal of the scan interval. SCC Signal Conditioning Carriers—A compact, modular form factor for signal conditioning modules. SCXI Signal Conditioning eXtensions for Instrumentation—The National Instruments product line for conditioning low-level signals within an external chassis near sensors so that only high-level signals are sent to DAQ devices in the noisy PC environment.
Glossary software applications The programs that run on your computer and perform a specific useroriented function, such as accounting, program development, measurement, or data acquisition. In contrast, operating system functions basically perform the generic "housekeeping" of the machine, which is independent of any specific application.
Glossary tout Output delay time. transducer A device that responds to a physical stimulus (heat, light, sound, pressure, motion, flow, and so on), and produces a corresponding electrical signal. See also sensor. trigger 1. Any event that causes or starts some form of data capture. 2. An external stimulus that initiates one or more instrument functions. Trigger stimuli include a front panel button, an external input voltage pulse, or a bus trigger command.
Glossary Vm Measured voltage. VOH Volts, output high. VOL Volts, output low. Vout Volts out. Vs Signal source voltage. virtual channel See channel. W waveform 1. The plot of the instantaneous amplitude of a signal as a function of time. 2. Multiple voltage readings taken at a specific sampling rate.
Index Symbols ai/HoldCompleteEvent, 4-28 ai/PauseTrigger, 4-30 ai/ReferenceTrigger, 4-29 ai/SampleClock, 4-22 ai/SampleClockTimebase, 4-24 ai/StartTrigger, 4-28 analog input analog-to-digital converter, 4-2 charge injection, B-1 circuitry, 4-1 crosstalk when sampling multiple channels, B-1 data acquisition methods, 4-9 differential, troubleshooting, B-1 FIFO, 4-2 getting started with applications in software, 4-31 ghost voltages when sampling multiple channels, B-1 ground-reference settings, 4-2, 4-3 I/O c
Index bus getting started with applications in software, 5-10 glitches on the output signal, 5-2 signals, 5-5 timing signals, 5-5 trigger signals, 5-4 triggering, 5-4 troubleshooting, B-3 ANSI C documentation, xviii AO FIFO, 5-1 AO Pause Trigger signal, 5-7 AO Sample Clock signal, 5-8 AO Sample Clock Timebase signal, 5-10 AO Start Trigger signal, 5-6 ao/PauseTrigger, 5-7 ao/SampleClock, 5-8 ao/SampleClockTimebase, 5-10 ao/StartTrigger, 5-6 applications counter input, 7-3 counter output, 7-21 edge counting
Index Counter n Source, 7-27 Counter n TC, 7-30 Counter n Up_Down, 7-29 FREQ OUT, 7-31 Frequency Output, 7-31 counter terminals, default, 7-31 counters cascading, 7-33 duplicate count prevention, 7-35 edge counting, 7-3 filters, 7-33 generation, 7-21 input applications, 7-3 other features, 7-33 output applications, 7-21 prescaling, 7-34 pulse train generation, 7-23 retriggerable single pulse generation, 7-22 simple pulse generation, 7-21 single pulse generation, 7-21 single pulse generation with start trig
Index DMA as a transfer method, 11-3 changing data transfer methods, 11-4 controllers, 11-1 documentation conventions used in manual, xv NI resources, C-1 related documentation, xvi double-buffered acquisition, 4-10 drivers (NI resources), C-1 duplicate count prevention, 7-35 enabling in NI-DAQmx, 7-38 example, 7-37 troubleshooting, B-3 data transfer methods, 11-3 changing, 11-4 DMA, 11-3 IRQ, 11-4 programmed I/O, 11-4 Declaration of Conformity (NI resources), C-1 default counter terminals, 7-31 device ca
Index F grounded signal sources, single-ended connection, 4-17 ground-reference connections, checking, B-1 settings, analog input, 4-3 ground-referenced differential connections, 4-14 signal sources, 4-13 features, counter, 7-33 field wiring considerations, 4-18 filters counter, 7-33 PFI, 8-4 PXI_STAR, 10-9 RTSI, 10-6 floating signal sources, 4-13 FREQ OUT signal, 7-31 frequency division, 7-25 generation, 7-24 generator, 7-24 measurement, 7-10 Frequency Output signal, 7-31 H hardware DAQ, 2-1 installing
Index measuring high frequency with two counters, 7-12 large range of frequencies using two counters, 7-13 low frequency with one counter, 7-10 averaged, 7-11 methods, data transfer, 11-3 minimizing glitches on the output signal, 5-2 output signal glitches (troubleshooting), B-3 voltage step between adjacent channels, 4-8 multichannel scanning considerations, 4-6 multiple device synchronization, 10-3 isolation barrier, 4-2, 5-2 isolators, 9-1 K KnowledgeBase, C-1 L LabVIEW documentation, xvii LabWindows
Index prescaling, 7-34 programmable function interface, 8-1 programmable power-up states, 6-1, 8-6 programmed I/O, 11-4 programming devices in software, 2-5 programming examples (NI resources), C-1 pulse encoders, measurements using two, 7-18 generation for ETS, 7-25 train generation, 7-23 continuous, 7-23 pulse-width measurement, 7-6 buffered, 7-7 single, 7-6 PXI and PXI Express, 11-2 clock, 11-2 clock and trigger signals, 10-8 considerations, 11-2 trigger signals, 11-2 triggers, 10-8 using with CompactPC
Index AO Sample Clock Timebase, 5-10 AO Start Trigger, 5-6 connecting analog voltage input, 4-11 connecting analog voltage output, 5-4 connecting counter, B-3 connecting digital I/O, 6-2, 8-6 connecting PFI input, 8-3 Counter n A, 7-29 Counter n Aux, 7-28 Counter n B, 7-29 Counter n Gate, 7-28 Counter n HW Arm, 7-30 Counter n Internal Output, 7-30 Counter n Source, 7-27 Counter n TC, 7-30 Counter n Up_Down, 7-29 Counter n Z, 7-29 counter timing, 7-26 counters, 7-26 exporting timing output using PFI termina
Index transducers, 2-3 triggering, 12-1 analog input, 4-11 counter, 7-32 with a digital source, 12-1 triggers, 12-1 AI Pause Trigger signal, 4-30 AI Reference Trigger signal, 4-29 AI Start Trigger signal, 4-28 AO Pause Trigger signal, 5-7 AO Start Trigger signal, 5-6 arm start, 7-32 pause, 7-33 PXI, 10-8 PXI_STAR, 10-8 Star Trigger, 10-8 start, 7-32 troubleshooting analog input, B-1 analog output, B-3 counters, B-3 NI resources, C-1 two-signal edge-separation measurement, 7-19 buffered, 7-20 single, 7-19
Index V X voltage connecting analog input signals, 4-11 connecting analog voltage, 5-4 X1 encoding, 7-16 X2 encoding, 7-17 X4 encoding, 7-17 W waveform generation signals, 5-5 Web resources, C-1 wiring, field, 4-18 NI 6232/6233 User Manual I-10 ni.
