DAQ S Series NI 6124/6154 User Manual DAQ-STC2 S Series Simultaneous Sampling Multifunction Input/Output Devices NI 6124/6154 User Manual August 2008 372613A-01
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Important Information Warranty NI 6124 and NI 6154 devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
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Contents About This Manual Conventions ...................................................................................................................xi Related Documentation..................................................................................................xii Chapter 1 Getting Started Installing NI-DAQmx ....................................................................................................1-1 Installing Other Software........................................................
Contents Connecting Analog Input Signals.................................................................................. 4-6 Types of Signal Sources.................................................................................. 4-7 Differential Connections for Ground-Referenced Signal Sources.................. 4-7 Common-Mode Signal Rejection Considerations ............................ 4-9 Differential Connections for Non-Referenced or Floating Signal Sources .... 4-9 DC-Coupled.......................
Contents Other Timing Requirements..............................................................5-7 AO Sample Clock Timebase Signal ................................................................5-8 AO Start Trigger Signal...................................................................................5-9 Using a Digital Source ......................................................................5-9 Using an Analog Source ...................................................................
Contents Period Measurement ....................................................................................... 7-6 Single Period Measurement.............................................................. 7-6 Buffered Period Measurement.......................................................... 7-7 Semi-Period Measurement .............................................................................. 7-7 Single Semi-Period Measurement ....................................................
Contents Frequency Output Signal.................................................................................7-30 Routing Frequency Output to a Terminal .........................................7-30 Default Counter/Timer Pinouts......................................................................................7-30 Counter Triggering ........................................................................................................7-31 Other Counter Features .....................................
Contents Real-Time System Integration (RTSI) .......................................................................... 9-4 RTSI Connector Pinout ................................................................................... 9-4 Using RTSI as Outputs ................................................................................... 9-5 Using RTSI Terminals as Timing Input Signals............................................. 9-6 RTSI Filters.............................................................
About This Manual The NI 6124/6154 User Manual contains information about using the National Instruments S Series NI 6124 and NI 6154 data acquisition (DAQ) devices with NI-DAQmx 8.8 and later. Conventions The following conventions appear in this manual: <> Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name—for example, AO <3..0>. » The » symbol leads you through nested menu items and dialog box options to a final action.
About This Manual Related Documentation Each application software package and driver includes information about writing applications for taking measurements and controlling measurement devices. The following references to documents assume you have NI-DAQmx 8.8 or later, and where applicable, version 7.1 or later of the NI application software.
About This Manual • VI and Function Reference»Measurement I/O VIs and Functions—Describes the LabVIEW NI-DAQmx VIs and properties. • Taking Measurements—Contains the conceptual and how-to information you need to acquire and analyze measurement data in LabVIEW, including common measurements, measurement fundamentals, NI-DAQmx key concepts, and device considerations. LabWindows/CVI The Data Acquisition book of the LabWindows/CVI Help contains measurement concepts for NI-DAQmx.
About This Manual To create an application in Visual C++, Visual C#, or Visual Basic .NET, follow these general steps: 1. In Visual Studio .NET, select File»New»Project to launch the New Project dialog box. 2. Find the Measurement Studio folder for the language you want to create a program in. 3. Choose a project type. You add DAQ tasks as a part of this step. ANSI C without NI Application Software The NI-DAQmx Help contains API overviews and general information about measurement concepts.
About This Manual Device Documentation and Specifications The NI 6124 Specifications and NI 6154 Specifications documents contain all specifications for the NI 6124 and NI 6154 S Series devices respectively. Documentation for supported devices and accessories, including PDF and help files describing device terminals, specifications, features, and operation are on the NI-DAQmx CD that includes Device Documentation.
1 Getting Started The NI 6124 and NI 6154 are simultaneous sampling multifunction I/O devices (S Series) that use the DAQ-STC2 ASIC. The NI 6124 S Series is a non-isolated device featuring PXI Express connectivity, four simultaneously sampling 16-bit analog inputs, two 16-bit voltage analog outputs, 24 lines of bidirectional DIO, and two general-purpose 32-bit counter/timers.
Chapter 1 Getting Started Installing the Hardware The DAQ Getting Started Guide contains non-software-specific information about how to install PCI and PXI Express devices, as well as accessories and cables. Device Self-Calibration NI recommends that you self-calibrate your S Series device after installation and whenever the ambient temperature changes. Self-calibration should be performed after the device has warmed up for the recommended time period.
Chapter 1 Getting Started Device Pinouts Refer to Appendix A, Device-Specific Information, for NI 6124 and NI 6154 device pinouts. Device Specifications Refer to the specifications for your device, the NI 6124 Specifications or the NI 6154 Specifications, available on the NI-DAQ Device Document Browser or ni.com/manuals, for more detailed information about the NI 6124 and NI 6154 devices.
2 DAQ System Overview Figure 2-1 shows a typical DAQ system setup, which includes transducers, signal conditioning, cables that connect the various devices to the accessories, the S Series device, and the programming software. Refer to Appendix A, Device-Specific Information, for a list of devices and their compatible accessories. 4 3 2 + V – 1 1 2 3 5 Sensors and Transducers Signal Conditioning Cable Assembly 4 5 DAQ Hardware Personal Computer/Chassis and DAQ Software Figure 2-1.
Chapter 2 DAQ System Overview DAQ Hardware DAQ hardware digitizes signals, performs D/A conversions to generate analog output signals, and measures and controls digital I/O signals. The following sections contain more information about specific components of the DAQ hardware. Figure 2-2 shows the components of the non-isolated S Series (NI 6124) device. Analog Input I/O Connector Analog Output Digital I/O Digital Routing Bus Interface Bus Counters RTSI PFI Figure 2-2.
Chapter 2 DAQ System Overview (NI 6154 Only) S Series isolated hardware also includes bank and channel-to-channel isolation. Isolated DAQ hardware allows for increased protection against hazardous voltages, rejection of common-mode voltages, and reduction of ground loops and their associated noise. Figure 2-3 shows the components of the isolated S Series (NI 6154) device.
Chapter 2 DAQ System Overview • Two flexible 32-bit counter/timer modules with hardware gating • Digital waveform acquisition and generation • Static DIO signals • True 5 V high current drive DO • PLL for clock synchronization • PCI/PXI interface • Independent scatter-gather DMA controllers for all acquisition and generation functions Calibration Circuitry Calibration is the process of making adjustments to a measurement device to reduce errors associated with measurements.
Chapter 2 DAQ System Overview External Calibration External calibration is a process to adjust the device relative to a traceable, high precision calibration standard. The accuracy specifications of your device change depending on how long it has been since your last external calibration. National Instruments recommends that you calibrate your device at least as often as the intervals listed in the accuracy specifications.
Chapter 2 DAQ System Overview • If you are using other application software, refer to Common Sensors in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later. Programming Devices in Software National Instruments measurement devices are packaged with NI-DAQmx driver software, an extensive library of functions and VIs you can call from your application software, such as LabVIEW or LabWindows/CVI, to program all the features of your NI measurement devices.
3 I/O Connector This chapter contains information about the S Series I/O connector. Refer to one of the following sections, depending on your device: • NI 6124 I/O Connector Signal Descriptions • NI 6154 I/O Connector Signal Descriptions Refer to Appendix A, Device-Specific Information, for the I/O connector pinout for your device. NI 6124 I/O Connector Signal Descriptions (NI 6124 Only) Table 3-1 describes the signals found on the NI 6124 I/O connector.
Chapter 3 I/O Connector Table 3-1. NI 6124 Device Signal Descriptions (Continued) I/O Connector Pin Reference Direction Signal Description P0.<0..7> D GND Input or Output Digital I/O Channels 0 through 7—You can individually configure each signal as an input or output. P0.6 and P0.7 can also control the up/down signal of Counters 0 and 1, respectively. PFI <0..7>/P1.<0..7> PFI <8..15>/P2.<0..
Chapter 3 I/O Connector Table 3-2. NI 6154 I/O Connector Signal Descriptions (Continued) I/O Connector Pin PFI <0..5>/P0.<0..5> Reference D GND Direction Signal Description Input Programmable Function Interface or Static Digital Input Channels 0 to 5—Each of these terminals can be individually configured as a PFI terminal or a digital input terminal. As an input, each PFI terminal can be used to supply an external source for AI or AO timing signals or counter/timer inputs. Note: PFI <0..5>/P0.<0..
4 Analog Input Figure 4-1 shows the analog input circuitry of each channel of the non-isolated S Series (NI 6124) device. Instrumentation Amplifier Filter AI+ AI FIFO ADC AI Data Mux AI– Analog Trigger CAL AI Timing Signals Figure 4-1. Non-Isolated S Series Analog Input Block Diagram Figure 4-2 shows the analog input circuitry of each channel of the isolated S Series (NI 6154) device.
Chapter 4 Analog Input On S Series devices, each channel uses its own instrumentation amplifier, FIFO, multiplexer (mux), and A/D converter (ADC) to achieve simultaneous data acquisition. The main blocks featured in the S Series analog input circuitry are as follows: • Mux—By default, the mux is set to route AI signals to the analog front end. When you calibrate your device, the state of the mux switches. You can manually switch the state of the mux to measure AI GND.
Chapter 4 Analog Input Exceeding the differential and common-mode input ranges distorts the input signals. Exceeding the maximum input voltage rating can damage the device and the computer. NI is not liable for any damage resulting from such signal connections. The maximum input voltage ratings can be found in the specifications document for each S Series device.
Chapter 4 Analog Input Working Voltage Range On most S Series devices, the PGIA operates normally by amplifying signals of interest while rejecting common-mode signals under the following three conditions: • The common-mode voltage (Vcm), which is equivalent to subtracting AI <0..x> GND from AI <0..x> –, must be less than ±10 V. This Vcm is a constant for all range selections. • The signal voltage (Vs), which is equivalent to subtracting AI <0..x> + from AI <0..
Chapter 4 Analog Input Hardware-timed acquisitions have several advantages over software-timed acquisitions: – The time between samples can be much shorter. – The timing between samples can be deterministic. – Hardware-timed acquisitions can use hardware triggering. For more information, refer to Chapter 11, Triggering. Hardware-timed operations can be buffered or non-buffered. A buffer is a temporary storage in the computer memory where acquired samples are stored.
Chapter 4 Analog Input Analog Input Triggering Analog input supports two different triggering actions: start and reference. An analog or digital hardware trigger can initiate these actions. All S Series devices support digital triggering, and some also support analog triggering. To find your device’s triggering options, refer to the specifications document for your device. The AI Start Trigger Signal and AI Reference Trigger Signal sections contain information about the analog input trigger signals.
Chapter 4 Analog Input Refer to the Analog Input Terminal Configuration section for descriptions of the input modes. Types of Signal Sources When configuring the input channels and making signal connections, first determine whether the signal sources are floating or ground-referenced: • Floating Signal Sources—A floating signal source is not connected in any way to the building ground system, and instead has an isolated ground-reference point.
Chapter 4 Analog Input Non-Isolated S Series Device AI 0+ GroundReferenced Signal Source + Instrumentation Amplifier + Vs + – CommonMode Noise and Ground Potential AI 0– – + Measured Voltage Vm – Vcm – AI 0 GND I/O Connector AI 0 Connections Shown Figure 4-3. Differential Connection for Ground-Referenced Signals on Non-Isolated Devices Figure 4-4 shows how to connect a ground-referenced signal source to a channel on an isolated S Series device.
Chapter 4 Analog Input With these types of connections, the instrumentation amplifier rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the device ground, shown as Vcm in these figures. Common-Mode Signal Rejection Considerations The instrumentation amplifier can reject any voltage caused by ground potential differences between the signal source and the device.
Chapter 4 Analog Input Figure 4-5 shows a bias resistor connected between AI 0 – and the floating signal source ground. This resistor provides a return path for the bias current. A value of 10 kΩ to 100 kΩ is usually sufficient. If you do not use the resistor and the source is truly floating, the source is not likely to remain within the common-mode signal range of the instrumentation amplifier, so the instrumentation amplifier saturates, causing erroneous readings.
Chapter 4 • Analog Input High Source Impedance—For larger source impedances, this connection leaves the DIFF signal path significantly off balance. Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground. Hence, this noise appears as a DIFF-mode signal instead of a common-mode signal, and the instrumentation amplifier does not reject it.
Chapter 4 Analog Input Minimize noise pickup and maximize measurement accuracy by taking the following precautions. • Use differential AI connections to reject common-mode noise. • Use individually shielded, twisted-pair wires to connect AI signals to the device. With this type of wire, the signals attached to the AI + and AI – inputs are twisted together and then covered with a shield. You then connect this shield only at one point to the signal source ground.
Chapter 4 Analog Input Analog Input Timing Signals An acquisition with posttrigger data allows you to view data that is acquired after a trigger event is received. A typical posttrigger DAQ sequence is shown in Figure 4-7. The sample counter is loaded with the specified number of posttrigger samples, in this example, five. The value decrements with each pulse on AI Sample Clock (ai/SampleClock), until the value reaches zero and all desired samples have been acquired.
Chapter 4 Analog Input If an AI Reference Trigger (ai/ReferenceTrigger) pulse occurs before the specified number of pretrigger samples are acquired, the trigger pulse is ignored. Otherwise, when the AI Reference Trigger pulse occurs, the sample counter value decrements until the specified number of posttrigger samples have been acquired. For more information about start and reference triggers, refer to the Analog Input Triggering section.
Chapter 4 Analog Input Several other internal signals can be routed to AI Sample Clock through RTSI. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information. Using an External Source Use one of the following external signals as the source of AI Sample Clock: • PFI <0..15> • RTSI <0..
Chapter 4 Analog Input Figure 4-9 shows the relationship of AI Sample Clock to AI Start Trigger. AI Sample Clock Timebase AI Start Trigger AI Sample Clock Delay From Start Trigger Figure 4-9. AI Sample Clock and AI Start Trigger AI Sample Clock Timebase Signal You can route any of the following signals to be the AI Sample Clock Timebase (ai/SampleClockTimebase) signal: • 20 MHz Timebase • 100 kHz Timebase • PXI_CLK10 • RTSI <0..7> • PFI <0..
Chapter 4 Analog Input Using an Internal Source One of the following internal signals can drive AI Convert Clock: • AI Convert Clock Timebase (divided down) • Counter n Internal Output A programmable internal counter divides down the AI Convert Clock Timebase to generate AI Convert Clock. The counter is started by AI Sample Clock and continues to count down to zero, produces an AI Convert Clock, reloads itself, and repeats the process until the sample is finished.
Chapter 4 Analog Input AI Hold Complete Event Signal The AI Hold Complete Event (ai/HoldCompleteEvent) signal generates a pulse after each A/D conversion begins. You can route ai/HoldCompleteEvent out to any PFI <0..15> or RTSI <0..7> terminal. The polarity of ai/HoldCompleteEvent is software-selectable, but is typically configured so that a low-to-high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed.
Chapter 4 Analog Input Using an Analog Source When you use an analog trigger source, the acquisition begins on the first rising edge of the Analog Comparison Event signal. Routing AI Start Trigger to an Output Terminal You can route AI Start Trigger out to any PFI <0..15> or RTSI <0..7> terminal. The output is an active high pulse. All PFI terminals are configured as inputs by default. The device also uses AI Start Trigger to initiate pretriggered DAQ operations.
Chapter 4 Analog Input When the reference trigger occurs, the DAQ device continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired. Figure 4-10 shows the final buffer. Reference Trigger Pretrigger Samples Complete Buffer Figure 4-10. Reference Trigger Final Buffer Using a Digital Source To use AI Reference Trigger with a digital source, specify a source and an edge. The source can be any of the following signals: • PFI <0..15> • RTSI <0..
Chapter 4 Analog Input Getting Started with AI Applications in Software You can use the S Series device in the following analog input applications: • Simultaneous sampling • Single-point analog input • Finite analog input • Continuous analog input You can perform these applications through DMA, interrupt, or programmed I/O data transfer mechanisms. Some of the applications also use start and reference pause triggers.
5 Analog Output Figure 5-1 shows the analog output circuitry of a non-isolated S Series (NI 6124) device. DAC0 AO 0 AO FIFO AO 1 AO Data DAC1 AO Sample Clock Figure 5-1. Non-Isolated S Series Device Analog Output Block Diagram Figure 5-2 shows the analog output circuitry of an isolated S Series (NI 6154) device. Isolation Barrier AO+ DAC0 Digital Isolators AO FIFO AO Data AO Sample Clock Figure 5-2.
Chapter 5 Analog Output The main blocks featured in the S Series analog output circuitry are as follows: • AO FIFO—The AO FIFO enables analog output waveform generation. It is a first-in-first-out (FIFO) memory buffer between the computer and the DACs that allows you to download all the points of a waveform to your board without host computer interaction. • AO Sample Clock—The DAC reads a sample from the FIFO with every cycle of the AO Sample Clock signal and generates the AO voltage.
Chapter 5 • Analog Output Hardware-Timed Generations—With a hardware-timed generation, a digital hardware signal controls the rate of the generation. This signal can be generated internally on your device or provided externally. Hardware-timed generations have several advantages over software-timed generations: – The time between samples can be much shorter. – The timing between samples can be deterministic. – Hardware-timed generations can use hardware triggering.
Chapter 5 Analog Output With FIFO regeneration, the entire buffer is downloaded to the FIFO and regenerated from there. After the data is downloaded, new data cannot be written to the FIFO. To use FIFO regeneration, the entire buffer must fit within the FIFO size. The advantage of using FIFO regeneration is that it does not require communication with the main host memory after the operation is started, thereby preventing any problems that may occur due to excessive bus traffic.
Chapter 5 Analog Output Figure 5-3 shows how AO 0 and AO 1 are wired on a non-isolated S Series device. AO 0 Channel 0 + Load VOUT 0 – AO GND – Load VOUT 1 AO 1 + Channel 1 Analog Output Channels Non-Isolated S Series Device Figure 5-3. Analog Output Connections for Non-Isolated S Series Devices Figure 5-4 shows how AO 0 is wired on an isolated S Series device. Isolation Barrier AO+ DAC + Load Analog Output Channel VOUT – Digital Isolators AO– Isolated S Series Device Figure 5-4.
Chapter 5 Analog Output Waveform Generation Timing Signals There is one AO Sample Clock that causes all AO channels to update simultaneously. Figure 5-5 summarizes the timing and routing options provided by the analog output timing engine. RTSI 7 Master Timebase Onboard Clock PFI 0–9, RTSI 0–6 ao/SampleClock Timebase ÷200 20 MHz Timebase Ctr1InternalOutput PFI 0–9, RTSI 0–6 Onboard Clock Divisor ao/SampleClock ÷ Figure 5-5.
Chapter 5 Analog Output Using an External Source You can use a signal connected to any PFI or RTSI <0..6> pin as the source of AO Sample Clock. Figure 5-6 shows the timing requirements of the AO Sample Clock source. tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 5-6. AO Sample Clock Timing Requirements Routing AO Sample Clock Signal to an Output Terminal You can route ao/SampleClock (as an active low signal) out to any PFI <0..15> or RTSI <0..7> terminal.
Chapter 5 Analog Output Figure 5-7 shows the relationship of the AO Sample Clock signal to the AO Start Trigger signal. AO Sample Clock Timebase AO Start Trigger AO Sample Clock Delay From Start Trigger Figure 5-7. AO Sample Clock and AO Start Trigger AO Sample Clock Timebase Signal You can select any PFI or RTSI pin as well as many other internal signals as the AO Sample Clock Timebase (ao/SampleClockTimebase) signal. This signal is not available as an output on the I/O connector.
Chapter 5 Analog Output Figure 5-8 shows the timing requirements for the AO Sample Clock Timebase signal. tp tw tw tp = 50 ns minimum tw = 23 ns minimum Figure 5-8. AO Sample Clock Timebase Timing Requirements The maximum allowed frequency is 20 MHz, with a minimum pulse width of 10 ns high or low. There is no minimum frequency. Unless you select an external source, either the 20MHzTimebase or 100kHzTimebase generates the AO Sample Clock Timebase signal.
Chapter 5 Analog Output Figure 5-9 shows the timing requirements of the AO Start Trigger digital source. tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 5-9. AO Start Trigger Timing Requirements Using an Analog Source When you use an analog trigger source, the waveform generation begins on the first rising edge of the Analog Comparison Event signal. For more information, refer to the Triggering with an Analog Source section of Chapter 11, Triggering.
Chapter 5 Analog Output Using a Digital Source To use ao/Pause Trigger, specify a source and a polarity. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information. Also, specify whether the samples are paused when AO Pause Trigger is at a logic high or low level.
6 Digital I/O Refer to one of the following sections, depending on your device: • Digital I/O for Non-Isolated Devices—NI 6124 devices have eight lines of bidirectional DIO lines on Port 0, and 16 PFI signals that can function as static DIO lines. • Digital I/O for Isolated Devices—NI 6154 devices have six bank-isolated digital inputs and four bank-isolated digital outputs. Digital I/O for Non-Isolated Devices (NI 6124 Only) NI 6124 devices contain eight lines of bidirectional DIO lines on Port 0.
Chapter 6 Digital I/O Figure 6-1 shows the circuitry of one DIO line. Each DIO line is similar. The following sections provide information about the various parts of the DIO circuit. DO Waveform Generation FIFO DO Sample Clock Static DO Buffer I/O Protection P0.x DO.x Direction Control Weak Pull-Down Static DI DI Waveform Measurement FIFO DI Sample Clock DI Change Detection Figure 6-1. Non-Isolated S Series Digital I/O Circuitry The DIO terminals are named P0.<0..7> on the device I/O connector.
Chapter 6 Digital I/O Digital Waveform Triggering for Non-Isolated Devices (NI 6124 Only) NI 6124 devices do not have an independent DI or DO Start Trigger for digital waveform acquisition or generation. To trigger a DI or DO operation, first select a signal to be the source of DI Sample Clock or DO Sample Clock. Then, generate a trigger that initiates pulses on the source signal. The method for generating this trigger depends on which signal is the source of DI Sample Clock or DO Sample Clock.
Chapter 6 Digital I/O You can configure each DIO line to be an output, a static input, or a digital waveform acquisition input. DI Sample Clock Signal (NI 6124 Only) Use the DI Sample Clock (di/SampleClock) signal to sample the P0.<0..7> terminals and store the result in the DI waveform acquisition FIFO. These S Series devices do not have the ability to divide down a timebase to produce an internal DI Sample Clock for digital waveform acquisition.
Chapter 6 • PXI_STAR • Analog Comparison Event (an analog trigger) Digital I/O You can sample data on the rising or falling edge of DI Sample Clock. Routing DI Sample Clock to an Output Terminal You can route DI Sample Clock out to any PFI terminal. The PFI circuitry inverts the polarity of DI Sample Clock before driving the PFI terminal. Digital Waveform Generation for Non-Isolated Devices (NI 6124 Only) You can generate digital waveforms on the Port 0 DIO lines.
Chapter 6 Digital I/O Using an Internal Source To use DO Sample Clock with an internal source, specify the signal source and the polarity of the signal. The source can be any of the following signals: • AI Sample Clock (ai/SampleClock) • AI Convert Clock (ai/ConvertClock) • AO Sample Clock (ao/SampleClock) • Counter n Internal Output • Frequency Output • DI Change Detection Output Several other internal signals can be routed to DO Sample Clock through RTSI.
Chapter 6 Digital I/O I/O Protection for Non-Isolated Devices (NI 6124 Only) Each DIO and PFI signal is protected against overvoltage, undervoltage, and overcurrent conditions as well as ESD events. However, you should avoid these fault conditions by following these guidelines: • If you configure a PFI or DIO line as an output, do not connect it to any external signal source, ground, or power supply.
Chapter 6 Digital I/O DI Change Detection for Non-Isolated Devices (NI 6124 Only) You can configure the DAQ device to detect changes in the DIO signals. Figure 6-3 shows a block diagram of the DIO change detection circuitry. P0.0 Synch Enable Enable Change Detection Event P0.7 Synch Enable Enable Figure 6-3. DI Change Detection You can enable the DIO change detection circuitry to detect rising edges, falling edges, or either edge individually on each DIO line.
Chapter 6 Digital I/O The Change Detection Event signal also can be used to detect changes on digital output events. DI Change Detection Applications for Non-Isolated Devices (NI 6124 Only) The DIO change detection circuitry can interrupt a user program when one of several DIO signals changes state. You also can use the output of the DIO change detection circuitry to trigger a DI or counter acquisition on the logical OR of several digital signals.
Chapter 6 Digital I/O +5 V LED PFI <4..7>/ P1.<4..7> PFI <0..3>/ P1.<0..3> TTL Signal +5 V Switch D GND I/O Connector Non-Isolated S Series Device Figure 6-4. Digital I/O Connections Caution Exceeding the maximum input voltage ratings, which are listed in the specifications document for each non-isolated DAQ-STC2 S Series device, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections.
Chapter 6 Digital I/O Digital I/O for Isolated Devices (NI 6154 Only) S Series isolated devices contain ten lines of unidirectional DIO signals. The digital I/O port is comprised of six digital inputs and four digital outputs, all bank-isolated. Each digital line has the functionality of a PFI line. Input PFI lines can be used to input trigger signals to the different function modules of the DAQ-STC2 ASIC. The PFI pins also can be used as static digital inputs when not used to input triggers.
Chapter 6 Digital I/O I/O Protection for Isolated Devices (NI 6154 Only) Each DIO and PFI signal is protected against over-voltage, under-voltage, and over-current conditions as well as ESD events. However, you should avoid these fault conditions by following these guidelines: • Do not connect any DO line to any external signal source, ground signal, or power supply. • Understand the current requirements of the load connected to DO signals.
Chapter 6 Digital I/O +5 V Isolation Barrier LED PFI <6..9>/P1.<0..3> Digital Isolators TTL Signal PFI <0..5>/P0.<0..5> +5 V Switch D GND I/O Connector Isolated S Series Device Figure 6-6. Isolated S Series Device Digital I/O Signal Connections Caution Exceeding the maximum input voltage ratings, which are listed in the NI 6154 Specifications, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections.
7 Counters S Series devices have two general-purpose 32-bit counter/timers and one frequency generator, as shown in Figure 7-1. The general-purpose counter/timers can be used for many measurement and pulse generation applications.
Chapter 7 Counters The counters have seven input signals, although in most applications only a few inputs are used. For information about connecting counter signals, refer to the Default Counter/Timer Pinouts section. Counter Input Applications Counting Edges In edge counting applications, the counter counts edges on its Source after the counter is armed. You can configure the counter to count rising or falling edges on its Source input. You also can control the direction of counting (up or down).
Chapter 7 Counters Counter Armed Pause Trigger (Pause When Low) SOURCE Counter Value 0 0 1 2 3 4 5 Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger Buffered (Sample Clock) Edge Counting With buffered edge counting (edge counting using a sample clock), the counter counts the number of edges on the Source input after the counter is armed. The value of the counter is sampled on each active edge of a sample clock. A DMA controller transfers the sampled values to host memory.
Chapter 7 Counters Controlling the Direction of Counting In edge counting applications, the counter can count up or down. You can configure the counter to do the following: • Always count up • Always count down • Count up when the Counter n B input is high; count down when it is low For information about connecting counter signals, refer to the Default Counter/Timer Pinouts section.
Chapter 7 Counters Figure 7-5 shows an example of a single pulse-width measurement. GATE SOURCE 0 Counter Value 1 HW Save Register 2 2 Figure 7-5. Single Pulse-Width Measurement Buffered Pulse-Width Measurement Buffered pulse-width measurement is similar to single pulse-width measurement, but buffered pulse-width measurement takes measurements over multiple pulses. The counter counts the number of edges on the Source input while the Gate input remains active.
Chapter 7 Counters condition is not met, consider using duplicate count prevention, described in the Duplicate Count Prevention section. For information about connecting counter signals, refer to the Default Counter/Timer Pinouts section. Period Measurement In period measurements, the counter measures a period on its Gate input signal after the counter is armed. You can configure the counter to measure the period between two rising edges or two falling edges of the Gate input signal.
Chapter 7 Counters Buffered Period Measurement Buffered period measurement is similar to single period measurement, but buffered period measurement measures multiple periods. The counter counts the number of rising (or falling) edges on the Source input between each pair of active edges on the Gate input. At the end of each period on the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory. The counter begins when it is armed.
Chapter 7 Counters You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges occurring on the Source input between two edges of the Gate signal. You can calculate the semi-period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter.
Chapter 7 Counters For information about connecting counter signals, refer to the Default Counter/Timer Pinouts section. Frequency Measurement You can use the counters to measure frequency in several different ways. You can choose one of the following methods depending on your application: • Method 1: Measure Low Frequency with One Counter—In this method, you measure one period of your signal using a known timebase. This method is good for low frequency signals.
Chapter 7 Counters You can configure the counter to make K + 1 buffered period measurements. Recall that the first period measurement in the buffer should be discarded. Average the remaining K period measurements to determine the average period of F1. The frequency of F1 is the inverse of the average period. Figure 7-11 illustrates this method. T1 F1 Gate Ft Source Intervals Measured T2 … TK F1 1 2 ...N11... ...N2 … 1... ...
Chapter 7 Counters Figure 7-12 illustrates this method. Another option would be to measure the width of a known period instead of a known pulse. Width of Pulse (T) Pulse Pulse Gate 1 F1 Source 2 … N F1 Pulse-Width Measurement Width of T = Pulse N F1 Frequency of F1 = N T Figure 7-12. Method 2 • © National Instruments Corporation Method 3: Measure Large Range of Frequencies Using Two Counters—By using two counters, you can accurately measure a signal that might be high or low frequency.
Chapter 7 Counters You can route the signal to measure to the Source input of Counter 0, as shown in Figure 7-13. Assume this signal to measure has frequency F1. Configure Counter 0 to generate a single pulse that is the width of N periods of the source input signal. Signal to Measure (F1) SOURCE OUT COUNTER 0 Signal of Known Frequency (F2) SOURCE OUT COUNTER 1 GATE CTR_0_SOURCE (Signal to Measure) CTR_0_OUT (CTR_1_GATE) 0 1 2 3 … N Interval to Measure CTR_1_SOURCE Figure 7-13.
Chapter 7 • Counters Method 1 uses only one counter. It is a good method for many applications. However, the accuracy of the measurement decreases as the frequency increases. Consider a frequency measurement on a 50 kHz signal using an 80 MHz Timebase. This frequency corresponds to 1600 cycles of the 80 MHz Timebase. Your measurement may return 1600 ± 1 cycles depending on the phase of the signal with respect to the timebase.
Chapter 7 Counters Table 7-2 summarizes some of the differences in methods of measuring frequency. Table 7-2. Frequency Measurement Method Comparison Method Number of Counters Used Number of Measurements Returned Measures High Frequency Signals Accurately Measures Low Frequency Signals Accurately 1 1 1 Poor Good 1b 1 Many Fair Good 2 1 or 2 1 Good Poor 3 2 1 Good Good For information about connecting counter signals, refer to the Default Counter/Timer Pinouts section.
Chapter 7 Counters Figure 7-14 shows a quadrature cycle and the resulting increments and decrements for X1 encoding. When channel A leads channel B, the increment occurs on the rising edge of channel A. When channel B leads channel A, the decrement occurs on the falling edge of channel A. Ch A Ch B Counter Value 5 6 7 7 5 6 Figure 7-14.
Chapter 7 Counters Channel Z behavior—when it goes high and how long it stays high—differs with quadrature encoder designs. You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B. You must then ensure that channel Z is high during at least a portion of the phase you specify for reload. For instance, in Figure 7-17, channel Z is never high when channel A is high and channel B is low. Thus, the reload must occur in some other phase.
Chapter 7 Counters For information about connecting counter signals, refer to the Default Counter/Timer Pinouts section. Buffered (Sample Clock) Position Measurement With buffered position measurement (position measurement using a sample clock), the counter increments based on the encoding used after the counter is armed. The value of the counter is sampled on each active edge of a sample clock. A DMA controller transfers the sampled values to host memory.
Chapter 7 Counters You can configure the rising or falling edge of the Aux input to be the active edge. You can configure the rising or falling edge of the Gate input to be the active edge. Use this type of measurement to count events or measure the time that occurs between edges on two signals. This type of measurement is sometimes referred to as start/stop trigger measurement, second gate measurement, or A-to-B measurement.
Chapter 7 Counters Figure 7-21 shows an example of a buffered two-signal edge-separation measurement. AUX GATE SOURCE Counter Value 1 2 3 1 3 Buffer 2 3 3 3 1 2 3 3 3 3 Figure 7-21. Buffered Two-Signal Edge-Separation Measurement For information about connecting counter signals, refer to the Default Counter/Timer Pinouts section. Counter Output Applications Simple Pulse Generation Single Pulse Generation The counter can output a single pulse.
Chapter 7 Counters Figure 7-22 shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source). Counter Armed SOURCE OUT Figure 7-22. Single Pulse Generation Single Pulse Generation with Start Trigger The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal. The pulse appears on the Counter n Internal Output signal of the counter. You can route the Start Trigger signal to the Gate input of the counter.
Chapter 7 Counters You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of each pulse. You also can specify the pulse width. The delay and pulse width are measured in terms of a number of active edges of the Source input. The counter ignores the Gate input while a pulse generation is in progress. After the pulse generation is finished, the counter waits for another Start Trigger signal to begin another pulse generation.
Chapter 7 Counters You also can use the Gate input of the counter as a Pause Trigger (if it is not used as a Start Trigger). The counter pauses pulse generation when the Pause Trigger is active. Figure 7-25 shows a continuous pulse train generation (using the rising edge of Source). SOURCE OUT Counter Armed Figure 7-25. Continuous Pulse Train Generation Continuous pulse train generation is sometimes called frequency division.
Chapter 7 Counters Frequency Generation You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit. Using the Frequency Generator The frequency generator can output a square wave at many different frequencies. The frequency generator is independent of the two general-purpose 32-bit counter/timer modules on S Series devices. Figure 7-27 shows a block diagram of the frequency generator.
Chapter 7 Counters Frequency Output can be routed out to any PFI <0..15> or RTSI <0..7> terminal. All PFI terminals are set to high-impedance at startup. The FREQ OUT signal also can be routed to DO Sample Clock and DI Sample Clock. In software, program the frequency generator as you would program one of the counters for pulse train generation. For information about connecting counter signals, refer to the Default Counter/Timer Pinouts section.
Chapter 7 Counters The waveform thus produced at the counter’s output can be used to provide timing for undersampling applications where a digitizing system can sample repetitive waveforms that are higher in frequency than the Nyquist frequency of the system. Figure 7-29 shows an example of pulse generation for ETS; the delay from the trigger to the pulse increases after each subsequent Gate active edge. GATE OUT D2 = D1 + ΔD D1 D3 = D1 + 2ΔD Figure 7-29.
Chapter 7 Counters Counter n Source Signal The selected edge of the Counter n Source signal increments and decrements the counter value depending on the application the counter is performing. Table 7-3 lists how this terminal is used in various applications. Table 7-3.
Chapter 7 Counters Routing Counter n Source to an Output Terminal You can route Counter n Source out to any PFI <0..15> or RTSI <0..7> terminal. All PFIs are set to high-impedance at startup. Counter n Gate Signal The Counter n Gate signal can perform many different operations depending on the application including starting and stopping the counter, and saving the counter contents. Routing a Signal to Counter n Gate Each counter has independent input selectors for the Counter n Gate signal.
Chapter 7 Counters Counter n Aux Signal The Counter n Aux signal indicates the first edge in a two-signal edge-separation measurement. Routing a Signal to Counter n Aux Each counter has independent input selectors for the Counter n Aux signal. Any of the following signals can be routed to the Counter n Aux input: • RTSI <0..7> • PFI <0..
Chapter 7 Counters Counter n Up_Down Signal Counter n Up_Down is another name for the Counter n B signal. Counter n HW Arm Signal The Counter n HW Arm signal enables a counter to begin an input or output function. To begin any counter input or output function, you must first enable, or arm, the counter. In some applications, such as buffered semi-period measurement, the counter begins counting when it is armed.
Chapter 7 Counters With pulse or pulse train generation tasks, the counter drives the pulse(s) on the Counter n Internal Output signal. The Counter n Internal Output signal can be internally routed to be a counter/timer input or an “external” source for AI, AO, DI, or DO timing signals. Routing Counter n Internal Output to an Output Terminal You can route Counter n Internal Output to any PFI <0..15> or RTSI <0..7> terminal. All PFIs are set to high-impedance at startup.
Chapter 7 Counters Counter Triggering Counters support three different triggering actions: • Arm Start Trigger—To begin any counter input or output function, you must first enable, or arm, the counter. Software can arm a counter or configure counters to be armed on a hardware signal. Software calls this hardware signal the Arm Start Trigger. Internally, software routes the Arm Start Trigger to the Counter n HW Arm input of the counter.
Chapter 7 Counters Other Counter Features Cascading Counters You can internally route the Counter n Internal Output and Counter n TC signals of each counter to the Gate inputs of the other counter. By cascading two counters together, you can effectively create a 64-bit counter. By cascading counters, you also can enable other applications.
Chapter 7 Counters The filter setting for each input can be configured independently. On power up, the filters are disabled. Figure 7-30 shows an example of a low to high transition on an input that has its filter set to 125 ns (N = 5). RTSI, PFI, or PXI_STAR Terminal 1 Filter Clock (40 MHz) 1 2 3 4 1 2 3 4 5 Filtered input goes high when terminal is sampled high on five consecutive filter clocks. Filtered Input Figure 7-30.
Chapter 7 Counters External Signal Prescaler Rollover (Used as Source by Counter) Counter Value 0 1 Figure 7-31. Prescaling Prescaling is intended to be used for frequency measurement where the measurement is made on a continuous, repetitive signal. The prescaling counter cannot be read; therefore, you cannot determine how many edges have occurred since the previous rollover. Prescaling can be used for event counting provided it is acceptable to have an error of up to seven (or one).
Chapter 7 Counters Example Application That Works Correctly (No Duplicate Counting) Figure 7-32 shows an external buffered signal as the period measurement Source. Rising Edge of Gate Counter detects rising edge of Gate on the next rising edge of Source. Gate Source Counter Value 6 7 1 2 1 7 Buffer 2 7 Figure 7-32. Duplicate Count Prevention Example On the first rising edge of the Gate, the current count of 7 is stored.
Chapter 7 Counters Example Application That Works Incorrectly (Duplicate Counting) In Figure 7-33, after the first rising edge of Gate, no Source pulses occur, so the counter does not write the correct data to the buffer. No Source edge, so no value written to buffer. Gate Source Counter Value 6 7 1 7 Buffer Figure 7-33.
Chapter 7 Counters Even if the Source pulses are long, the counter increments only once for each Source pulse. Normally, the counter value and Counter n Internal Output signals change synchronously to the Source signal. With duplicate count prevention, the counter value and Counter n Internal Output signals change synchronously to the 80 MHz Timebase. Note that duplicate count prevention should only be used if the frequency of the Source signal is 20 MHz or less.
Chapter 7 Counters In DAQmx, the device uses 80 MHz source mode if you perform the following: • Perform a position measurement • Select duplicate count prevention Otherwise, the mode depends on the signal that drives Counter n Source. Table 7-5 describes the conditions for each mode. Table 7-5.
Chapter 7 Counters Other Internal Source Mode In other internal source mode, the device synchronizes signals on the falling edge of the source, and counts on the following rising edge of the source, as shown in Figure 7-36. Source Synchronize Count Figure 7-36. Other Internal Source Mode External Source Mode In external source mode, the device generates a delayed Source signal by delaying the Source signal by several nanoseconds.
8 Programmable Function Interfaces (PFI) Refer to one of the following sections, depending on your device: • PFI for Non-Isolated Devices—NI 6124 devices have 16 PFI pins in addition to eight lines of bidirectional DIO signals. • PFI for Isolated Devices—NI 6154 devices have 10 equivalent directional PFI pins that can be independently configured as an input or output. PFI for Non-Isolated Devices (NI 6124 Only) Non-isolated S Series devices have 16 Programmable Function Interface (PFI) signals.
Chapter 8 Programmable Function Interfaces (PFI) Each PFI input also has a programmable debouncing filter. Figure 8-1 shows the circuitry of one PFI line. Each PFI line is similar. Timing Signals Static DO Buffer I/O Protection PFI x/P1 or PFI x/P2 Direction Control Static DI Weak Pull-Down To Input Timing Signal Selectors PFI Filters Figure 8-1.
Chapter 8 Programmable Function Interfaces (PFI) Figure 8-2 shows the circuitry of one PFI input line. Each PFI line is similar. Isolation Barrier Static DI PFI <0..5>/P0.<0..5> I/O Protection Digital Isolators PFI Filters To Input Timing Signal Selectors Figure 8-2. PFI Input Circuitry on Isolated S Series Devices Each PFI <6..9>/P1.<0..3> can be configured as a timing output signal from AI or counter/timer functions or a static digital output. Figure 8-3 shows the circuitry of one PFI output line.
Chapter 8 Programmable Function Interfaces (PFI) Using PFI Terminals as Timing Input Signals Use PFI terminals to route external timing signals to many different S Series functions.
Chapter 8 Programmable Function Interfaces (PFI) • AO Start Trigger (ao/StartTrigger) • Counter n Source • Counter n Gate • Counter n Internal Output • Frequency Output • PXI_STAR • RTSI <0..7> • (NI 6124 Only) Analog Comparison Event • (NI 6124 Only) Change Detection Event • (NI 6124 Only) DI Sample Clock* (di/SampleClock) • (NI 6124 Only) DO Sample Clock* (do/SampleClock) Note Signals with a * are inverted before being driven to a terminal; that is, these signals are active low.
Chapter 8 Programmable Function Interfaces (PFI) Connecting PFI Input Signals All PFI input connections are referenced to D GND. Figure 8-4 shows this reference, and how to connect an external PFI 0 source and an external PFI 2 source to two PFI terminals. PFI 0 PFI 2 PFI 0 Source PFI 2 Source D GND I/O Connector S Series Device Figure 8-4. PFI Input Signals Connections PFI Filters You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal.
Chapter 8 Programmable Function Interfaces (PFI) Assume that an input terminal has been low for a long time. The input terminal then changes from low to high, but glitches several times. When the filter clock has sampled the signal high on N consecutive edges, the low to high transition is propagated to the rest of the circuit. The value of N depends on the filter setting; refer to Table 8-1. Table 8-1.
Chapter 8 Programmable Function Interfaces (PFI) I/O Protection Each DIO and PFI signal is protected against overvoltage, undervoltage, and overcurrent conditions as well as ESD events. However, you should avoid these fault conditions by following these guidelines: • If you configure a PFI or DIO line as an output, do not connect it to any external signal source, ground, or power supply.
Chapter 8 • Programmable Function Interfaces (PFI) NI 6154 Devices—By default, the digital output lines (P1.<0..3>/PFI <6..9>) are disabled (high impedance) at power up. Software can configure the board to power up with the entire port enabled or disabled; you cannot enable individual lines. If the port powers up enabled, you also can configure each line individually to power up as 1 or 0. Refer to the NI-DAQmx Help or the LabVIEW Help in version 8.
9 Digital Routing and Clock Generation The digital routing circuitry has the following main functions: • Manages the flow of data between the bus interface and the acquisition/generation sub-systems (analog input, analog output, digital I/O, and the counters). The digital routing circuitry uses FIFOs (if present) in each sub-system to ensure efficient data movement. • Routes timing and control signals. The acquisition/generation sub-systems use these signals to manage acquisitions and generations.
Chapter 9 Digital Routing and Clock Generation 80 MHz Timebase The 80 MHz Timebase can be used as the Source input to the 32-bit general-purpose counter/timers. The 80 MHz Timebase is generated from the following sources: • Onboard oscillator • External signal (by using the external reference clock) 20 MHz Timebase The 20 MHz Timebase normally generates many of the AI and AO timing signals. The 20 MHz Timebase also can be used as the Source input to the 32-bit general-purpose counter/timers.
Chapter 9 Digital Routing and Clock Generation 10 MHz Reference Clock The 10 MHz reference clock can be used to synchronize other devices to your S Series device. The 10 MHz reference clock can be routed to the RTSI <0..7> terminals. Other devices connected to the RTSI bus can use this signal as a clock input. The 10 MHz reference clock is generated by dividing down the onboard oscillator.
Chapter 9 Digital Routing and Clock Generation Real-Time System Integration (RTSI) Real-Time System Integration (RTSI) is a set of bused signals among devices that allows you to do the following: • Use a common clock (or timebase) to drive the timing engine on multiple devices • Share trigger signals between devices Many National Instruments DAQ, motion, vision, and CAN devices support RTSI. In a PCI system, the RTSI bus consists of the RTSI bus interface and a ribbon cable.
Chapter 9 Digital Routing and Clock Generation Table 9-1. RTSI Signals (Continued) Terminal RTSI Bus Signal 32 RTSI 6 34 RTSI 7 Terminal 34 Terminal 33 Terminal 2 Terminal 1 Figure 9-2. S Series PCI Device RTSI Pinout Using RTSI as Outputs RTSI <0..7> are bidirectional terminals.
Chapter 9 Digital Routing and Clock Generation Note • Counter n Source, Gate, Z, Internal Output • Change Detection Event • Analog Comparison Event • FREQ OUT • PFI <0..5> Signals with a * are inverted before being driven on the RTSI terminals. Using RTSI Terminals as Timing Input Signals You can use RTSI terminals to route external timing signals to many different S Series functions.
Chapter 9 Digital Routing and Clock Generation The following is an example of low to high transitions of the input signal. High to low transitions work similarly. Assume that an input terminal has been low for a long time. The input terminal then changes from low to high, but glitches several times. When the filter clock has sampled the signal high on N consecutive edges, the low to high transition is propagated to the rest of the circuit. The value of N depends on the filter setting; refer to Table 9-2.
Chapter 9 Digital Routing and Clock Generation Refer to the KnowledgeBase document, Digital Filtering with M Series and CompactDAQ, for more information about digital filters and counters. To access this KnowledgeBase, go to ni.com/info and enter the info code rddfms. PXI Clock and Trigger Signals (NI 6124 Only) PXI clock and trigger signals are only available on PXI and PXI Express devices.
Chapter 9 Digital Routing and Clock Generation An S Series device receives the Star Trigger signal (PXI_STAR) from a Star Trigger controller. PXI_STAR can be used as an external source for many AI, AO, and counter signals. An S Series device is not a Star Trigger controller. An S Series device may be used in the first peripheral slot of a PXI system, but the system will not be able to use the Star Trigger feature.
Chapter 9 Digital Routing and Clock Generation The filter setting for each input can be configured independently. On power up, the filters are disabled. Figure 9-4 shows an example of a low to high transition on an input that has its filter set to 125 ns (N = 5). RTSI, PFI, or PXI_STAR Terminal 1 Filter Clock (40 MHz) 1 2 3 4 1 2 3 4 5 Filtered input goes high when terminal is sampled high on five consecutive filter clocks. Filtered Input Figure 9-4.
10 Bus Interface Each S Series device is designed on a complete hardware architecture that is deployed on the following platforms: • PCI • PXI Express Using NI-DAQmx driver software, you have the flexibility to change hardware platforms and operating systems with little or no change to software code. MITE and DAQ-PnP All S Series devices are jumperless for complete plug-and-play operation. The operating system automatically assigns the base address, interrupt levels, and other resources.
Chapter 10 Bus Interface Data Transfer Methods There are three primary ways to transfer data across the PCI bus are as follows: • Direct Memory Access (DMA)—DMA is a method to transfer data between the device and computer memory without the involvement of the CPU. This method makes DMA the fastest available data transfer method. National Instruments uses DMA hardware and software technology to achieve high throughput rates and to increase system utilization.
11 Triggering A trigger is a signal that causes a device to perform an action, such as starting an acquisition. You can program your DAQ device to generate triggers on any of the following: • A software command • A condition on an external digital signal • A condition on an external analog signal You can also program your DAQ device to perform an action in response to a trigger.
Chapter 11 Triggering Figure 11-1 shows a falling-edge trigger. 5V Digital Trigger 0V Falling edge initiates acquisition Figure 11-1. Falling-Edge Trigger You can also program your DAQ device to perform an action in response to a trigger from a digital source. The action can affect the following: • analog input acquisitions • analog output generation • counter behavior Triggering with an Analog Source (NI 6124 Only) Some S Series devices can generate a trigger on an analog signal.
Chapter 11 Triggering Analog Input Channel (NI 6124 Only) You can select any analog input channel to drive the instrumentation amplifier. The instrumentation amplifier amplifies the signal as determined by the input mode and the input polarity and range. The output of the instrumentation amplifier then drives the analog trigger detection circuit. By using the instrumentation amplifier, you can trigger on very small voltage changes in the input signal.
Chapter 11 Triggering In below-level analog triggering mode, shown in Figure 11-3, the trigger is generated when the signal value is less than Level. Level Analog Comparison Event Figure 11-3. Below-Level Analog Triggering Mode In above-level analog triggering mode, shown in Figure 11-4, the trigger is generated when the signal value is greater than Level. Level Analog Comparison Event Figure 11-4.
Chapter 11 Triggering For the trigger to assert, the signal must first be below the low threshold, then go above the high threshold. The trigger stays asserted until the signal returns below the low threshold. The output of the trigger detection circuitry is the internal Analog Comparison Event signal, as shown in Figure 11-5.
Chapter 11 Triggering • Analog Window Triggering—An analog window trigger occurs when an analog signal either passes into (enters) or passes out of (leaves) a window defined by two voltage levels. Specify the levels by setting the window Top value and the window Bottom value. Figure 11-7 demonstrates a trigger that asserts when the signal enters the window. Top Bottom Analog Comparison Event Figure 11-7.
A Device-Specific Information This appendix includes device-specific information about the following S Series devices: • NI 6124 • NI 6154 NI 6124 The NI 6124 is a Plug-and-Play, multifunction analog, digital, and timing I/O device for PXI Express bus computers.
Appendix A Device-Specific Information The AO channels do not have analog or digital filtering hardware and do produce images in the frequency domain related to the update rate. Note NI 6124 I/O Connector Pinout Figure A-1 shows the pin assignments for the 68-pin connector on the NI 6124. AI 0 + AI 0 GND AI 1 – AI 2 + AI 2 GND AI 3 – NC NC NC NC NC NC NC AO GND AO GND D GND P0.0 P0.5 D GND P0.2 P0.7 P0.3 PFI 11/P2.3 PFI 10/P2.2 D GND PFI 2/P1.2 PFI 3/P1.3 PFI 4/P1.4 PFI 13/P2.5 PFI 15/P2.7 PFI 7/P1.
Appendix A Device-Specific Information Table A-1.
Appendix A Device-Specific Information NI 6124 Block Diagram Figure A-2 shows the NI 6124 block diagram. Channel Control(0) PGIA Channel Control(1) Cal Relay Control(1) PGIA Channel Control(2) Cal Relay Control(2) 16-Bit SAR AI Data ADC(0) AI Convert(0) 16-Bit SAR AI Data ADC(1) Board Power AI Convert(1) 16-Bit SAR Spartan-3A FPGA AI Data ADC(2) AI Convert(2) 3.
Appendix A Device-Specific Information Using BNCs You can connect BNC cables to your DAQ device using BNC accessories such as the BNC-2110, BNC-2120, and BNC-2090A.
Appendix A Device-Specific Information Mating connectors and a backshell kit for making custom 68-pin cables are available from NI. NI recommends that you use one of the following connectors with the I/O connector on your device. • Honda 68-position, solder cup, female connector • Honda backshell • AMP VHDCI connector For more information about the connectors used for DAQ devices, refer to the KnowledgeBase document, Specifications and Manufacturers for Board Mating Connectors, by going to ni.
Appendix A Device-Specific Information NI 6154 The NI 6154 is an isolated Plug-and-Play multifunction analog, digital, and timing I/O device for PCI bus computers.
Appendix A Device-Specific Information NI 6154 I/O Connector Pinout Figure A-3 shows the pin assignments for the 37-pin I/O connector on the NI 6154. AI 0+ AI 1– NC AI 2+ AI 3– NC AO 0+ AO 1– NC AO 2+ AO 3– NC PFI 1/P0.1 (Input) PFI 2/P0.2 (Input) PFI 4/P0.4 (Input) PFI 5/P0.5 (Input) PFI 7/P1.1 (Output) PFI 8/P1.2 (Output) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 AI 0– NC AI 1+ AI 2– NC AI 3+ AO 0– NC AO 1+ AO 2– NC AO 3+ PFI 0/P0.
Appendix A Device-Specific Information Table A-2. NI 6154 Device Default NI-DAQmx Counter/Timer Pins (Continued) Counter/Timer Signal Default Pin Number (Name) Port CTR 0 B 33 (PFI 2) P0.2 CTR 1 SRC 15 (PFI 3) P0.3 CTR 1 GATE 34 (PFI 4) P0.4 CTR 1 AUX 35 (PFI 5) P0.5 CTR 1 OUT 36 (PFI 7) P1.1 CTR 1 A 15 (PFI 3) P0.3 CTR 1 Z 34 (PFI 4) P0.4 CTR 1 B 35 (PFI 5) P0.
Appendix A Device-Specific Information NI 6154 Block Diagram Figure A-4 shows the NI 6154 block diagram.
Appendix A Device-Specific Information • CB-37FH—37-pin screw terminal block, horizontal, DIN rail mount • CB-37FV—37-pin screw terminal block, vertical, DIN rail mount • TB-37F-37CP—37-pin crimp & poke terminals, shell with strain relief • TB-37F-37SC—37-pin solder cup terminals, shell with strain relief • CB-37F-HVD—37-pin screw terminal block, 150 V CAT II, DIN rail mount To connect your DAQ device to a screw terminal accessory, use one of the following cables: • SH37F-37M-2—37-pin female-to
Appendix A Device-Specific Information The non-isolated ground is connected to the chassis ground of the PC or chassis where the device is installed. The isolated ground is not connected to the chassis ground of the PC or chassis. The isolated ground can be at a higher or lower voltage relative to the non-isolated ground. All analog measurements are made relative to the isolated ground signal. The isolated ground is an input to the NI 6154 device.
Appendix A Device-Specific Information • Improved accuracy—Isolation improves measurement accuracy by physically preventing ground loops. Ground loops, a common source of error and noise, are the result of a measurement system having multiple grounds at different potentials. • Improved safety—Isolation creates an insulation barrier so you can make floating measurements while protecting against large transient voltage spikes.
Technical Support and Professional Services B Visit the following sections of the award-winning National Instruments Web site at ni.com for technical support and professional services: • Support—Technical support at ni.com/support includes the following resources: – Self-Help Technical Resources—For answers and solutions, visit ni.
Appendix B Technical Support and Professional Services • Declaration of Conformity (DoC)—A DoC is our claim of compliance with the Council of the European Communities using the manufacturer’s declaration of conformity. This system affords the user protection for electromagnetic compatibility (EMC) and product safety. You can obtain the DoC for your product by visiting ni.com/certification.
Glossary Symbol Prefix Value p pico 10–12 n nano 10–9 μ micro 10–6 m milli 10–3 k kilo 10 3 M mega 10 6 Symbols ° Degree. > Greater than. < Less than. – Negative of, or minus. Ω Ohms. / Per. % Percent. ± Plus or minus. + Positive of, or plus. A A Amperes—the unit of electric current. A/D Analog-to-digital. AC Alternating current.
Glossary ADC Analog-to-digital converter—an electronic device, often an integrated circuit, that converts an analog voltage to a digital number. ADE Application Development Environment—a software environment incorporating the development, debug, and analysis tools for software development. LabVIEW, Measurement Studio, and Visual Studio are examples. AI 1. Analog input. 2. Analog input channel signal.
Glossary channel 1. Physical—a terminal or pin at which you can measure or generate an analog or digital signal. A single physical channel can include more than one terminal, as in the case of a differential analog input channel or a digital port of eight lines. The name used for a counter physical channel is an exception because that physical channel name is not the name of the terminal where the counter measures or generates the digital signal. 2.
Glossary D D/A Digital-to-analog. DAC Digital-to-analog converter—an electronic device, often an integrated circuit, that converts a digital number into a corresponding analog voltage or current. DAQ See data acquisition (DAQ). DAQ device A device that acquires or generates data and can contain multiple channels and conversion devices. DAQ devices include plug-in devices, PCMCIA cards, and DAQPad devices, which connect to a computer USB or 1394 (FireWire)® port.
Glossary DIP Dual inline package. DMA Direct memory access—a method by which data can be transferred to/from computer memory from/to a device or memory on the bus while the processor does something else. DMA is the fastest method of transferring data to/from computer memory. DNL Differential nonlinearity—a measure in least significant bit of the worst-case deviation of code widths from their ideal value of 1 LSB. DO Digital output.
Glossary FPGA Field-programmable gate array. G gain The factor by which a signal is amplified, often expressed in dB. Gain as a function of frequency is commonly referred to as the magnitude of the frequency response function. grounded signal sources Signal sources with voltage sources that are referenced to a system ground such as the earth or building ground. Also called referenced signal sources. H h Hour. Hz Hertz.
Glossary M m Meter. master A functional part of a MXI/VME/VXIbus device that initiates data transfers on the backplane. A transfer can be either a read or a write. module A board assembly and its associated mechanical parts, front panel, optional shields, and so on. A module contains everything required to occupy one or more slots in a mainframe. SCXI and PXI devices are modules. MSB Most significant bit.
Glossary pd Pull-down. PFI Programmable function interface. PGIA Programmable gain instrumentation amplifier. physical channel See channel. port 1. A communications connection on a computer or a remote controller. 2. A digital port consisting of four or eight lines of digital input and/or output. ppm Parts per million. pu Pull-up. PXI Express PCI Express eXtensions for Instrumentation—The PXI implementation of PCI Express, a scalable full-simplex serial bus standard that operates at 2.
Glossary S s Seconds. S Samples. S/s Samples per second—used to express the rate at which a digitizer or D/A converter or DAQ device samples an analog signal. scatter-gather The term used to describe very high-speed DMA burst-mode transfers that are made only by the bus master, and where noncontiguous blocks of memory are transparently mapped by the controller to appear as a seamless piece of memory.
Glossary tgw Gate pulse width. THD Total harmonic distortion—the ratio of the total rms signal due to harmonic distortion to the overall rms signal, in dB or percent. THD+N Signal-to-THD plus noise—the ratio in decibels of the overall rms signal to the rms signal of harmonic distortion, plus noise introduced. thermocouple A temperature sensor created by joining two dissimilar metals. The junction produces a small voltage as a function of the temperature.
Glossary VIL Volts, input low. Vin Volts in. Vm Measured voltage. VOH Volts, output high. VOL Volts, output low. VOUT Volts out. Vrms Volts, root mean square. Vs Ground-referenced signal source. virtual channel See channel.
Index Numerics signals AI Convert Clock, 4-16 AI Convert Clock Timebase, 4-17 AI Reference Trigger, 4-19 AI Sample Clock, 4-14 AI Sample Clock Timebase, 4-16 AI Start Trigger, 4-18 connecting, 4-6 terminal configuration, 4-2 timing signals, 4-13 timing summary, 4-13 triggering, 4-6 analog output circuitry, 5-2 connecting signals, 5-4 data generation methods, 5-2 fundamentals, 5-1 minimizing glitches, 5-2 NI 6124, A-1 NI 6154, A-7 overview, 5-1 triggering, 5-4 analog output signals AO Pause Trigger, 5-10 AO
Index PXI, and trigger signals, 9-8 routing, 9-1 common-mode input range, 4-3 noise differential ground-referenced signals, 4-9 differential non-referenced or floating signals, 4-11 differential signals, 4-9 rejection, 4-11 signal range differential non-referenced or floating signals, 4-9 signal rejection considerations differential ground-referenced signals, 4-9 connecting digital I/O signals, 6-9 PFI input signals, 8-6 connecting signals analog input, 4-6 analog output, 5-4 digital I/O S Series isolated
Index D Counter n Source signal, 7-26 Counter n TC signal, 7-29 Counter n Up_Down signal, 7-29 Counter n Z signal, 7-28 counter signals Counter n A, 7-28 Counter n Aux, 7-28 Counter n B, 7-28 Counter n Gate, 7-27 Counter n HW Arm, 7-29 Counter n Internal Output, 7-29 Counter n Source, 7-26 Counter n TC, 7-29 Counter n Up_Down, 7-29 FREQ OUT, 7-30 Frequency Output, 7-30 counters, 7-1 cascading, 7-32 connecting terminals, 7-30 duplicate count prevention, 7-34 edge counting, 7-2 filters, 7-32 generation, 7-1
Index example, 7-35 prevention example, 7-36 triggering, 11-1 waveform acquisition, 6-3 waveform generation, 6-5 digital I/O, 6-1 block diagram, 6-2 circuitry, 6-2 connecting signals, 6-9 DI change detection, 6-8 digital waveform generation, 6-5 getting started with applications in software, 6-10 I/O protection, 6-7 programmable power-up states, 6-7 static DIO, 6-2 waveform acquisition, 6-3 waveform triggering, 6-3 digital I/O for isolated devices connecting signals, 6-9, 6-12 I/O protection, 6-12 softwar
Index I/O protection, 6-7, 8-8 input coupling, 4-2 input polarity and range, 4-3 input signals using PFI terminals as, 8-4 using RTSI terminals as, 9-6 installation hardware, 1-2 NI-DAQmx, 1-1 other software, 1-1 instrument drivers (NI resources), B-1 instrumentation amplifier, 4-2 interrupt request (IRQ), 10-2 IRQ, 10-2 isolation (NI 6154), A-11 digital isolation, A-12 finite pulse train timing generation, 7-22 FREQ OUT signal, 7-30 frequency division, 7-24 generation, 7-23 generator, 7-23 measurement, 7
Index NI-DAQmx default counter terminals, 7-30 documentation, xii enabling duplicate count prevention, 7-37 single pulse-width, 7-4 single semi-period, 7-8 single two-signal edge-separation, 7-18 two-signal edge-separation, 7-17 using quadrature encoders, 7-14 using two pulse encoders, 7-16 measuring high frequency with two counters, 7-10 large range of frequencies using two counters, 7-11 low frequency with one counter, 7-9 averaged, 7-9 minimizing glitches on the output signal, 5-2 MITE and DAQ-PnP, 10-
Index reference clock 10 MHz, 9-3 external, 9-2 related documentation, xii retriggerable single pulse generation, 7-20 routing clock, 9-1 digital, 9-1 RTSI, 9-4 connector pinout, 9-4 filters, 9-6 using as outputs, 9-5 using terminals as timing input signals, 9-6 power-up states, 6-7, 8-8, 8-9 prescaling, 7-33 programmable function interface (PFI), 8-1 power-up states, 6-7, 8-8 programmable function interface, 8-2 programmable power-up states, 8-9 programmed I/O, 10-2 programming examples (NI resources), B
Index software, 1-1 AI applications, 4-21 AO applications, 5-11 DIO applications for isolated devices, 6-13 NI resources, B-1 programming devices, 2-6 routing signals in, 9-10 specifications device, 1-3 NI 6124, A-6 NI 6154, A-13 start trigger, 7-31 static DIO, 6-2 S Series isolated devices (NI 6154), 6-11 using PFI terminals as, 8-5 support, technical, B-1 synchronization modes, 7-37 80 MHz source, 7-38 external source, 7-39 other internal source, 7-39 synchronizing multiple devices, 9-3 synchronous count
Index W training and certification (NI resources), B-1 transducers, 2-5 trigger arm start, 7-31 pause, 7-31 PXI, 9-8 PXI_STAR, 9-8 Star Trigger, 9-8 start, 7-31 triggering analog edge, 11-3 analog edge with hysteresis, 11-4 analog input, 4-6 analog output, 5-4 analog types, 11-3 analog window, 11-6 counter, 7-31 digital waveform, 6-3 overview, 11-1 with a digital source, 11-1 with an analog source, 11-2 troubleshooting (NI resources), B-1 two-signal edge-separation measurement, 7-17 buffered, 7-18 single,
