Lab-PC+ User Manual Low-Cost Multifunction I/O Board for ISA June 1996 Edition Part Number 320502B-01 © Copyright 1992, 1996 National Instruments Corporation. All Rights Reserved.
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Warranty The Lab-PC+ board is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer.
Contents About This Manual ...........................................................................................................xi Organization of the Lab-PC+ User Manual ..................................................................xi Conventions Used in This Manual .................................................................................xii National Instruments Documentation ............................................................................xiii Customer Communication ..........
Contents Chapter 3 Signal Connections ............................................................................................................3-1 I/O Connector Pin Description.......................................................................................3-1 Signal Connection Descriptions .........................................................................3-2 Analog Input Signal Connections ......................................................................3-4 Types of Signal Sources....
Contents Chapter 5 Calibration .............................................................................................................................5-1 Calibration Equipment Requirements ............................................................................5-1 Calibration Trimpots ......................................................................................................5-2 Analog Input Calibration ....................................................................................
Contents Figures Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware............................................................................1-3 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 2-7. 2-8. 2-9. 2-10. 2-11. 2-12. 2-13. Parts Locator Diagram .......................................................................................2-2 Example Base I/O Address Switch Settings .....
Contents Tables Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 3-1. PC Bus Interface Factory Settings .....................................................................2-3 Switch Settings with Corresponding Base I/O Address and Base I/O Address Space .....................................................................................2-5 DMA Channels for the Lab-PC+ .......................................................................2-6 Analog I/O Jumper Settings ......................
About This Manual This manual describes the electrical and mechanical aspects of the Lab-PC+ and contains information concerning its operation and programming. The Lab-PC+ is a low-cost multifunction analog, digital, and timing I/O board for PC compatible computers.
About This Manual • The Glossary contains an alphabetical list and description of terms used in this manual, including abbreviations, acronyms, metric prefixes, mnemonics, and symbols. • The Index contains an alphabetical list of key terms and topics used in this manual, including the page where each one can be found. Conventions Used in This Manual The following conventions appear in this manual. 8253 8253 refers to the OKI Semiconductor 82C53 System Timing Controller integrated circuit.
About this Manual National Instruments Documentation The Lab-PC+ User Manual is one piece of the documentation set for your DAQ system. You could have any of several types of manuals depending on the hardware and software in your system. Use the manuals you have as follows: • Getting Started with SCXI—If you are using SCXI, this is the first manual you should read. It gives an overview of the SCXI system and contains the most commonly needed information for the modules, chassis, and software.
Chapter 1 Introduction This chapter describes the Lab-PC+; lists what you need to get started; describes the optional software and optional equipment; and explains how to unpack the Lab-PC+. About the Lab-PC+ The Lab-PC+ is a low-cost multifunction analog, digital, and timing I/O board for the PC. The Lab-PC+ contains a 12-bit successive-approximation ADC with eight analog inputs, which can be configured as eight single-ended or four differential channels.
Introduction Chapter 1 Software Programming Choices There are several options to choose from when programming your National Instruments DAQ and SCXI hardware. You can use LabVIEW, LabWindows/CVI, NI-DAQ, or register-level programming. LabVIEW and LabWindows/CVI Application Software LabVIEW and LabWindows/CVI are innovative program development software packages for data acquisition and control applications.
Chapter 1 Introduction NI-DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers. NI-DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code. Whether you are using conventional programming languages, LabVIEW, or LabWindows/CVI, your application uses the NI-DAQ driver software, as illustrated in Figure 1-1.
Introduction Chapter 1 Optional Equipment National Instruments offers a variety of products to use with your Lab-PC+ board, including cables, connector blocks, and other accessories, as follows: • Cables and cable assemblies, shielded and ribbon • Connector blocks, shielded and unshielded 50, 68, and 100-pin screw terminals • Real Time System Integration (RTSI) bus cables • Signal Condition eXtension for Instrumentation (SCXI) modules and accessories for isolating, amplifying, exciting, and multipl
Chapter 2 Configuration and Installation This chapter describes the Lab-PC+ jumper configuration and installation of the Lab-PC+ board in your computer. Board Configuration The Lab-PC+ contains six jumpers and one DIP switch to configure the PC bus interface and analog I/O settings. The DIP switch is used to set the base I/O address. Two jumpers are used as interrupt channel and DMA selectors. The remaining four jumpers are used to change the analog input and analog output circuitry.
Configuration and Installation Chapter 2 3 4 5 6 7 8 2 9 1 13 1 2 3 4 Assembly Number Spare Fuse U1 W1 12 5 6 7 W2 W3 W4 11 8 9 10 Serial Number J1 Fuse 10 11 12 13 W6 W5 Product Name Figure 2-1.
Chapter 2 Configuration and Installation Table 2-1. PC Bus Interface Factory Settings Base I/O Address Default Settings Hardware Implementation A9 A8 A7 A6 A5 Lab-PC+ Board Hex 260 U1 1 2 3 4 5 O N O F F DMA Channel DMA Channel 3 (factory setting) W6: DRQ3, DACK*3 Interrupt Level Interrupt level 5 selected (factory setting) W5: Row 5 Note: The shaded portion indicates the side of the switch that is pressed down.
O N This side down for 1 — O F F A7 A6 A5 1 2 3 4 5 U1 This side down for 0 — A8 Chapter 2 A9 Configuration and Installation O N This side down for 1 — O F F A8 A7 A6 A5 1 2 3 4 5 U1 This side down for 0 — A9 A. Switches Set to Base I/O Address of Hex 000 B. Switches Set to Base I/O Address of Hex 260 (Factory Setting) Figure 2-2.
Chapter 2 Configuration and Installation Table 2-2.
Configuration and Installation Chapter 2 DMA Channel Selection The Lab-PC+ uses the DMA channel selected by jumpers on W6 (see Figure 2-1). The Lab-PC+ is set at the factory to use DMA Channel 3. This is the default DMA channel used by the Lab-PC+ software handler. Verify that other equipment already installed in your computer does not use this DMA channel. If any device uses DMA Channel 3, change the DMA channel used by either the Lab-PC+ or the other device.
Chapter 2 Configuration and Installation DACK* W6 DRQ • • • • • • • • • • • • • • • • 1 2 3 Figure 2-4. DMA Jumper Settings for Disabling DMA Transfers Interrupt Selection The Lab-PC+ board can connect to any one of the six interrupt lines of the PC I/O channel. The interrupt line is selected by a jumper on one of the double rows of pins located above the I/O slot edge connector on the Lab-PC+ (refer to Figure 2-1).
Configuration and Installation Chapter 2 W5 If you do not want to use interrupts, place the jumper on W5 in the position shown in Figure 2-6. This setting disables the Lab-PC+ from asserting an interrupt line on the PC I/O channel. • • • • • • • • • • • • 3 4 5 6 7 9 IRQ Figure 2-6.
Chapter 2 Configuration and Installation Table 2-4.
Configuration and Installation Chapter 2 Unipolar Output Selection You can select the unipolar (0 V to 10 V) output configuration for either analog output channel by setting the following jumpers: Analog Output Channel 0 W1 B-C Analog Output Channel 1 W2 B-C This configuration is shown in Figure 2-8. W1 A B C • • • W2 B A B U C Channel 0 • • • B U Channel 1 Figure 2-8.
Chapter 2 Configuration and Installation Table 2-5. Input Configurations Available for the Lab-PC+ Configuration Description DIFF Differential configuration provides four differential inputs with the positive (+) input of the instrumentation amplifier tied to Channels 0, 2, 4, or 6 and the negative (-) input tied to Channels 1, 3, 5, or 7 respectively, thus choosing channel pairs (0,1), (2,3), (4,5), or (6,7).
Configuration and Installation Chapter 2 This configuration is shown in Figure 2-9. W4 • A RSE B NRSE/DIFF C Figure 2-9. DIFF Input Configuration Considerations in using the DIFF configuration are discussed in Chapter 3, Signal Connections. Note that the signal return path is through the negative terminal of the amplifier and through Channels 1, 3, 5, or 7, depending on which channel pair was selected.
Chapter 2 Configuration and Installation NRSE Input (Eight Channels) NRSE input means that all input signals are referenced to the same common mode voltage, which is allowed to float with respect to the analog ground of the Lab-PC+ board. This common mode voltage is subsequently subtracted out by the input instrumentation amplifier. This configuration is useful when measuring ground-referenced signal sources.
Configuration and Installation Chapter 2 W3 B U • • • A B C Figure 2-12. Bipolar Input Jumper Configuration (Factory Setting) Unipolar Input Selection You can select the unipolar (0 to 10 V) input configuration by setting the following jumper: Analog Input W3 B-C This configuration is shown in Figure 2-13. W3 B U • • • A B C Figure 2-13.
Chapter 2 Configuration and Installation Hardware Installation The Lab-PC+ can be installed in any available 8-bit or 16-bit expansion slot in your computer. After you have changed (if necessary), verified, and recorded the switches and jumper settings, you are ready to install the Lab-PC+. The following are general installation instructions, but consult your PC user manual or technical reference manual for specific instructions and warnings. 1. Turn off your computer. 2.
Chapter 3 Signal Connections This chapter describes how to make input and output signal connections to your Lab-PC+ board via the board I/O connector. I/O Connector Pin Description Figure 3-1 shows the pin assignments for the Lab-PC+ I/O connector. This connector is located on the back panel of the Lab-PC+ board and is accessible at the rear of the PC after the board has been properly installed.
Signal Connections Chapter 3 ACH0 1 2 ACH1 ACH2 3 4 ACH3 ACH4 5 6 ACH5 ACH6 7 8 ACH7 AISENSE/AIGND 9 10 DAC0 OUT AGND 11 12 DAC1 OUT DGND 13 14 PA0 PA1 15 16 PA2 PA3 17 18 PA4 PA5 19 20 PA6 PA7 21 22 PB0 PB1 23 24 PB2 PB3 25 26 PB4 PB5 27 28 PB6 PB7 29 30 PC0 PC1 31 32 PC2 PC3 33 34 PC4 PC5 35 36 PC6 PC7 37 38 EXTTRIG EXTUPDATE* 39 40 EXTCONV* OUTB0 41 42 GATB0 COUTB1 43 44 GATB1 CCLKB1 45 46 OUTB2 GATB2 47 48 CLKB2 +5 V 49 50
Chapter 3 Signal Connections Pin Signal Name Description 1-8 ACH0 through ACH7 Analog input Channels 0 through 7 (single-ended). 9 AISENSE/AIGND Analog input ground in RSE mode, AISENSE in NRSE mode. Bi-directional. 10 DAC0 OUT Voltage output signal for analog output Channel 0. 11 AGND Analog ground. Analog output ground for analog output mode. Analog input ground for DIFF or NRSE mode. Bi-directional. 12 DAC1 OUT Voltage output signal for analog output Channel 1.
Signal Connections Chapter 3 The connector pins can be grouped into analog input signal pins, analog output signal pins, digital I/O signal pins, and timing I/O signal pins. Signal connection guidelines for each of these groups are included later in this chapter. Analog Input Signal Connections Pins 1 through 8 are analog input signal pins for the 12-bit ADC. Pin 9, AISENSE/AIGND, is an analog common signal.
Chapter 3 Signal Connections Instrumentation Amplifier + Vin+ + Vm Measured Voltage - Vin- - Vm = [Vin+ - Vin-] * GAIN Figure 3-2. Lab-PC+ Instrumentation Amplifier The Lab-PC+ instrumentation amplifier applies gain, common-mode voltage rejection, and highinput impedance to the analog input signals connected to the Lab-PC+ board. Signals are routed to the positive and negative inputs of the instrumentation amplifier through input multiplexers on the Lab-PC+.
Signal Connections Chapter 3 the measured input signal varies or appears to float. An instrument or device that provides an isolated output falls into the floating signal source category. Ground-Referenced Signal Sources A ground-referenced signal source is one that is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the Lab-PC+, assuming that the PC is plugged into the same power system.
Chapter 3 Signal Connections When the Lab-PC+ is configured for DIFF input, each signal uses two of the multiplexer inputs– one for the signal and one for its reference signal. Therefore, only four analog input channels are available when using the DIFF configuration. The DIFF input configuration should be used when any of the following conditions are present: • Input signals are low-level (less than 1 V). • Leads connecting the signals to the Lab-PC+ are greater than 15 ft.
Signal Connections Grounded Signal Source Common Mode Noise, Ground Potential, and so on Chapter 3 1 ACH 0 3 ACH 2 5 ACH 4 7 ACH 6 2 ACH 1 4 ACH 3 + 6 ACH 5 - 8 ACH 7 9 AISENSE/AIGND (not connected) + V s + - - V m + Measured Voltage - V cm 11 AGND I/O Connector Lab-PC+ Board in DIFF Configuration Figure 3-3.
Chapter 3 Floating Signal Source Signal Connections + V s 1 ACH 0 3 ACH 2 5 ACH 4 7 ACH 6 2 ACH 1 4 ACH 3 6 ACH 5 8 ACH 7 9 AISENSE/AIGND (not connected) + - 100 kΩ Bias Current Return Paths 100 kΩ - Vm + Measured Voltage - 11 AGND I/O Connector Lab-PC+ Board in DIFF Configuration Figure 3-4. Differential Input Connections for Floating Sources The 100 kΩ resistors shown in Figure 3-4 create a return path to ground for the bias currents of the instrumentation amplifier.
Signal Connections Chapter 3 Single-Ended Connection Considerations Single-ended connections are those in which all Lab-PC+ analog input signals are referenced to one common ground. The input signals are tied to the positive input of the instrumentation amplifier, and their common ground point is tied to the negative input of the instrumentation amplifier. When the Lab-PC+ is configured for single-ended input (NRSE or RSE), eight analog input channels are available.
Chapter 3 Signal Connections Floating Signal Source 1 ACH 0 2 ACH 1 3 ACH 2 8 ACH 7 + Vs + 9 + AISENSE/AIGND - 11 AGND Measured Voltage Vm - I/O Connector Lab-PC+ Board in RSE Configuration Figure 3-5. Single-Ended Input Connections for Floating Signal Sources Single-Ended Connections for Grounded Signal Sources (NRSE Configuration) If a grounded signal source is to be measured with a single-ended configuration, then the Lab-PC+ must be configured in the NRSE input configuration.
Signal Connections Ground+ Referenced V s Signal Source Common Mode Noise and so on Chapter 3 1 ACH 0 2 ACH 1 3 ACH 2 8 ACH 7 + 9 + 11 AGND V cm AISENSE/AIGND - Vm + Measured Voltage - - I/O Connector Lab-PC+ Board in NRSE Input Configuration Figure 3-6.
Chapter 3 Signal Connections Pin 11, AGND, is the ground reference point for both analog output channels as well as analog input. The following output ranges are available: Bipolar input: ±5 V* Unipolar input: 0 to 10 V* Output signal range * Maximum load current = ±2 mA for 12-bit linearity Figure 3-7 shows how to make analog output signal connections. 10 DAC0 OUT + Load Channel 0 VOUT 0 11 AGND Load VOUT 1 + 12 DAC1 OUT Channel 1 Analog Output Channels Lab PC+ Board Figure 3-7.
Signal Connections Chapter 3 are connected to the digital lines PC<0..7> for digital I/O Port C. Pin 13, DGND, is the digital ground pin for all three digital I/O ports. The following specifications and ratings apply to the digital I/O lines. Absolute maximum voltage input rating: +5.5 V with respect to DGND -0.5 V with respect to DGND Logical Inputs and Outputs Digital I/O lines: Minimum Maximum Input logic low voltage -0.3 V 0.8 V Input logic high voltage 2.2 V 5.
Chapter 3 Signal Connections +5 V LED Port A 14 PA0 PA<7..0> Port B 22 PB0 PB<7..0> TTL Signal 30 PC0 +5 V Port C PC<7..0> Switch 13 DGND I/O Connector Lab-PC+ Board Figure 3-8. Digital I/O Connections In Figure 3-8, Port A is configured for digital output, and Ports B and C are configured for digital input. Digital input applications include receiving TTL signals and sensing external device states such as the switch in Figure 3-8.
Signal Connections Chapter 3 Table 3-2. Port C Signal Assignments Programmable Mode Group A Group B PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Mode 0 I/O I/O I/O I/O I/O I/O I/O I/O Mode 1 Input I/O I/O IBF A STBA* INTRA STBB* IBFBB INTRB Mode 1 Output OBFA* ACKA* I/O I/O INTRA ACKB* OBFB* INTRB Mode 2 OBFA* ACKA* IBF A STBA* INTRA I/O I/O I/O *Indicates that the signal is active low.
Chapter 3 Signal Connections Name Type Description (continued) OBF* Output Output buffer full–A low signal on this handshaking line indicates that data has been written from the specified port. INTR Output Interrupt request–This signal becomes high when the 8255A is requesting service during a data transfer. The appropriate interrupt enable signals must be set to generate this signal. RD* Internal Read signal–This signal is the read signal generated from the control lines of the PC I/O channel.
Signal Connections Chapter 3 Mode 1 Input Timing The timing specifications for an input transfer in Mode 1 are as follows: T1 T2 T4 STB * T7 T6 IBF INTR RD * T3 T5 DATA Name T1 T2 T3 T4 T5 T6 T7 Description Minimum STB* pulse width STB* = 0 to IBF = 1 Data before STB* = 1 STB* = 1 to INTR = 1 Data after STB* = 1 RD* = 0 to INTR = 0 RD* = 1 to IBF = 0 500 – 0 – 180 – – Maximum – 300 – 300 – 400 300 All timing values are in nanoseconds.
Chapter 3 Signal Connections Mode 1 Output Timing The timing specifications for an output transfer in Mode 1 are as follows: T3 WR* T4 OBF* T1 INTR T6 T5 ACK* DATA T2 Name T1 T2 T3 T4 T5 T6 Description Minimum WR* = 0 to INTR = 0 WR* = 1 to output WR* = 1 to OBF* = 0 ACK* = 0 to OBF* = 1 ACK* pulse width ACK* = 1 to INTR = 1 – – – – 300 – Maximum 450 350 650 350 – 350 All timing values are in nanoseconds.
Signal Connections Chapter 3 Mode 2 Bidirectional Timing The timing specifications for bidirectional transfers in Mode 2 are as follows: T1 WR * T6 OBF * INTR T7 ACK * T3 STB * T10 T4 IBF RD * T2 T5 T8 T9 DATA Name T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Description Minimum WR* = 1 to OBF* = 0 Data before STB* = 1 STB* pulse width STB* = 0 to IBF = 1 Data after STB* = 1 ACK* = 0 to OBF = 1 ACK* pulse width ACK* = 0 to output ACK* = 1 to output float RD* = 1 to IBF = 0 – 0 500 – 180 – 300 – 20 – Ma
Chapter 3 Signal Connections Timing Connections Pins 38 through 48 of the I/O connector are connections for timing I/O signals. The timing I/O of the Lab-PC+ is designed around the 8253 Counter/Timer integrated circuit. Two of these integrated circuits are employed in the Lab-PC+. One, designated 8253(A), is used exclusively for data acquisition timing, and the other, 8253(B), is available for general use.
Signal Connections Chapter 3 and 3-11 illustrate two possible posttrigger data acquisition timing cases. In Figure 3-10, the rising edge on EXTTRIG is sensed when the EXTCONV* input is high. Thus, the first A/D conversion occurs on the second falling edge of EXTCONV*, after the rising edge on EXTTRIG. In Figure 3-11, the rising edge on EXTTRIG is sensed when the EXTCONV* input is low. In this case, the first A/D conversion occurs on the first falling edge of EXTCONV*, after the rising edge on EXTTRIG.
Chapter 3 Signal Connections If PRETRIG is set, EXTTRIG serves as a pretrigger signal. In pretrigger mode, A/D conversions are enabled via software before a rising edge is sensed on the EXTTRIG input. However, the sample counter, Counter A1, is not gated on until a rising edge is sensed on the EXTTRIG input. Additional transitions on this line have no effect until a new data acquisition sequence is set up.
Signal Connections Chapter 3 EXTUPDATE* text DAC OUTPUT UPDATE CNTINT DACWRT text Minimum 50 nsec Figure 3-13. EXTUPDATE* Signal Timing for Updating DAC Output Since a rising edge on the EXTUPDATE* signal always sets the CNTINT bit in the Status Register, the EXTUPDATE* signal can also be used for periodic interrupt generation timed by an external source. The CNTINT bit is cleared by writing to the Timer Interrupt Clear Register.
Chapter 3 Signal Connections measurement. For these applications, CLK and GATE signals are sent to the counters, and the counters are programmed for various operations. The single exception is counter B0, which has an internal 2 MHz clock. The 8253 Counter/Timer is described briefly in Chapter 4, Theory of Operation. For detailed programming information, consult Appendix B, OKI 82C53 Data Sheet.
Signal Connections Chapter 3 counting after receiving a low-to-high edge. The time lapse since receiving the edge equals the counter value difference (loaded value minus read value) multiplied by the CLK period. To perform frequency measurement, program a counter to be level gated and count the number of falling edges in a signal applied to a CLK input. The gate signal applied to the counter GATE input is of known duration.
Chapter 3 Signal Connections The following specifications and ratings apply to the 8253 I/O signals: Absolute maximum voltage input rating: -0.5 to 7.0 V with respect to DGND 8253 digital input specifications (referenced to DGND): VIH input logic high voltage 2.2 V minimum VIL input logic low voltage 0.8 V maximum Input load current ±10 µA maximum 8253 digital output specifications (referenced to DGND): VOH output logic high voltage 3.7 V minimum VOL output logic low voltage 0.
Signal Connections Chapter 3 The GATE and OUT signals in Figure 3-17 are referenced to the rising edge of the CLK signal. Cabling National Instruments currently offers a cable termination accessory, the CB-50, for use with the Lab-PC+ board. This kit includes a terminated, 50-conductor, flat ribbon cable and a connector block. Signal input and output wires can be attached to screw terminals on the connector block and thereby connected to the Lab-PC+ I/O connector.
Chapter 4 Theory of Operation This chapter contains a functional overview of the Lab-PC+ and explains the operation of each functional unit making up the Lab-PC+. This chapter also explains the basic operation of the Lab-PC+ circuitry. Functional Overview The block diagram in Figure 4-1 shows a functional overview of the Lab-PC+ board.
Theory of Operation Chapter 4 The following are the major components making up the Lab-PC+ board: • PC I/O channel interface circuitry • Analog input and data acquisition circuitry • Analog output circuitry • Digital I/O circuitry • Timing I/O circuitry Data acquisition functions can be executed by using the analog input circuitry and some of the timing I/O circuitry. The internal data and control buses interconnect the components.
Chapter 4 Theory of Operation Address Bus PC I/O Channel Control Lines Data Bus DMA REQ DMA ACK Address Decoder Address Latches Register Selects Timing Interface Read and Write Signals Data Buffers Internal Data Bus DMA Control DMA Request DMA ACK and DMATC Interrupt Control Interrupt Requests IRQ Figure 4-2.
Theory of Operation Chapter 4 • When a digital I/O port is ready to transfer data • When a rising edge signal is detected on Counter A2 output or on the EXTUPDATE line Each one of these interrupts is individually enabled and cleared. The DMA control circuitry generates DMA requests whenever an A/D conversion result is available from FIFO, if the DMA transfer is enabled. The Lab-PC+ supports 8-bit DMA transfers. DMA Channels 1, 2, and 3 of the PC I/O channel are available for such transfers.
Chapter 4 Theory of Operation Analog Input Circuitry The analog input circuitry consists of two CMOS analog input multiplexers, a softwareprogrammable gain amplifier, a 12-bit ADC, and a 12-bit FIFO memory that is sign-extended to 16 bits. One of the input multiplexers has eight analog input channels (Channels 0 through 7). The other multiplexer is connected to Channels 1, 3, 5, and 7 for differential mode. The input multiplexers provide input overvoltage protection of ±45 V, powered on or off.
Theory of Operation Chapter 4 (scanned) data acquisition in two modes–continuous and interval. The Lab-PC+ uses a counter to switch between analog input channels automatically during scanned data acquisition. Data acquisition timing consists of signals that initiate a data acquisition operation, initiate individual A/D conversions, gate the data acquisition operation, and generate scanning clocks. Sources for these signals are supplied mainly by timers on the Lab-PC+ board.
Chapter 4 Theory of Operation You must initialize two additional counters to operate in interval acquisition mode. In singlechannel interval acquisition mode, the Lab-PC+ samples a single channel a programmable number of times, waits for the duration of the scan interval, and repeats this cycle. In the scanned interval acquisition mode, the Lab-PC+ scans the selected samples, waits for the duration of the scan interval, and repeats the cycle.
Theory of Operation Chapter 4 Table 4-2. Lab-PC+ Maximum Recommended Data Acquisition Rates Acquisition Mode Gain Setting Rate Single Channel 1 2, 5, 10, 20, 50, 100 83.3 ksamples/s 71.4 ksamples/s* Multiple Channel 1 2, 5, 10, 20, 50 83.3 ksamples/s 62.5 ksamples/s typical, 55.5 ksamples/s worst case 20.0 ksamples/s 100 * The single-channel acquisition rate decreases at higher gains because an offset error, dependent on the sampling rate, occurs at rates faster than 71.4 ksamples/s.
Chapter 4 Theory of Operation Analog Output Circuitry The Lab-PC+ provides two channels of 12-bit D/A output. Each analog output channel can provide unipolar or bipolar output. Figure 4-4 shows a block diagram of the analog output circuitry. 2SDAC0 DAC0WR Coding DAC0 DAC0 OUT Ref Data DAC1WR Ref DAC1 Coding I/O Connector PC I/O Channel AGND 5 V Internal Reference 8 DAC1 OUT Counter A2 2SDAC1 EXTUPDATE* CNFGWR Command Register 2 LDAC1 2SDAC1 2SDAC0 LDAC0 Figure 4-4.
Theory of Operation Chapter 4 Each DAC channel can be jumper-programmed for either a unipolar voltage output or a bipolar voltage output range. A unipolar output gives an output voltage range of 0.0000 V to +9.9976 V. A bipolar output gives an output voltage range of -5.0000 V to +4.9976 V. For unipolar output, 0.0000 V output corresponds to a digital code word of 0. For bipolar output, -5.0000 V output corresponds to a digital code word of F800 (hex).
Chapter 4 Theory of Operation All three ports on the 8255A are TTL-compatible. When enabled, the digital output ports are capable of sinking 2.4 mA of current and sourcing 2.6 mA of current on each digital I/O line. When the ports are not enabled, the digital I/O lines act as high-impedance inputs. Timing I/O Circuitry The Lab-PC+ uses two 8253 Counter/Timer integrated circuits for data acquisition timing and for general-purpose timing I/O functions.
Theory of Operation Chapter 4 GATEB2 GATEB2 1 MHz Source OUTB0 CLKB2 CLKB2 OUTB2 OUTB2 GATEB1 CLKB1 GATEB1 Scan Interval/ General Purpose Counter MUX MUX CCLKB1 CLKA0 OUTB1 N/C I/O Connector Timebase Extension/ General Purpose Counter MUX PC I/O Channel OUTB0 GATEB0 OUTB0 GATEB0 CLKB0 CTR RD CLKA0 8253 Counter/Timer Group B GATEA0 CTR WR Data 2 MHz Source Sample Interval Counter COUTB1 OUTA0 8 MUX CLKA1 Sample Counter A/D Conversion Logic GATEA1 OUTA1 CLKA2 EXTCONV* EXTTR
Chapter 4 Theory of Operation Each 8253 contains three independent 16-bit counter/timers and one 8-bit Mode Register. As shown in Figure 4-6, Counter Group A is reserved for data acquisition timing, and Counter Group B is free for general use. The output of Counter B0 can be used in place of the 1 MHz clock source on Counter A0 to allow clock periods greater than 65,536 µs. All six counter/timers can be programmed to operate in several useful timing modes.
Theory of Operation Chapter 4 Scan Interval OUTB1 Sample Sample Interval Interval OUTA0 CONVERT GATEA0 Interval Counter Figure 4-8. Single-Channel Interval Timing The 16-bit counters in the 8253 can be diagrammed as shown in Figure 4-9. CLK Counter OUT GATE Figure 4-9. Counter Block Diagram Each counter has a CLK input pin, a GATE input pin, and an output pin labeled OUT.
Chapter 5 Calibration This chapter discusses the calibration procedures for the Lab-PC+ analog input and analog output circuitry. The Lab-PC+ is calibrated at the factory before shipment. In order to maintain the 12-bit accuracy of the Lab-PC+ analog input and analog output circuitry, recalibration at six-month intervals is recommended. Recalibration is also recommended whenever the input or output configuration is changed.
Calibration Chapter 5 Calibration Trimpots The Lab-PC+ has six trimpots for calibration. The location of these trimpots on the Lab-PC+ board is shown in the partial diagram of the board in Figure 5-1. 1 1 2 R1 R2 3 4 2 3 4 R3 R4 5 5 6 6 7 R5 R6 7 R7 Figure 5-1.
Chapter 5 Calibration Analog Input Calibration To null out error sources that compromise the quality of measurements, you must calibrate the analog input circuitry by adjusting the following potential sources of error: • Offset errors • Gain error of the analog input circuitry You must perform the calibration if you change the input configuration from bipolar (the factory setting) to unipolar.
Calibration Chapter 5 The voltages corresponding to V-fs, which is the most negative voltage that the ADC can read, V+fs - 1, which is the most positive voltage the ADC can read, and 1 LSB, which is the voltage corresponding to one count of the ADC, depend on the input range selected. The value of these voltages for each input range is given in Table 5-1. Table 5-1. Voltage Values of ADC Input Input Range V-fs V+fs - 1 1 LSB 0.5 LSB -5 to +5 V 0 to 10 V -5 V 0V +4.99756 V +9.99756 V 2.44 mV 2.
Chapter 5 Calibration later for software offset correction of the data at gains other than 1, thus eliminating the need to perform the input offset recalibration when a different gain is used. The software correction consists of subtracting the recorded reading at gain G from every A/D conversion value obtained at gain G. 3. Gain Calibration Adjust the analog input gain by applying an input voltage across ACH0 and AISENSE/AIGND. This input voltage is +4.99634 V or V+fs - 1.5 LSB. a.
Calibration Chapter 5 3. Gain Calibration Adjust the analog input gain by applying an input voltage across ACH0 and AISENSE/AIGND. This input voltage is +9.99634 V or V+fs - 1.5 LSB. a. Connect the calibration voltage (+9.99634 V) across ACH0 (pin 1 on the I/O connector) and AISENSE/AIGND (pin 9). b. Take analog input readings from Channel 0 at a gain of 1, and adjust trimpot R5 until the ADC readings flicker evenly between 4,094 and 4,095.
Chapter 5 Calibration 1. Adjust the Analog Output Offset Adjust the analog output offset by measuring the output voltage generated with the DAC set at negative full-scale (0). This output voltage should be V-fs ±0.5 LSB. For bipolar output, V-fs = -5 V, and 0.5 LSB = 1.22 mV. For analog output Channel 0: a. Connect the voltmeter between DAC0 OUT (pin 10 on the I/O connector) and AGND (pin 11). b. Set the analog output channel to -5 V by writing -2,048 to the DAC. c.
Calibration Chapter 5 Unipolar Output Calibration Procedure If your analog output channel is configured for unipolar output, which has an output range of 0 to +10 V, then offset calibration is not needed. Calibrate your board by completing the following procedures for gain calibration. Adjust the Analog Output Gain Adjust the analog output gain by measuring the output voltage generated with the DAC set at positive full-scale (4,095). This output voltage should be V+fs ±0.5 LSB.
Appendix A Specifications This appendix lists the specifications of the Lab-PC+. These specifications are typical at 25°C unless otherwise stated. The operating temperature range is 0° to 70°C. Analog Input Input Characteristics Number of channels ...................................... 8 single-ended, 4 differential Type of ADC................................................. Successive approximation Resolution .....................................................
Specifications Appendix A Amplifier Characteristics Input impedance ............................................ 0.1 GΩ in parallel with 45 pF Input bias current .......................................... 150 pA CMRR ........................................................... Gain CMRR at 60 Hz 1 75 dB 100 105 dB Dynamic Characteristics Bandwidth (-3 dB) ........................................ 400 kHz for gain = 1, 40 kHz for gain = 100 Settling time to full-scale step.......................
Appendix A Specifications Explanation of Analog Input Specifications Relative accuracy is a measure of the linearity of an ADC. However, relative accuracy is a tighter specification than a nonlinearity specification. Relative accuracy indicates the maximum deviation from a straight line for the analog input-to-digital output transfer curve.
Specifications Appendix A Analog Output Output Characteristics Number of channels ...................................... 2 Resolution ..................................................... 12 bits, 1 in 4,096 Type of DAC................................................. Double-buffered multiplying Data transfers ................................................ Interrupts, programmed I/O Transfer Characteristics Relative accuracy (INL) ................................ bipolar range ..........................
Appendix A Specifications Differential nonlinearity (DNL) in a D/A system is a measure of deviation of code width from 1 LSB. In this case, code width is the difference between the analog values produced by consecutive digital codes. A specification of ±1 LSB differential nonlinearity ensures that the code width is always greater than 0 LSBs (guaranteeing monotonicity) and is always less than 2 LSBs. Digital I/O Number of channels ...................................... 24 Compatibility ..................
Specifications Appendix A Digital logic levels ........................................ Level Input low voltage Input high voltage Output low voltage (Iout = 4 mA) Output high voltage (Iout = -1 mA) Min -0.3 V 2.2 V Max 0.8 V 5.3 V - 0.45 V 3.7 V - Triggers Digital Trigger Compatibility .......................................... TTL Response ................................................. Rising edge Pulse width .............................................. 250 ns Bus Interface ................
Appendix B OKI 82C53 Data Sheet* This appendix contains the manufacturer data sheet for the OKI 82C53 System Timing Controller integrated circuit (OKI Semiconductor). This circuit is used on the Lab-PC+. * Copyright © OKI Semiconductor 1991. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor. Microprocessor Data Book 1990/1991.
Appendix C OKI 82C55A Data Sheet* This appendix contains the manufacturer data sheet for the OKI 82C55A Programmable Peripheral Interface integrated circuit (OKI Semiconductor). This circuit is used on the Lab-PC+. * Copyright © OKI Semiconductor 1991. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor. Microprocessor Data Book 1990/1991.
Appendix D Register Map and Descriptions This appendix describes in detail the address and function of each of the Lab-PC+ registers. Note: If you plan to use a programming software package such as NI-DAQ, NI-DSP, LabVIEW, or LabWindows/CVI with your Lab-PC+, you need not read this appendix. Refer to your software documentation for programming information. Register Map The register map for the Lab-PC+ is given in Table D-1.
Register Map and Descriptions Appendix D Table D-1.
Appendix D Register Map and Descriptions Register Sizes The Lab-PC+ registers are 8-bit registers. To transfer 16-bit data, two consecutive I/O readings or writings are needed. For example, to read the 16-bit A/D conversion result, two consecutive 8-bit readings of FIFO are needed. The first reading returns the low byte of the 16-bit data, and the second returns the high byte of the data. Register Description Table D-1 divides the Lab-PC+ registers into six different register groups.
Register Map and Descriptions Appendix D Configuration and Status Register Group The five registers making up the Configuration and Status Register Group allow general control and monitoring of the Lab-PC+ A/D and D/A circuitry. Command Register 1 and Command Register 2 contain bits that control the operation modes of the A/D and D/A circuitry. Command Register 3 enables or disables the interrupt and DMA operations.
Appendix D Register Map and Descriptions Command Register 1 Command Register 1 indicates the input channel to be read, the gain for the analog input circuitry, and the range of the input signal (unipolar or bipolar). Address: Base address + 00 (hex) Type: Write-only Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 SCANEN GAIN2 GAIN1 GAIN0 TWOSCMP MA2 MA1 MA0 Bit Name Description 7 SCANEN This bit enables or disables multiple-channel scanning during data acquisition.
Register Map and Descriptions Appendix D Bit Name Description (continued) 3 TWOSCMP This bit selects the format of the coding of the output of the ADC. If this bit is set, the 12-bit data from the ADC is sign-extended to 16 bits. If this bit is cleared, bits 12 through 15 return 0. 2-0 MA<2..0> These three bits select which of the eight input channels are read. The analog input __multiplexers depend on these bits and also on SCANEN and SE/D (bit 3 of Command Register 4).
Appendix D Register Map and Descriptions Status Register The Status Register indicates the status of the current A/D conversion. The bits in this register determine if a conversion is being performed or if data is available, whether any errors have been found, and the interrupt status.
Register Map and Descriptions Appendix D Bit Name Description (continued) 1 OVERRUN This bit indicates if an overrun error has occurred. If this bit is cleared, no error occurred. This bit is set if a convert command is issued to the ADC while the last conversion is still in progress. 0 DAVAIL This bit indicates whether conversion output is available. If this bit is set, the ADC is finished with the last conversion and the result can be read from the FIFO. This bit is cleared if the FIFO is empty.
Appendix D Register Map and Descriptions Command Register 2 Command Register 2 contains eight bits that control Lab-PC+ analog input trigger modes and analog output modes. Address: Base address + 01 (hex) Type: Write-only Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 LDAC1 LDAC0 2SDAC1 2SDAC0 TBSEL SWTRIG HWTRIG PRETRIG Bit Name Description 7 LDAC1 This bit is used to enable timer waveform generation from DAC1.
Register Map and Descriptions Appendix D Bit Name Description (continued) 2 SWTRIG This bit enables and disables a data acquisition operation that is controlled by Counter A0 and Counter A1. If Counter A0 is programmed for data acquisition, writing 1 to this bit enables Counter A0, and thus starts a data acquisition operation. A data acquisition process is terminated either by the terminal count signal of Counter A1 or by clearing SWTRIG.
Appendix D Register Map and Descriptions Command Register 3 The Command Register 3 contains six bits that enable and disable the interrupts and DMA operation. Address: Base address + 02 (hex) Type: Write-only Word Size: 8-bit Bit Map: 7 6 5 X X FIFOINTEN 4 3 ERRINTEN CNTINTEN 2 1 0 TCINTEN DIOINTEN DMAEN Bit Name Description 7-6 X Don't care bits. 5 FIFOINTEN This bit enables and disables the generation of an interrupt when A/D conversion results are available.
Register Map and Descriptions Appendix D Bit Name Description (continued) 1 DIOINTEN This bit enables or disables generation of an interrupt when either Port A or Port B is ready to transfer data, and an interrupt request is set via PC3 or PC0 of 8255A. (See Appendix C, OKI 82C55A Data Sheet, for details.) If DIOINTEN is cleared, the interrupts from PC3 or PC0 are disabled. 0 DMAEN This bit enables and disables the generation of DMA requests.
Appendix D Register Map and Descriptions Command Register 4 This register allows multiplexing of certain A/D conversion logic signals. This enables the interval scanning and A/D conversion signals to be available at the I/O connector and allows the I/O connector pins to externally drive these signals. Address: Base address + 0F (hex) Type: Write-only Word Size: 8-bit Bit Map: 7 6 5 4 X X X ECLKRCV __3 SE /D 2 1 0 ECLKDRV EOIRCV INTSCAN Bit Name Description 7-5 X Don't care bits.
Register Map and Descriptions Appendix D Bit Name Description (continued) 2 ECKDRV This bit controls the direction of the EXTCONV* line on the I/O Connector. If this bit is clear, EXTCONV* is driven from the I/O Connector into the conversion circuitry. If this bit is set, a conditioned version of the output of counter A0 is driven onto the I/O Connector. Under most circumstances, this bit should be clear. This bit is cleared on reset.
Appendix D Register Map and Descriptions Analog Input Register Group The four registers making up the Analog Input Register Group control the analog input circuitry and can be used to read the FIFO. Reading the FIFO Register returns stored A/D conversion results. Writing to the Start Convert Register initiates an A/D conversion. Writing to the A/D Clear Register clears the data acquisition circuitry. Writing to the DMATC Clear Register clears the interrupt request generated by a DMA terminal count pulse.
Register Map and Descriptions Appendix D A/D FIFO Register The 12-bit A/D conversion results are sign-extended to 16-bit data in either two's complement or straight binary format and are stored into a 512-word deep A/D FIFO buffer. Two consecutive 8-bit readings of the A/D FIFO Register return an A/D conversion value stored in the A/D FIFO. The first reading returns the low byte of the 16-bit value, and the second reading returns the high byte.
Appendix D Bit Register Map and Descriptions Name Description (continued) Low Byte 7-0 D<7..0> Bit Map: These bits contain the low byte of the straight binary result of a 12-bit A/D conversion. The first of two consecutive readings of the A/D FIFO Register always return this byte.
Register Map and Descriptions Appendix D A/D Clear Register The ADC can be reset by writing to this register. This operation clears the FIFO and loads the last conversion value into the FIFO. All error bits in the Status Register are cleared as well. Notice that the FIFO contains one data word after reset, so two consecutive FIFO readings are necessary after reset to empty the FIFO. The data that is read should be ignored.
Appendix D Register Map and Descriptions Start Convert Register Writing to the Start Convert Register location initiates an A/D conversion. Address: Base address + 03 (hex) Type: Write-only Word Size: 8-bit Bit Map: Not applicable, no bits used Note: A/D conversions can be initiated in one of two ways: by writing to the Start Convert Register or by detecting an active low signal on either the Counter A0 output or the EXTCONV* signal.
Register Map and Descriptions Appendix D DMATC Interrupt Clear Register Writing to the DMA Terminal Count (DMATC) Clear Register clears the interrupt request asserted when a DMA terminal count pulse is detected.
Appendix D Register Map and Descriptions Analog Output Register Group The four registers making up the Analog Output Register Group are used for loading the two 12-bit DACs in the two analog output channels. DAC0 controls analog output Channel 0. DAC1 controls analog output Channel 1. These DACs should be written to individually. Bit descriptions of the registers making up the Analog Output Register Group are given on the following pages.
Register Map and Descriptions Appendix D DAC0 Low-Byte (DAC0L), DAC0 High-Byte (DAC0H), DAC1 Low-Byte (DAC1L), and DAC1 High-Byte (DAC1H) Registers Writing to DAC0L and then to DAC0H loads the analog output Channel 0. Writing to DAC1L and then to DAC1H loads the analog output Channel 1. The voltage generated by the analog output channels is updated immediately after the corresponding DACxH register is written to, if the corresponding LDACx bit is cleared in Command Register 2.
Appendix D Register Map and Descriptions 8253 Counter/Timer Register Groups A and B The nine registers making up the two Counter/Timer Register Groups access the two onboard 8253 Counter/Timers. Each 8253 has three counters. For convenience, the two Counter/Timer Groups and their respective 8253 integrated circuits have been designated A and B. The three counters of Group A control onboard data acquisition timing and waveform generation.
Register Map and Descriptions Appendix D Counter A0 Data Register The Counter A0 Data Register is used for loading and reading back contents of 8253(A) Counter 0. Address: Base address + 14 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7-0 D<7..0> 8-bit Counter A0 contents.
Appendix D Register Map and Descriptions Counter A1 Data Register The Counter A1 Data Register is used for loading and reading back contents of 8253(A) Counter 1. Address: Base address + 15 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7-0 D<7..0> 8-bit Counter A1 contents.
Register Map and Descriptions Appendix D Counter A2 Data Register The Counter A2 Data Register is used for loading and reading back contents of 8253(A)Counter A2. Address: Base address + 16 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7-0 D<7..0> 8-bit Counter A2 contents.
Appendix D Register Map and Descriptions Counter A Mode Register The Counter A Mode Register determines the operation mode for each of the three counters on the 8253(A) chip. The Counter A Mode Register selects the counter involved, its read/load mode, its operation mode (that is, any of the 8253's six operation modes), and the counting mode (binary or BCD counting). The Counter A Mode Register is an 8-bit register. Bit descriptions for each of these bits are given in Appendix B, OKI 82C53 Data Sheet.
Register Map and Descriptions Appendix D Timer Interrupt Clear Register Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a low pulse is detected on the Counter A2 output or on EXTUPDATE* line. Address: Base address + 0C (hex) Type: Write-only Word Size: 8-bit Bit Map: Not applicable, no bits used.
Appendix D Register Map and Descriptions Counter B0 Data Register The Counter B0 Data Register is used for loading and reading back the contents of 8253(B) Counter 0. Address: Base address + 18 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7-0 D<7..0> 8-bit Counter B0 contents.
Register Map and Descriptions Appendix D Counter B1 Data Register The Counter B1 Data Register is used for loading and reading back the contents of 8253(B) Counter 1. Address: Base address + 19 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7-0 D<7..0> 8-bit Counter B1 contents.
Appendix D Register Map and Descriptions Counter B2 Data Register The Counter B2 Data Register is used for loading and reading back the contents of 8253(B) Counter 2. Address: Base address + 1A (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7-0 D<7..0> 8-bit Counter B2 contents.
Register Map and Descriptions Appendix D Counter B Mode Register The Counter B Mode Register determines the operation mode for each of the three counters on the 8253(B) chip. The Counter B Mode Register selects the counter involved, its read/load mode, its operation mode (that is, any of the 8253's six operation modes), and the counting mode (binary or BCD counting). The Counter Mode Register is an 8-bit register.
Appendix D Register Map and Descriptions 8255A Digital I/O Register Group Digital I/O on the Lab-PC+ uses an 8255A integrated circuit. The 8255A is a general-purpose peripheral interface containing 24 programmable I/O pins. These pins represent the three 8-bit I/O ports (A, B, and C) of the 8255A. These ports can be programmed as two groups of 12 signals or as three individual 8-bit ports. Bit descriptions for the registers in the Digital I/O Register Group are given on the following pages.
Register Map and Descriptions Appendix D Port A Register Reading the Port A Register returns the logic state of the eight digital I/O lines constituting Port A, that is, PA<0..7>. If Port A is configured for output, the Port A Register can be written to in order to control the eight digital I/O lines constituting Port A. See Programming the Digital I/O Circuitry in Appendix E, Register-Level Programming, for information on how to configure Port A for input or output.
Appendix D Register Map and Descriptions Port B Register Reading the Port B Register returns the logic state of the eight digital I/O lines constituting Port B, that is, PB<0..7>. If Port B is configured for output, the Port B Register can be written to in order to control the eight digital I/O lines constituting Port B. See Programming the Digital I/O Circuitry in Appendix E, Register-Level Programming, for information on how to configure Port B for input or output.
Register Map and Descriptions Appendix D Port C Register Port C is special in the sense that it can be used as an 8-bit I/O port like Port A and Port B if neither Port A nor Port B is used in handshaking (latched) mode. If either Port A or Port B is configured for latched I/O, some of the bits in Port C are used for handshaking signals. See Programming the Digital I/O Circuitry in Appendix E, Register-Level Programming, for a description of the individual bits in the Port C Register.
Appendix D Register Map and Descriptions Digital Control Register The Digital Control Register can be used to configure Port A, Port B, and Port C as inputs or outputs as well as selecting simple mode (basic I/O) or handshaking mode (strobed I/O) for transfers. See Programming the Digital I/O Circuitry in Appendix E, Register-Level Programming, for a description of the individual bits in the Digital Control Register.
Register Map and Descriptions Appendix D Interval Counter Register Group The 8-bit Interval Counter is used only in the single-channel interval mode (SCANEN = 0 and INTSCAN = 1) and consists of two 8-bit registers–the Interval Counter Data Register and the Interval Counter Strobe Register. The Interval Counter Data Register is loaded with the count. Writing to the Interval Counter Strobe Register loads this count into the Interval Counter. The Interval Counter decrements with each conversion.
Appendix D Register Map and Descriptions Interval Counter Data Register The Interval Counter Data Register is loaded with the desired number of samples of a single channel that will be acquired between intervals. See Programming Multiple A/D Conversions in Single-Channel Interval Acquisition Mode in Appendix E, Register-Level Programming, for a description of the programming sequence.
Register Map and Descriptions Appendix D Interval Counter Strobe Register Writing to Interval Counter Strobe Register strobes the contents of the Interval Counter Data Register into the Interval Counter. This action arms the Interval Counter, which then decrements with each conversion pulse.
Appendix E Register-Level Programming This appendix contains important information about programming the Lab-PC+. Programming the Lab-PC+ involves writing to and reading from the various registers on the board. The programming instructions included here list the sequence of steps to take.
Register-Level Programming Appendix E 8. Write 00 (hex) to the DMATC Interrupt Clear Register. 9. Write 00 (hex) to the Timer Interrupt Clear Register. 10. Write 00 (hex) to the A/D Clear Register. 11. Read the data from the A/D FIFO Register (twice). Ignore the data. 12. Write 00 (hex) to the DAC0L, and then write 00 (hex) to the DAC0H if DAC0 is configured for unipolar output. Write 00 (hex) to the DAC0L, and then write 08 (hex) to the DAC0H if DAC0 is configured for bipolar output. 13.
Appendix E Register-Level Programming Analog Input Circuitry Programming Sequence Programming the analog input circuitry for a single A/D conversion involves selecting the analog input channel and gain, initiating an A/D conversion, and reading the A/D conversion result. 1. Select analog input channel and gain. The analog input channel and gain are selected by writing to Command Register 1. See the Command Register 1 bit description earlier in this chapter for gain and analog input channel bit patterns.
Register-Level Programming Appendix E The DAVAIL bit indicates whether one or more A/D conversion results are stored in the A/D FIFO. If the DAVAIL bit is cleared, the A/D FIFO is empty and reading the A/D FIFO Register returns meaningless data. Once an A/D conversion is initiated, the DAVAIL bit should be set after 12 µs or after a rising edge on OUTA0, whichever occurs later.
Appendix E Register-Level Programming Clearing the Analog Input Circuitry The analog input circuitry can be cleared by writing to the A/D Clear Register, which leaves the analog input circuitry in the following state: • Analog input error flags OVERFLOW and OVERRUN are cleared. • Pending interrupt requests are cleared. • A/D FIFO has one garbage word of data. Empty the A/D FIFO before starting any A/D conversions by performing two 8-bit reads on the A/D FIFO Register and ignoring the data read.
Register-Level Programming Appendix E Alternatively, a programmable timebase for Counter A0 is available through the use of Counter B0. If the TBSEL bit in Command Register 1 is set, then the timebase for Counter A0 is Counter B0. Counter B0 has a fixed, unalterable 2 MHz clock as its own timebase, so its period is the value stored in it multiplied by 500 ns. The minimum period that can be selected for Counter B0 is 1 µs.
Appendix E Register-Level Programming 3. Program Counters A0 and A1. This step involves programming Counter A0 (the sample interval counter) in rate generator mode (Mode 2) and programming Counter A1 to interrupt on terminal count mode (Mode 0). Counter A0 of the 8253(A) Counter/Timer is used as the sample interval counter. A high-tolow transition on the Counter A0 output initiates a conversion. Counter A0 can be programmed to generate a pulse once every N µs.
Register-Level Programming Appendix E Once the data acquisition operation is started, the operation must be serviced by reading the A/D FIFO Register every time an A/D conversion result becomes available. To do this, perform the following sequence until the desired number of conversion results have been read: a. Read the Status Register (8-bit read). b. If the DAVAIL bit is set (bit 0), then read the A/D FIFO Register to obtain the result.
Appendix E Register-Level Programming 1. Select analog input channel, gain, and timebase for Counter A0. The analog input channel and gain are selected by writing to the A/D Configuration Register. The SCANEN bit must be cleared for data acquisition operations on a single channel. See the Command Register 1 bit description earlier in this chapter for gain and analog input channel bit patterns.
Register-Level Programming Appendix E 4. Program Counter A1 to force OUT1 low. If OUT1 is high, Counter A0 is disabled. Write 70 (hex) to the Counter A Mode Register (select Counter A1, Mode 0) to force OUT1 low. Counter A0 can be used as the Sample Interval Counter. 5. Clear the A/D circuitry. Before you start the data acquisition operation, the A/D FIFO must be emptied in order to clear out any old A/D conversion results.
Appendix E Register-Level Programming External Timing Considerations for Multiple A/D Conversions Two external timing signals, EXTTRIG and EXTCONV*, can be used for multiple A/D conversions. EXTTRIG can be used to initiate a conversion sequence (posttrigger mode) or to terminate an ongoing conversion sequence (pretrigger mode), and the EXTCONV* signal can be used to time the individual A/D conversions from an external timing source.
Register-Level Programming Appendix E Using the EXTCONV* Signal to Initiate A/D Conversions As mentioned earlier, A/D conversions can be initiated by a falling edge on either OUTA0 or EXTCONV*. Setting the GATA0 bit low disables conversions from both OUTA0 and EXTCONV*. Setting the GATA0 bit high enables conversions from both OUTA0 and EXTCONV*. The GATA0 bit is set low whenever OUTA1 is high or SWTRIG in Command Register 1 is cleared.
Appendix E Register-Level Programming 3. Program Counter A0. Since a high-to-low transition on the Counter A0 output initiates an A/D conversion, Counter A0 output must be programmed to a high state. This ensures that Counter A0 does not cause any A/D conversions. Write 34 (hex) to the Counter A Mode Register (select Counter A0, Mode 2) to force OUT0 to a high state. This is an 8-bit operation. 4. Clear the A/D circuitry.
Register-Level Programming Appendix E Two error conditions may occur during a data acquisition operation: an overflow error or an overrun error. These error conditions are reported through the Status Register and should be checked every time the Status Register is read to check the DAVAIL bit. An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more data.
Appendix E Register-Level Programming 2. Program Counter A0. Since a high-to-low transition on the Counter A0 output initiates an A/D conversion, Counter A0 output must be programmed to a high state. This ensures that Counter A0 does not cause any A/D conversions. Write 34 (hex) to the Counter A Mode Register (select Counter A0, Mode 2) to force OUTO to a high state. This is an 8-bit operation. 3. Clear the A/D circuitry.
Register-Level Programming Appendix E 5. Start and service the data acquisition operation. To start the data acquisition operation, set the SWTRIG bit in Command Register 2. After this setting, A/D conversions are initiated by a falling edge on EXTCONV* input, but the sample counter (Counter A1) is not gated on until a rising edge on EXTTRIG input.
Appendix E Register-Level Programming Pretrigger Mode Pretriggering mode requires that the A/D conversions be shut off at a programmed time by the hardware after the trigger on EXTTRIG. Therefore, pretriggered data acquisition is not possible in freerun acquisition mode. Programming Multiple A/D Conversions with Channel Scanning The data acquisition programming sequences given earlier in this chapter are for programming the Lab-PC+ for multiple A/D conversions on a single input channel.
Register-Level Programming Appendix E acquisition operation is fully configured. Use the following sequence to configure the Lab-PC+ for interval scanning: 1. Write the configuration value indicating the highest channel number in the scan sequence, the gain, and the input polarity to the Analog Configuration Register. The SCANEN bit must be clear during this first write to the Analog Configuration Register. Immediately write a 0 to the INTSCAN bit in the Command Register 4.
Appendix E Register-Level Programming another N samples and the cycle repeats. The operation stops when the sample counter (Counter A1) decrements to 0. Use the following sequence to configure the Lab-PC+ for single-channel interval acquisition mode. 1. Write the count to the Interval Counter Data Register and strobe it in the counter. 2. Write the channel number and gain in Command Register 1. Write 0 to the SCANEN bit. 3. Write 1 to the INTSCAN bit in Command Register 4.
Register-Level Programming Appendix E To use the error interrupt, set the ERRINTEN bit in the Command Register 3. If this bit is set, an interrupt is generated whenever the OVERFLOW or the OVERRUN bit in the Status Register is set. This interrupt condition is cleared by writing to the A/D Clear Register. Programming DMA Operation The Lab-PC+ can be programmed so that the FIFO generates a DMA request signal every time one or more A/D conversion values are stored in the FIFO.
Appendix E Register-Level Programming updated when a low level is detected on either EXTUPDATE* or OUTA2. If LDAC0 is set low, the analog output from DAC0 is updated as soon as the DAC0 Data Register is written to. LDAC1 controls the updating of DAC1 analog output in a similar manner. The output voltage generated from the digital code depends on the configuration, unipolar or bipolar, of the associated analog output channel.
Register-Level Programming Appendix E The following formula calculates the voltage output versus digital code for a bipolar analog output configuration and two’s complement coding: Vout = 5.0 * (digital code) 2,048 The digital code in the above formula is a decimal value ranging from -2,048 to +2,047. Notice that two’s complement mode coding is selected by setting the 2SDAC bit high in Command Register 2. Table E-4.
Appendix E Register-Level Programming 3. Enable timer interrupts. Timer interrupts refer to the interrupts generated by rising edges on OUTA2 or EXTUPDATE*. A rising edge on OUTA2 or EXTUPDATE* sets the CNTINT bit high in the Status Register. A timer interrupt is generated whenever the CNTINT bit in the Status Register and the CNTINTEN bit in Command Register 3 are set high. Set the CNTINTEN bit in Command Register 3 high to enable timer interrupts.
Register-Level Programming Appendix E Group A D7 D6 D5 D4 Group B D3 D2 D1 D0 Control-Word Flag 1 = Mode Set Port C (low nibble) 1 = input 0 = output Mode Selection 00 = Mode 0 01 = Mode 1 1X = Mode 2 Port B 1 = input 0 = output Port A 1 = input 0 = output Mode Selection 0 = Mode 0 1 = Mode 1 Port C (high nibble) 1 = input 0 = output Figure E-1.
Appendix E Register-Level Programming Modes of Operation for the 8255A The three basic modes of operation for the 8255A are as follows: • Mode 0 – Basic I/O • Mode 1 – Strobed I/O • Mode 2 – Bidirectional bus The 8255A also has a single bit set/reset feature for Port C. The 8-bit control word also programs this function. For additional information, refer to Appendix C, OKI 82C55A Data Sheet. Mode 0 This mode is for simple I/O operations for each of the ports.
Register-Level Programming Appendix E Table E-5.
Appendix E Register-Level Programming Mode 1 This mode is used for transferring data with handshake signals. Ports A and B use the eight lines of Port C to generate or receive the handshake signals. This mode divides the ports into two groups (Group A and Group B). • Each group contains one 8-bit data port (Port A or Port B) and one 4-bit control/data port (upper or lower nibble of Port C). • The 8-bit data ports can be either input or output, both of which are latched.
Register-Level Programming Appendix E Port C status-word bit definitions for input (Port A and Port B): 7 6 5 4 3 2 1 0 I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB Bit Name Description 7-6 I/O Extra I/O status lines when Port A is in Mode 1 input. 5 IBFA Input buffer full for Port A. High indicates that data has been loaded into the input latch for Port A. 4 INTEA Interrupt enable bit for Port A. Enables interrupts from the 8255A for Port A. Controlled by bit set/reset of PC4.
Appendix E Register-Level Programming Programming Example Example 1. Configure Port A as an input port in Mode 1: • Write B0 (hex) to the Digital Control Register. • Wait for bit 5 of Port C (IBFA) to be set, indicating that data has been latched into Port A. • Read data from Port A. Example 2. Configure Port B as an input port in Mode 1: • Write 86 (hex) to the Digital Control Register. • Wait for bit 1 of Port C (IBFB) to be set, indicating that data has been latched into Port B.
Register-Level Programming Appendix E Port C status-word bit definitions for output (Port A and Port B): 7 6 5 4 3 2 1 0 OBFA* INTEA I/O I/O INTRA INTEB OBFB* INTRB Bit Name Description 7 OBFA* Output buffer full for Port A. Low indicates that the CPU has written data out to Port A. 6 INTEA Interrupt enable bit for Port A. If this bit is high, interrupts are enabled from the 8255A for Port A. Controlled by bit set/reset of PC6.
Appendix E Register-Level Programming Programming Example Example 1. Configure Port A as an output port in Mode 1: • Write A0 (hex) to the Digital Control Register. • Wait for bit 7 of Port C (OBFA*) to be cleared, indicating that the data last written to Port A has been read. • Write new data to Port A. Example 2. Configure Port B as an output port in Mode 1: • Write 84 (hex) to the Digital Control Register.
Register-Level Programming Appendix E 7 6 5 4 3 2 1 0 1 1 X X X 1/0 1/0 1/0 Port C bits (PC2-PC0) 1 = input 0 = output Port B direction 1 = input 0 = output Group B Mode 0 = Mode 0 1 = Mode 1 During a Mode 2 data transfer, the status of the handshaking lines and interrupt signals can be obtained by reading Port C. The Port C status-word bit definitions for a Mode 2 transfer are shown next.
Appendix E Register-Level Programming At the digital I/O connector, Port C has the following pin assignments when in Mode 2. Group A PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 OBFA* ACKA* IBFA STBA* INTRA I/O I/O I/O Programming Example Example. Configure Port A in Mode 2: • Write C0 (hex) to the Digital Control Register. • Wait for bit 7 of Port C (OBFA*) to be cleared, indicating that the data last written to Port A has been read. • Write new data to Port A.
Register-Level Programming Appendix E Single Bit Set/Reset Feature Any of the 8 bits of Port C can be set or reset with one control word. This feature is used to generate status and control for Port A and Port B when operating in Mode 1 or Mode 2. Interrupt Programming for the Digital I/O Circuitry Interrupts can be enabled on PC0, PC3, or both PC0 and PC3 by setting the DIOINTEN bit in Command Register 3. See the Command Register 3 description earlier in this chapter for corresponding bit positions.
Appendix F Customer Communication For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation. Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster. National Instruments provides comprehensive technical assistance around the world. In the U.S.
Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
Lab-PC+ Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: Lab-PC+ User Manual Edition Date: June 1996 Part Number: 320502B-01 Please comment on the completeness, clarity, and organization of the manual. If you find errors in the manual, please record the page numbers and describe the errors. Thank you for your help.
Glossary Prefix Meaning Value pnµmkMG- piconanomicromillikilomegagiga- 10-12 10-9 10-6 10-3 103 106 109 ° Ω % A A/D AC ADC AWG BCD C CMOS D/A DAC dB DC DIFF DIP DMA EISA F FIFO ft hex Hz I/O in.
Glossary NRSE PPI ppm PS/2 REXT RSE RTSI s SCXI SDK STC TTL V VDC VEXT VIH VIL Vin VOH VOL Vout Vref Lab-PC+ User Manual non-referenced single-ended programmable peripheral interface parts per million IBM Personal System/2 external resistance referenced single-ended Real-Time System Integration seconds Signal Conditioning eXtensions for Instrumentation (bus) System Development Kit system timing controller transistor-to-transistor logic volts volts direct current external volts volts, input high volts, in
Index Numbers 2SDAC0 bit, D-9 2SDAC1 bit, D-9 +5 V signal (table), 3-3 8253 Counter/Timer Register Groups A and B, D-23 to D-32 Counter A Mode Register description, D-27 interrupt programming for analog output circuitry, E-22 to E-23 Counter A0 Data Register controlled acquisition mode, E-6, E-7 posttrigger mode, E-13 pretrigger mode, E-15 description, D-24 freerun acquisition mode, 4-6, E-9 used as sample interval counter, E-9 Counter A1 Data Register controlled acquisition mode, E-7 posttrigger mode, E-13
Index A/D Clear Register clearing A/D FIFO, E-7 description, D-18 A/D Configuration Register, E-9 A/D conversion. See also multiple A/D conversions, programming.
Index input signals, 3-4 Lab-PC+ instrumentation amplifier (figure), 3-5 analog input specifications, A-1 to A-2 amplifier characteristics, A-2 dynamic characteristics, A-2 explanation, A-3 input characteristics, A-1 stability, A-2 transfer characteristics, A-1 analog output calibration, 5-6 to 5-8 bipolar output procedure, 5-6 to 5-7 board configuration, 5-6 unipolar output procedure, 5-8 analog output circuitry block diagram, 4-9 theory of operation, 4-9 to 4-10 analog output circuitry, programming, E-20
Index HWTRIG, 3-21, D-10, E-11, E-13, E-14 INTSCAN, D-14, E-17 to E-19 Lab-PC/PC+, D-7 LDAC0, D-9, E-20 to E-21 LDAC1, 3-23, D-9, E-20 to E-21 MA<2..0>, D-6 OVERFLOW, D-7, E-20. See also A/D FIFO overflow condition. OVERRUN, D-8, E-20. See also A/D FIFO overrun condition. PRETRIG, 3-21, D-10, E-11, E-12, E-14 SCANEN. See SCANEN bit. SE/D, D-13 SWTRIG. See SWTRIG bit.
Index PC bus interface, 2-1 factory settings (table), 2-3 parts locator diagram, 2-2 Configuration and Status Register Group, D-4 to D-14 Command Register 1 channel scanning, E-17 controlled acquisition mode, E-6 posttrigger mode, E-12 pretrigger mode, E-14 description, D-5 to D-6 freerun acquisition mode, E-9 selecting analog input channel, E-3 single-channel interval acquisition mode, E-19 Command Register 2, D-9 to D-10 Command Register 3 description, D-11 to D-12 digital I/O circuitry programming, E-34
Index D D<7..0> bits A/D FIFO Register, D-17 Counter A0 Data Register, D-24 Counter A1 Data Register, D-25 Counter A2 Data Register, D-26 Counter B0 Data Register, D-29 Counter B1 Data Register, D-30 Counter B2 Data Register, D-31 DAC0 Low-Byte and DAC1 Low-Byte Registers, D-22 Digital Control Register, D-37 Interval Counter Data Register, D-39 Port A Register, D-34 Port B Register, D-35 Port C Register, D-36 D<11..8> bits, D-22 D<15..8> bits, D-16, D-17 D<15..
Index Mode 1 output, E-29 to E-31 control words, E-29 Port C pin assignments, E-30 Port C status-word bit definitions, E-30 programming example, E-30 Mode 2 operation, E-31 to E-34 control words, E-31 to E-32 Port C pin assignments, E-33 Port C status-word bit definitions, E-32 programming example, E-33 single bit set/reset control words, E-33 single bit set/reset feature, E-34 Digital I/O Register Group. See 8255A Digital I/O Register Group.
Index EXTUPDATE* signal analog output circuitry programming, E-20 to E-21 data acquisition timing, 3-23 to 3-24 generating interrupts (figure), 3-24 updating DAC output (figure), 3-24 description (table), 3-3 interrupt programming for analog output circuitry, E-22 to E-23 F fax technical support, F-1 FIFOINTEN bit A/D interrupt programming, E-19 description, D-11 floating signal sources definition, 3-5 to 3-6 signal connection considerations differential connections, 3-8 to 3-9 recommended configurations
Index differential connection considerations, 3-6 to 3-9 floating signal sources, 3-8 to 3-9 ground-referenced signal sources, 3-7 to 3-8 recommended configurations for ground-referenced and floating signal sources (table), 3-6 single-ended connection considerations, 3-10 to 3-12 floating signal sources (RSE configuration), 3-10 to 3-11 grounded signal sources (NRSE configuration), 3-11 to 3-12 input modes, 2-10 to 2-11 DIFF input (four channels), 2-11 to 2-12 NRSE input (eight channels), 2-13 RSE input (e
Index disabling DMA transfers (figure), 2-7 factory settings (figure), 2-6 NRSE input, 2-13 PC bus interface factory settings (table), 2-3 RSE input, 2-12 unipolar output (figure), 2-10 L Lab-PC+ block diagram, 4-1 initializing, E-1 to E-2 optional equipment, 1-4 overview, 1-1 requirements, 1-1 software programming choices LabVIEW and LabWindows/CVI software, 1-2 NI-DAQ driver software, 1-2 to 1-3 register-level programming, 1-3 unpacking, 1-4 Lab-PC+ instrumentation amplifier analog input signal connecti
Index pretrigger mode, E-16 freerun acquisition programming, E-10 A/D interrupt programming, E-20 description, D-8 N NI-DAQ driver software, 1-2 to 1-3 NRSE input (eight channels) configuration, 2-13 definition (table), 2-11 signal connection considerations recommended configurations (table), 3-6 single-ended connections, 3-11 to 3-12 O OBF* signal description, 3-17 Mode 1 output timing, 3-19 Mode 2 bidirectional timing, 3-20 Port C signal assignments (table), 3-16 OBFA* status word, Port C Mode 1 output
Index PRETRIG bit controlled acquisition mode posttrigger mode, E-12 pretrigger mode, E-14 data acquisition timing, 3-21 description, D-10 multiple A/D conversions using EXTTRIG signal, E-11 pretrigger data acquisition timing (figure), 3-23 pretrigger mode controlled acquisition mode programming, E-14 to E-16 freerun acquisition mode programming, E-17 termination of multiple A/D conversions using EXTTRIG signal, E-11 programmable gain amplifier, 4-5 programming A/D interrupt programming, E-19 to E-20 analo
Index 8253 Counter/Timer Register Groups A and B, D-23 to D-32 8255A Digital I/O Register Group, D-33 to D-37 Analog Input Register Group, D-15 to D-20 Analog Output Register Group, D-21 to D-22 Configuration and Status Register Group, D-4 to D-14 Interval Counter Register Group, D-38 to D-40 programming considerations, E-1 register map (table), D-2 sizes, D-3 relative accuracy analog input, A-3 analog output, A-4 RSE input (eight channels) configuration, 2-12 definition (table), 2-11 signal connection con
Index grounded signal sources (NRSE configuration), 3-11 to 3-12 software programming choices LabVIEW and LabWindows/CVI software, 1-2 NI-DAQ driver software, 1-2 to 1-3 register-level programming, 1-3 specifications analog input, A-1 to A-2 amplifier characteristics, A-2 dynamic characteristics, A-2 explanation, A-3 input characteristics, A-1 stability, A-2 transfer characteristics, A-1 analog output, A-4 to A-5 dynamic characteristics, A-4 explanation, A-4 to A-5 output characteristics, A-4 stability, A-
Index general-purpose timing connections, 3-24 to 3-28 event-counting application with external switch gating (figure), 3-25 frequency measurement application (figure), 3-26 pretrigger timing (figure), 3-23 specifications and ratings, 3-27 timing requirements for GATE and CLK signals (figure), 3-27 timing I/O circuitry, 4-11 to 4-14 block diagram, 4-12 counter block diagram, 4-14 single-channel interval timing (figure), 4-14 two-channel interval-scanning timing (figure), 4-13 timing I/O specifications, A-5
