- National Semiconductor Memory Interface Circuits Specification Sheet

After the complement correct cycle, the memory must be
rewritten with the corrected data since the address now
contains data that is complemented. Full error reporting is
available from the DP8400 after the second read, the com-
plement read, of memory. This is shown in Table VI.
This method is a very effective tool to avoid system crash
due to memory chip failure, and can do much to reduce
unscheduled field service calls. The only time the system
will see a double error that is not directly correctable is
when a double soft error occurs. The probability of this is
very low if the previously discussed techniques are used.
The extra time taken to do an additional read and write of
memory is insignificant when the alternative is a system that
has a catastrophic failure that requires immediate field serv-
ice. Using this technique, software may be provided in the
system to warn the operator that the system is in a degrad-
ed operational mode and that field service should occur
shortly. In the meantime, the system will continue to operate
properly. The key to the effectiveness of the DP8400 in this
application is its three error flags which allow complete error
reportingÐincluding a unique double error indication.
DP8402A, 3, 4, 5 32-Bit Error Detector and Corrector
(EDAC)
In addition to the popular DP8400-2 16-bit error checker/
corrector, National offers a family of 32-bit Error Detector
and Correctors (EDACs). With a few exceptions, the
DP8402A, 3, 4, 5 function in a similar manner to the
DP8400-2. One major exception is that the DP8402A, 3, 4, 5
are not expandable beyond 32 bits.
TL/F/5012– 16
FIGURE 12. Double Error Correct Complement Hard Error
MethodÐ1 Hard Error and 1 Soft Error in Data Bits
TABLE VI. DP8400 Error Flags after a Complement Read
AE E1 E0 Error Type
0 0 0 Two Hard Errors
1 1 0 One Hard Error, One Soft Check Bit Error
1 1 1 One Hard Error, One Soft Data Bit Error
1 0 0 Two Soft Errors, Not Corrected
10