AT-MIO-16X User Manual Multifunction I/O Board for the PC AT/EISA October 1997 Edition Part Number 320640B-01 © Copyright 1992, 1997 National Instruments Corporation. All rights reserved.
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Important Information Warranty The AT-MIO-16X is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
Table of Contents About This Manual Organization of This Manual ........................................................................................ xv Conventions Used in This Manual................................................................................ xvi Related Documentation................................................................................................. xvii Customer Communication ............................................................................................
Table of Contents Analog Output Reference Selection............................................................... 2-11 Analog Output Polarity Selection .................................................................. 2-12 Digital I/O Configuration ............................................................................................. 2-12 Board and RTSI Clock Configuration.......................................................................... 2-12 Hardware Installation .........................
Table of Contents Chapter 3 Theory of Operation Functional Overview..................................................................................................... 3-1 PC I/O Channel Interface Circuitry .............................................................................. 3-2 Analog Input and Data Acquisition Circuitry............................................................... 3-5 Analog Input Circuitry ...................................................................................
Table of Contents Command Register 3 ....................................................................... 4-13 Command Register 4 ....................................................................... 4-20 Status Register 1 .............................................................................. 4-25 Status Register 2 .............................................................................. 4-30 Analog Input Register Group .....................................................................
Table of Contents Chapter 5 Programming Register Programming Considerations........................................................... 5-1 Resource Allocation Considerations .............................................................. 5-1 Initializing the AT-MIO-16X ......................................................................... 5-2 Initializing the Am9513A ................................................................ 5-3 Programming the Analog Input Circuitry................................
Table of Contents RTSI Switch Signal Connection Considerations.......................................................... 5-38 Programming the RTSI Switch .................................................................................... 5-39 Programming DMA Operations..................................................................... 5-41 Interrupt Programming...................................................................................
Table of Contents Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 2-11. Figure 2-12. Figure 2-13. Figure 2-14. Figure 2-15. Figure 2-16. Figure 2-17. Figure 2-18. Figure 2-19. AT-MIO-16X 68-Pin I/O Connector ..................................................... 2-16 AT-MIO-16X PGIA .............................................................................. 2-20 Differential Input Connections for Ground-Referenced Signals ...........
Table of Contents Figure 5-7. Figure 5-8. Figure 5-9. Figure 5-10. Cyclic Waveform Programming ........................................................... 5-27 Programmed Cycle Waveform Programming ....................................... 5-29 Pulsed Cyclic Waveform Programming................................................ 5-31 RTSI Switch Control Pattern................................................................. 5-40 Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5.
Table of Contents Table A-1. Table A-2. Table A-3. Equivalent Offset Errors in 16-Bit Systems .......................................... A-3 Equivalent Gain Errors in 16-Bit Systems............................................. A-4 Typical Multiple-Channel Scanning Settling Times ............................. A-5 Table B-1. Signal Connection Descriptions.............................................................
About This Manual This manual describes the mechanical and electrical aspects of the AT-MIO-16X board and contains information concerning its operation and programming. The AT-MIO-16X is a high-performance, multifunction analog, digital, and timing I/O board for the IBM PC AT and compatibles and EISA personal computers (PCs).
About This Manual • Appendix C, AMD Am9513A Data Sheet, contains the manufacturer data sheet for the AMD Am9513A System Timing Controller integrated circuit (Advanced Micro Devices, Inc.). This controller is used on the AT-MIO-16X. • Appendix D, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products.
About This Manual Related Documentation The following document contains information that you may find helpful as you read this manual: • IBM Personal Computer AT Technical Reference You may also want to consult the following Advanced Micro Devices information if you plan to program the Am9513A Counter/Timer used on the AT-MIO-16X: • Am9513A/Am9513 System Timing Controller Customer Communication National Instruments want to receive your comments on our products and manuals.
Chapter 1 Introduction This chapter describes the AT-MIO-16X, lists the contents of your AT-MIO-16X kit, the optional software, and optional equipment, and explains how to unpack the AT-MIO-16X. About the AT-MIO-16X Congratulations on your purchase of the National Instruments AT-MIO-16X. The AT-MIO-16X is a high-performance, software-configurable 16-bit DAQ board for laboratory, test and measurement, and data acquisition and control applications.
Chapter 1 Introduction signals for communication and control. SCXI is the instrumentation front end for plug-in DAQ boards. Analog Input The AT-MIO-16X is a high-performance multifunction analog, digital, and timing I/O board for the PC.
Chapter 1 Introduction Digital and Timing I/O In addition to the analog input and analog output capabilities of the AT-MIO-16X, the AT-MIO-16X also has eight digital I/O lines that can sink up to 24 mA of current, and three independent 16-bit counter/timers for frequency counting, event counting, and pulse output applications. The AT-MIO-16X has timer-generated interrupts, a high-performance RTSI bus interface, and four triggers for system-level timing.
Chapter 1 Introduction ❑ AT-MIO-16X User Manual ❑ One of the following software packages and documentation: ComponentWorks LabVIEW for Windows LabWindows/CVI for Windows Measure NI-DAQ for PC Compatibles VirtualBench ❑ Your computer Software Programming Choices You have several options to choose from when programming your National Instruments DAQ and SCXI hardware. You can use National Instruments application software, NI-DAQ, or register-level programming.
Chapter 1 Introduction VirtualBench features virtual instruments that combine DAQ products, software, and your computer to create a stand-alone instrument with the added benefit of the processing, display, and storage capabilities of your computer. VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word processors.
Chapter 1 Introduction Conventional Programming Environment ComponentWorks, LabVIEW, LabWindows/CVI, or VirtualBench NI-DAQ Driver Software DAQ or SCXI Hardware Personal Computer or Workstation Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware Register-Level Programming The final option for programming any National Instruments DAQ hardware is to write register-level software.
Chapter 1 Introduction Optional Equipment National Instruments offers a variety of products to use with your AT-MIO-16X board, including cables, connector blocks, and other accessories, as follows: • Cables and cable assemblies, shielded and ribbon • Connector blocks, shielded and unshielded 50 and 68-pin screw terminals • Real Time System Integration (RTSI) bus cables • SCXI modules and accessories for isolating, amplifying, exciting, and multiplexing signals for relays and analog output.
Chapter Configuration and Installation 2 This chapter explains board configuration, installation of the AT-MIO-16X into the PC, signal connections to the AT-MIO-16X, and cable considerations. 1 4 1 3 Product Name, Assembly Number, and Revision Letter 2 Fuse 3 2 U112 4 Spare Fuse Figure 2-1.
Chapter 2 Configuration and Installation 1 4 1 3 Product Name, Assembly Number, and Revision Letter 2 Fuse 3 2 U112 4 Spare Fuse Figure 2-2. AT-MIO-16X with 68-Pin I/O Connector Parts Locator Diagram Board Configuration The AT-MIO-16X contains one DIP switch to configure the base address selection for the AT bus interface. The remaining resource selections, such as DMA and interrupt channel selections, are determined by programming the individual registers in the AT-MIO-16X register set.
Chapter 2 Configuration and Installation The PC defines accesses to plug-in boards to be I/O mapped accesses within the I/O space of the computer. Locations are either written to or read from as bytes or words. Each register in the register set is mapped to a certain offset from the base address selection of the board as read or write, and as a word or byte location as defined by the decode circuitry. Base I/O Address Selection The AT-MIO-16X is configured at the factory to a base I/O address of 220 hex.
Chapter 2 Configuration and Installation The base address DIP switch is arranged so that a logical 1 or true state for the associated address selection bit is selected by pushing the toggle switch up, or toward the top of the board. Alternately, a logical 0 or false state is selected by pushing the toggle switch down, or toward the bottom of the board. In Figure 2-3B, A9 is up (true), A8 through A6 are low (false), and A5 is up (true). This represents a binary value of 10001XXXXX, or hex 220.
Chapter 2 Configuration and Installation Table 2-1.
Chapter 2 Configuration and Installation Table 2-2.
Chapter 2 Configuration and Installation Interrupt and DMA Channel Selection The base I/O address selection is the only resource on the AT-MIO-16X board that must be set manually before the board is placed into the PC. The interrupt level and DMA channels used by the AT-MIO-16X are selected via registers in the AT-MIO-16X register set. The AT-MIO-16X powers up with all interrupt and DMA requests disabled.
Chapter 2 Configuration and Installation Table 2-3. Available Input Configurations for the AT-MIO-16X Configuration Description DIFF Differential configurationnput of the PGIA tied to the multiplexer output of Channels 8 through 15. RSE Referenced single-ended configurationve (–) input of the PGIA referenced to analog ground. NRSE Nonreferenced single-ended configurationative (–) input of the PGIA tied to AI SENSE and not connected to ground.
Chapter 2 Configuration and Installation RSE Input (16 Channels) RSE input means that all input signals are referenced to a common ground point that is also tied to the analog input ground of the AT-MIO-16X board. The negative (–) input of the differential input amplifier is tied to the analog ground. This configuration is useful when measuring floating signal sources. See the Types of Signal Sources section later in this chapter for more information.
Chapter 2 Configuration and Installation • Note: Multiplexer control is configured to control up to 16 input channels. The NRSE input mode is the only mode in which the AI SENSE signal from the I/O connector is used as an input. In all other modes, AI SENSE is either programmed to be unused or driven with the board analog input ground. Considerations for using the NRSE input configuration are discussed in the Signal Connections section later in this chapter.
Chapter 2 Configuration and Installation Table 2-4. Actual Range and Measurement Precision Versus Input Range Selection and Gain Range Configuration Gain Actual Input Range Precision* 0 to +10 V 1.0 2.0 5.0 10.0 20.0 50.0 100.0 0 to +10.0 V 0 to +5.0 V 0 to +2.0 V 0 to +1.0 V 0 to +0.5 V 0 to +0.2 V 0 to 100.0 mV 152.59 µV 76.29 µV 30.52 µV 15.26 µV 7.63 µV 3.05 µV 1.53 µV –10 to +10 V 1.0 2.0 5.0 10.0 20.0 50.0 100.0 –10.0 to +10.0 V –5.0 to +5.0 V –2.0 to +2.0 V –1.0 to +1.0 V –0.5 to +0.
Chapter 2 Configuration and Installation Analog Output Polarity Selection Each analog output channel can be configured for either unipolar or bipolar output. A unipolar configuration has a range of 0 to V ref at the analog output. A bipolar configuration has a range of –V ref to +Vref at the analog output. V ref is the voltage reference used by the DACs in the analog output circuitry and can be either the 10-V onboard reference or an externally supplied reference between –18 and +18 V.
Chapter 2 Configuration and Installation The AT-MIO-16X can use either its internal 10-MHz timebase, or it can use a timebase received over the RTSI bus. In addition, if the board is configured to use the internal timebase, it can also be programmed to drive its internal timebase over the RTSI bus to another board that is programmed to receive this timebase signal. This clock source, whether local or from the RTSI bus, is then divided by 10 and used as the Am9513A frequency source.
Chapter 2 Configuration and Installation Signal Connections This section describes input and output signal connections to the AT-MIO-16X board via the AT-MIO-16X I/O connector. This section also includes specifications and connection instructions for the signals given on the AT-MIO-16X I/O connector. Caution: AT-MIO-16X User Manual Connections that exceed any of the maximum ratings of input or output signals on the AT-MIO-16X can result in damage to the AT-MIO-16X board and to the PC.
Chapter 2 Configuration and Installation Figure 2-4 shows the pin assignments for the AT-MIO-16X 50-pin I/O connector.
Chapter 2 Configuration and Installation Figure 2-5 shows the pin assignments for the AT-MIO-16X 68-pin I/O connector.
Chapter 2 Configuration and Installation Signal Connection Descriptions Signal Names Reference Descriptions AI GND N/A Analog Input Ground—These pins are the reference point for single-ended measurements and the bias current return point for differential measurements. ACH<0..15> AI GND Analog Input Channels 0 through 15—In differential mode, the input is configured for up to eight channels. In single-ended mode, the input is configured for up to 16 channels.
Chapter 2 Configuration and Installation Signal Names Reference Descriptions SCANCLK DIG GND Scan Clock—This pin pulses once for each A/D conversion in the scanning modes. The low-to-high edge indicates when the input signal can be removed from the input or switched to another signal. EXTSTROBE* DIG GND External Strobe—Writing to the EXTSTROBE Register results in a minimum 500-nsec low pulse on this pin.
Chapter 2 Signal Names Reference Configuration and Installation Descriptions OUT5 DIG GND OUT5—This pin is from the Am9513A Counter 5 signal. FOUT DIG GND Frequency Output—This pin is from the Am9513A FOUT signal. The signals on the connector can be classified as analog input signals, analog output signals, digital I/O signals, digital power connections, or timing I/O signals. Signal connection guidelines for each of these groups are given in the following section.
Chapter 2 Configuration and Installation Programmable Gain V in+ + + Gain V in- - Vm Measured Voltage - Gain = 1, 2, 5, 10, 20, 50, 100 V m = [ V in+ - V in - ] * GAIN Figure 2-6. AT-MIO-16X PGIA The AT-MIO-16X PGIA applies gain and common-mode voltage rejection, and presents high-input impedance to the analog input signals connected to the AT-MIO-16X board. Signals are routed to the positive (+) and negative (–) inputs of the PGIA through input multiplexers on the AT-MIO-16X.
Chapter 2 Configuration and Installation Types of Signal Sources When configuring the input mode of the AT-MIO-16X and making signal connections, you must first determine whether the signal source is floating or ground-referenced. These two types of signals are described in the following sections. Floating Signal Sources A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground reference point.
Chapter 2 Configuration and Installation Table 2-5 summarizes the recommended input configuration for both types of signal sources. Table 2-5.
Chapter 2 Configuration and Installation Differential Connections for Ground-Referenced Signal Sources Figure 2-7 shows how to connect a ground-referenced signal source to an AT-MIO-16X board configured in the DIFF input mode. The AT-MIO-16X analog input circuitry must be configured for DIFF input to make these types of connections. Configuration instructions are included in Chapter 4, Register Map and Descriptions. ACH<0..7> GroundReferenced Signal Source + V s PGIA + - Gain ACH<8..
Chapter 2 Configuration and Installation Differential Connections for Nonreferenced or Floating Signal Sources Figure 2-8 shows how to connect a floating signal source to an AT-MIO-16X board configured in the DIFF input mode. The AT-MIO-16X analog input circuitry must be configured for DIFF input to make these types of connections. Configuration instructions are included in Chapter 4, Register Map and Descriptions. ACH<0..7> Bias Resistors Floating Signal Source + V s PGIA + - Gain ACH<8..
Chapter 2 Configuration and Installation connect the negative side of the signal to AI GND as well as to the negative (–) input of the PGIA. This works well for DC-coupled sources with low source impedance (less than 100 Ω). However, for larger source impedances, this connection leaves the differential signal path significantly out of balance. Noise that couples electrostatically onto the positive (+) line does not couple onto the negative (–) line because it is connected to ground.
Chapter 2 Configuration and Installation resistors. For example, if two 100-kΩ bias resistors are used, there could be as much as 200 µV of input offset voltage (0.66 LSB at a gain of 1, bipolar range). Single-Ended Connection Considerations Single-ended connections are those in which all AT-MIO-16X analog input signals are referenced to one common ground. The input signals are tied to the positive (+) input of the PGIA, and their common ground point is tied to the negative (–) input of the PGIA.
Chapter 2 Configuration and Installation and 15 are on pins 17 and 18, which are the farthest analog inputs from AI GND. The sensitivities to noise of the other channels in the middle are between those of Channels 0 and 15 and vary according to their distance from AI GND.
Chapter 2 Configuration and Installation Single-Ended Connections for Grounded Signal Sources (NRSE Configuration) If a grounded signal source is to be measured with a single-ended configuration, then the AT-MIO-16X must be configured in the NRSE input configuration. The signal is connected to the positive (+) input of the AT-MIO-16X PGIA and the signal local ground reference is connected to the negative (–) input of the AT-MIO-16X PGIA.
Chapter 2 Configuration and Installation Common-Mode Signal Rejection Considerations Figures 2-7 and 2-8, located earlier in this chapter, show connections for signal sources that are already referenced to some ground point with respect to the AT-MIO-16X. In these cases, the PGIA can reject any voltage caused by ground potential differences between the signal source and the AT-MIO-16X.
Chapter 2 Configuration and Installation The following ranges and ratings apply to the EXTREF input: Normal input voltage range ±10 V peak with respect to AO GND Usable input voltage range ±18 V peak with respect to AO GND Absolute maximum ratings ±30 V peak with respect to AO GND AO GND is the ground reference point for both analog output channels and for the external reference signal.
Chapter 2 Configuration and Installation Digital I/O Signal Connections The digital lines ADIO<0..3> are connected to digital I/O port A. The digital lines BDIO<0..3> are connected to digital I/O port B. DIG GND is the digital ground pin for both digital I/O ports. Ports A and B can be programmed individually to be inputs or outputs. The following specifications and ratings apply to the digital I/O lines. Absolute maximum voltage input rating 5.
Chapter 2 Configuration and Installation +5 V LED Port A ADIO<3..0> Port B TTL Signal BDIO<3..0> +5 V Switch DIG GND I/O Connector AT-MIO-16X Board Figure 2-12. Digital I/O Connections In Figure 2-12, port A is configured for digital output, and port B is configured for digital input. Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2-12.
Chapter 2 Caution: Configuration and Installation Under no circumstances should these +5-V power pins be directly connected to analog or digital ground or to any other voltage source on the AT-MIO-16X or any other device. Doing so can damage the AT-MIO-16X and the PC. National Instruments is not liable for damages resulting from such a connection.
Chapter 2 Configuration and Installation EXTCONV* Signal A/D conversions can be externally triggered with the EXTCONV* pin. Applying an active low pulse to the EXTCONV* signal initiates an A/D conversion. Figure 2-14 shows the timing requirements for the EXTCONV* signal. tw VIH VIL tw tw 50 nsec minimum ADC switches to hold mode within 100 nsec from this point Figure 2-14. EXTCONV* Signal Timing The minimum allowed pulse width is 50 ns.
Chapter 2 Configuration and Installation EXTTRIG* Signal Any data acquisition sequence can be initiated by an external trigger applied to the EXTTRIG* pin. Applying a falling edge to the EXTTRIG* pin starts the sample and sample-interval counters, thereby initiating a data acquisition sequence. Figure 2-15 shows the timing requirements for the EXTTRIG* signal. tw VIH VIL tw tw 50 nsec minimum First A/D conversion starts within 1 sample interval from this point Figure 2-15.
Chapter 2 Configuration and Installation EXTGATE* Signal EXTGATE* is an input signal used for hardware gating. EXTGATE* controls A/D conversion pulses. If EXTGATE* is low, no A/D conversion pulses occur from EXTCONV* or the sample-interval counter. If EXTGATE* is high, conversions take place if programmed and otherwise enabled. EXTTMRTRIG* Signal The analog output DACs on the AT-MIO-16X can be updated using either internal or external signals in posted update mode.
Chapter 2 Configuration and Installation Counter Signal Connections The general-purpose timing signals include the GATE and OUT signals for the Am9513A Counters 1, 2, and 5, SOURCE signals for Counters 1 and 5, and the FOUT signal generated by the Am9513A. Counters 1, 2, and 5 of the Am9513A Counter/Timer can be used for general-purpose applications, such as pulse and square wave generation, event counting, pulse-width, time-lapse, and frequency measurements.
Chapter 2 Configuration and Installation +5 V 4.7 kΩ SOURCE OUT GATE Switch Counter Signal Source DIG GND I/O Connector AT-MIO-16X Board Figure 2-17. Event-Counting Application with External Switch Gating To perform pulse-width measurement, a counter is programmed to be level gated. The pulse to be measured is applied to the counter GATE input. The counter is programmed to count while the signal at the GATE input is either high or low.
Chapter 2 Configuration and Installation To measure frequency, a counter is programmed to be level gated and the rising or falling edges are counted in a signal applied to a SOURCE input. The gate signal applied to the counter GATE input is of some known duration. In this case, the counter is programmed to count either rising or falling edges at the SOURCE input while the gate is applied. The frequency of the input signal is then the count value divided by the known gate period.
Chapter 2 Configuration and Installation The signals for Counters 1, 2, and 5, and the FOUT output signal are directly tied from the Am9513A input and output pins to the I/O connector. In addition, the GATE, SOURCE, and OUT1 pins are pulled up to +5 V through a 4.7-kΩ resistor. The input and output ratings and timing specifications for the Am9513A signals are given as follows: Absolute maximum voltage input rating –0.5 V to +7.
Chapter 2 t sc SOURCE t sp OUT t sp V IH V IL t gsu GATE Configuration and Installation t gh V IH V IL t gw t out V OH VOL t sc t sp t gsu t gh t gw t out 145 nsec 70 nsec 100 nsec 10 nsec 145 nsec 300 nsec minimum minimum minimum minimum minimum maximum Figure 2-19. General-Purpose Timing Signals The GATE and OUT signal transitions in Figure 2-17 are referenced to the rising edge of the SOURCE signal. This timing diagram assumes that the counters are programmed to count rising edges.
Chapter 2 Configuration and Installation register in the AT-MIO-16X register set and then divided by 10. The default value is 1 MHz into the Am9513A (10-MHz clock signal on the AT-MIO-16X). The six internal timebase clocks can be used as counting sources, and these clocks have a maximum skew of 75 nsec between them. The SOURCE signal shown in Figure 2-19 represents any of the signals applied at the SOURCE inputs, GATE inputs, or internal timebase clocks.
Chapter 2 Configuration and Installation You can minimize noise pickup and maximize measurement accuracy by doing the following: • Use differential analog input connections to reject common-mode noise. • Use individually shielded, twisted-pair wires to connect analog input signals to the AT-MIO-16X. With this type of wire, the signals attached to the CH+ and CH– inputs are twisted together and then covered with a shield. This shield is then connected only at one point to the signal source ground.
Chapter 2 Configuration and Installation The CB-50 is useful for prototyping an application or in situations where AT-MIO-16X interconnections are frequently changed. When you develop a final field wiring scheme, however, you may want to develop your own cable. This section contains information and guidelines for designing custom cables. In making your own cabling, you may decide to shield your cables.
Chapter 3 Theory of Operation This chapter contains a functional overview of the AT-MIO-16X and explains the operation of each functional unit making up the AT-MIO-16X. Functional Overview The block diagram in Figure 3-1 is a functional overview of the AT-MIO-16X board.
Chapter 3 Theory of Operation The following major components make up the AT-MIO-16X board: • PC I/O channel interface circuitry • Analog input circuitry • Data acquisition circuitry • Analog output circuitry • DAC waveform generation circuitry • Digital I/O circuitry • Timing I/O circuitry • RTSI bus interface circuitry The internal data and control buses interconnect the components. The theory of operation of each of these components is explained in the remainder of this chapter.
Chapter 3 Address Address Latches Bus PC I/O Channel Timing Interface PC I/O Channel I/O Channel Control Lines Data Bus Address Decoder 16 / Internal Data Bus AT-MIO-16X DMA Request DMA Control Circuitry DMA Acknowledge AT-MIO-16X DMA Acknowledge and Terminal Count Interrupt Control Circuitry IRQ Register Selects Read-and-Write Signals Data Buffers DMA Request Theory of Operation AT-MIO-16X Interrupt Request Figure 3-2.
Chapter 3 Theory of Operation conflicts with any other equipment in your PC, you must change the base address of the AT-MIO-16X or of the other device. See Chapter 2, Configuration and Installation, for more information. The PC I/O channel interface timing signals are used to generate read-and-write signals and to define the transfer cycle size. A transfer cycle can be either an 8-bit or a 16-bit data I/O operation.
Chapter 3 Theory of Operation selected for DMA transfer. These DMA channels are selectable from one of the registers in the AT-MIO-16X register set. Analog Input and Data Acquisition Circuitry The AT-MIO-16X handles 16 channels of analog input with software-programmable configuration and 16-bit A/D conversion. In addition, the AT-MIO-16X contains data acquisition configuration for automatic timing of multiple A/D conversions and includes advanced options such as external triggering, gating, and clocking.
Chapter 3 Theory of Operation Analog Input Circuitry The analog input circuitry consists of an input multiplexer, multiplexer-mode selection circuitry, a PGIA, calibration circuitry, a 16-bit sampling ADC, and a 16-bit, 512-word deep FIFO. A/D Converter The ADC is a 16-bit, sampling, successive approximation ADC. With 16-bit resolution, the converter can resolve its input range into 65,536 different steps.
Chapter 3 Theory of Operation input of the PGIA in single-ended mode is connected to either the input ground or the AI SENSE signal at the I/O connector depending on the nature of the input signals. PGIA The PGIA fulfills two purposes on the AT-MIO-16X board. It converts a differential input signal into a single-ended signal with respect to the AT-MIO-16X ground for input common-mode signal rejection.
Chapter 3 Theory of Operation bipolar modes, and these values are also permanently stored in the EEPROM. Calibration constants can be read from the EEPROM then written to the calibration DACs that adjust pregain offset, postgain offset, and gain errors associated with the analog input section.
Chapter 3 Theory of Operation When the ADC value is shifted into the ADC FIFO buffer by FIFO_LD*, a signal is generated that indicates valid data is available to be read. Single conversion timing of this type is appropriate for reading channel data on an ad hoc basis. However, if a sequence of conversions is needed, this method is not very reliable because it relies on the software to generate the conversions in the case of the strobe register.
Chapter 3 Theory of Operation acquisition sequence that employs external conversion timing, conversions are inhibited by the hardware until a trigger condition is received, then the programmed number of conversions occurs, and conversions are inhibited after the sequence completes. When using internal timing, the EXTCONV* signal at the I/O connector must be left unconnected or in the high-impedance state. Data acquisition can be controlled by the onboard sample counter.
Chapter 3 Theory of Operation In this sequence, the sample-interval counter, Counter 3, is programmed to generate conversion signals only under a certain gating signal, such as the DAQPROG signal. In addition, the sample counter, Counter 4, is programmed to count the number of conversions generated. In this case, the sample counter is programmed to count 10 samples, then stop the acquisition sequence. A signal is generated at the end of the sequence to indicate its completion.
Chapter 3 Theory of Operation the sample timer is independent of the gating signal, and for pretrigger sequences, the sample timer is dependent on the gating signal. Multiple-Channel Data Acquisition Multiple-channel data acquisition is performed by enabling scanning during data acquisition. Multiple-channel scanning is controlled by the configuration memory register. The configuration memory register consists of 512 words of memory.
Chapter 3 Theory of Operation Continuous Scanning Data Acquisition Timing Continuous scanning data acquisition uses the configuration memory register to automatically sequence from one analog input channel setting to another during the data acquisition sequence. Continuous scanning cycles through the configuration memory without any delays between cycles. Scanning is similar to the single-channel acquisition in the programming of both the sample-interval counter and the sample counter.
Chapter 3 Theory of Operation Interval Scanning Data Acquisition Timing Interval scanning assigns a time between the beginning of consecutive scan sequences. If only one scan sequence is in the configuration memory list, the circuitry stops at the end of the list and waits the necessary interval time before starting the scan sequence again.
Chapter 3 Theory of Operation Data Acquisition Rates The acquisition and channel selection hardware function so that in the channel scanning mode, the next channel in the channel configuration register is selected immediately after the conversion process has begun on the previous channel. With this method, the input multiplexers and the PGIA begin to settle to the new value while the conversion of the last value is still taking place.
Chapter 3 Theory of Operation REF Selection x2 +5 V INT REF Internal REF From Gain DAC1 REF DAC1WR DAC1 OUT From Offset DAC1 DATA / 16 From Offset DAC0 I/O Connector PC I/O Channel DAC1 DAC0 AO GND DAC0 OUT REF DAC0WR EXTREF +5 V INT REF x2 Internal REF From Gain DAC0 REF Selection Figure 3-9.
Chapter 3 Theory of Operation The output voltage is available on the AT-MIO-16X I/O connector DAC0 OUT and DAC1 OUT pins.
Chapter 3 Theory of Operation AT-MIO-16X board can be recalibrated without external hardware at any time under any number of different operating conditions in order to remove errors caused by temperature drift and time. The AT-MIO-16X is factory calibrated in both unipolar and bipolar modes, and these values are also permanently stored in the EEPROM.
Chapter 3 Theory of Operation Update* RTSI Latch Serial RTSI Data LATCHEN* R_Latch* DAC0 Local Latch Local Data Bus DAC Data Bus L_Latch* LATCHEN* DAC1 FIFO IN OUT DACFIFOWR* DACFIFORD* DACFIFORT* DACFIFORS* From Control Circuitry DACFIFOFF* DACFIFOHF* DACFIFOEF* To Control Circuitry Figure 3-10. Analog Output Waveform Circuitry The local latch is used for immediate updating of the DACs.
Chapter 3 Theory of Operation latch concurrently or separately. In this instance, the value written to the DAC through the local latch is not updated until the update pulse trigger occurs. If the RTSI latch is used to transfer serial data from the AT-DSP2200 over the RTSI bus, no other transferring path is allowed. In other words, data cannot be transmitted serially over the RTSI bus to DAC Channel 0 and transferred through the FIFO to DAC Channel 1 at the same time. These modes are mutually exclusive.
Chapter 3 Theory of Operation In Figure 3-11, the update trigger signal serves to update the previously written value to the DAC. In the posted update mode, the DAC FIFO is used to buffer the data. Requests are generated either when the FIFO is not full or when the FIFO is less than half full. One of these two signals generates the TMRREQ signal. In the example above, requesting is generated when the FIFO is not full.
Chapter 3 Theory of Operation continuous waveform. The advantage of having the data in the DAC FIFO is that the FIFO never needs to have the data refreshed, therefore it is never empty. Rather than requesting new data, the FIFO simply reuses existing data, removing a large demand on the PC bus bandwidth. Maximum updating performance is achieved in this mode because it does not rely on the speed of the computer.
Chapter 3 Theory of Operation FIFO Programmed Cyclic Waveform Generation One step beyond the continuous waveform generation is the programmed cyclic waveform generation. This mode is also available only when the entire buffer fits within the DAC FIFO. Figure 3-14 shows the operation of this mode. DACFIFORT* 5 COUNTER 1, 2, or 5 4 3 2 1 0 5 Figure 3-14.
Chapter 3 Theory of Operation In the pulsed waveform application, Counter 1 of the Am9513A is programmed to count the number of retransmit signals, before terminating the sequence. At this point, Counter 2 serves as an interval timer and then restarting the sequence. This process proceeds ad infinitum until the timer trigger is removed or disabled, or the CYCLICSTOP bit is set. Digital I/O Circuitry The AT-MIO-16X has eight digital I/O lines.
Chapter 3 Theory of Operation The digital I/O lines are controlled by the Digital Output Register and monitored by the Digital Input Register. The Digital Output Register is an 8-bit register that contains the digital output values for both ports 0 and 1. When port 0 is enabled, bits <3..0> in the Digital Output Register are driven onto digital output lines ADIO<3..0>. When port 1 is enabled, bits <7..4> in the Digital Output Register are driven onto digital output lines BDIO<3..0>.
Theory of Operation 1 MHz FOUT Am9513A Five-Channel Counter/ Timer GATE1 SOURCE1 OUT1 GATE5 SOURCE5 OUT5 5 MHz EXTTRIG* ÷2 / 16 / 2 SOURCE4 SOURCE3 Flip Flop GATE4 TE4 GA BRDCLK (10 MHz) SOURCE2 I/O Connector GATE2 OUT2 ÷5 DATA<15..0> Am9513A RD/WR RTSI Bus OUT1 OUT2 OUT3 OUT4 OUT5 GATE3 PC I/O Channel Chapter 3 CONVERT Data Acquisition Timing SCANCLK CONFIGCLK Figure 3-17.
Chapter 3 Theory of Operation SOURCE Counter OUT GATE Figure 3-18. Counter Block Diagram Each counter has a SOURCE input pin, a GATE input pin, and an output pin labeled OUT. The Am9513A counters are numbered 1 through 5, and their GATE, SOURCE, and OUT pins are labeled GATE N, SOURCE N, and OUT N, where N is the counter number.
Chapter 3 Theory of Operation counter applications, the counter reloads from an internal register when it reaches TC. In TC pulse output mode, the counter generates a pulse during the cycle that it reaches TC and reloads. In TC toggle output mode, the counter output changes state after it reaches TC and reloads. In addition, the counters can be configured for positive logic output or negative (inverted) logic output for a total of four possible output signals generated for one timing mode.
Chapter 3 Theory of Operation Counter 5 is sometimes used by the data acquisition timing circuitry and concatenated with Counter 4 to form a 32-bit sample counter. The SCANCLK signal is connected to the SOURCE3 input of the Am9513A, and OUT1 is sent to the data acquisition timing circuitry. This allows Counter 1 to be used to divide the SCANCLK signal for generating the CONFIGCLK signal. See the Data Acquisition Timing Circuitry section earlier in this chapter.
Chapter 3 Theory of Operation The RTSICLK line can be used to source a 10-MHz signal across the RTSI bus or to receive another clock signal from another AT board connected to the RTSI bus. BRDCLK is the system clock used by the AT-MIO-16X. Bits in a command register in the AT-MIO-16X register set control how these clock signals are routed. The RTSI switch is a National Instruments custom integrated circuit that acts as a 7×7 crossbar switch. Pins B<6..0> are connected to the seven RTSI bus trigger lines.
Chapter Register Map and Descriptions 4 This chapter describes in detail the address and function of each of the AT-MIO-16X control and status registers. Note: If you plan to use a programming software package such as NI-DAQ or LabWindows/CVI with your AT-MIO-16X board, you need not read this chapter. However, you will gain added insight into your AT-MIO-16X board by reading this chapter. Register Map The register map for the AT-MIO-16X is shown in Table 4-1.
Chapter 4 Register Map and Descriptions Table 4-1.
Chapter 4 Register Map and Descriptions Register Sizes Two different transfer sizes for read-and-write operations are available on the PC: byte (8-bit) and word (16-bit). Table 4-1 shows the size of each AT-MIO-16X register. For example, reading the ADC FIFO Register requires a 16-bit (word) read operation at the selected address, whereas writing to the RTSI Strobe Register requires an 8-bit (byte) write operation at the selected address.
Chapter 4 Register Map and Descriptions Configuration and Status Register Group The six registers making up the Configuration and Status Register Group allow general control and monitoring of the AT-MIO-16X hardware. Command Registers 1, 2, 3, and 4 contain bits that control operation of several different pieces of the AT-MIO-16X hardware. Status Registers 1 and 2 can be used to read the state of different pieces of the AT-MIO-16X hardware.
Chapter 4 Register Map and Descriptions Command Register 1 Command Register 1 contains 11 bits that control AT-MIO-16X serial device access, and data acquisition mode selection. The contents of this register are not defined upon power up and are not cleared after a reset condition. This register should be initialized through software.
Chapter 4 Register Map and Descriptions application of the appropriate load signal. AT-MIO-16X User Manual 12 SCANDIV Scan Divide—This bit controls the configuration memory ssequencing during scanned data acquisition. If SCANDIV is set, then sequencing is controlled by Counter 1 of the Am9513A Counter/Timer. If SCANDIV is cleared, the configuration memory is sequenced after each conversion during scanning. 11 0 Reserved—This bit must always be set to zero.
Chapter 4 Register Map and Descriptions thereby initiating a data acquisition operation. If DAQEN is cleared, software and hardware triggers have no effect. 7 SCANEN Scan Enable—This bit controls multiple-channel scanning during data acquisition. If SCANEN is set and DAQEN is also set, alternate analog input channels are sampled during data acquisition under control of the channel configuration memory.
Chapter 4 Register Map and Descriptions concatenated with Counter 5 to control conversion counting. A 16-bit count mode can be used if the number of A/D sample conversions to be performed is less than 65,537. A 32-bit count mode should be used if the number of A/D sample conversions to be performed is greater than or equal to 65,537. AT-MIO-16X User Manual 4 RTSITRIG RTSI Trigger—This bit controls multiple board synchronization through RTSI Bus triggering.
Chapter 4 Register Map and Descriptions Command Register 2 Command Register 2 contains 15 bits that control AT-MIO-16X RTSI bus transceivers, analog output configuration, and DMA Channels A and B selection. Bits 8-15 of this register are cleared upon power up and after a reset condition. Bits 0-7 of this register are undefined upon power up and are not cleared after a reset condition. These bits should be initialized through software.
Chapter 4 Register Map and Descriptions AT-MIO-16X User Manual 13 A2RCV RTSI A2 Receive—This bit controls the driver that allows the GATE1 signal to be driven from pin A2 of the RTSI switch. If A2RCV is set, pin A2 of the RTSI switch drives the GATE1 signal. In this case, GATE1 may not be driven by a signal at the I/O connector. 12 A2DRV RTSI A2 Drive—This bit controls the driver that allows the OUT2 signal to drive pin A2 of the RTSI switch.
Chapter 4 Register Map and Descriptions 9 EXTREFDAC1 External Reference for DAC 1—This bit controls the reference selection for DAC 1 in the analog output section. If this bit is set, the reference used for DAC 1 is the external reference voltage from the I/O connector. If this bit is cleared, the internal +10 Vref is used for the DAC 1 reference. 8 EXTREFDAC0 External Reference for DAC 0—This bit controls the reference selection for DAC 0 in the analog output section.
Chapter 4 Register Map and Descriptions Table 4-2.
Chapter 4 Register Map and Descriptions Command Register 3 Command Register 3 contains 16 bits that control the ADC link to the AT-DSP2200, digital I/O port, interrupt and DMA modes, and interrupt channel selection. The contents of this register are defined to be cleared upon power up and after a reset condition.
Chapter 4 Register Map and Descriptions AT-MIO-16X User Manual 13 DIOPAEN Digital I/O Port A Enable—This bit controls the 4-bit digital port A. If DIOPAEN is set, the Digital Output Register drives the DIO<4..1> digital lines at the I/O connector. If DIOPAEN is cleared, the Digital Output Register drivers are set to a high-impedance state; therefore, an external device can drive the DIO<4..1> digital lines.
Chapter 4 Register Map and Descriptions data acquisition operation completes. The interrupt request is serviced by strobing the DAQ Clear Register. When DAQCMPLINT is cleared, completion of a data acquisition sequence does not generate an interrupt. A data acquisition sequence ends by running its course or when an error condition occurs such as OVERRUN or OVERFLOW.
Chapter 4 Register Map and Descriptions 6 ADCREQ ADC Request Enable—This bit controls DMA requesting and interrupt generation from an A/D conversion. If this bit is set, an interrupt or DMA request is generated when an A/D conversion is available in the FIFO. If this bit is cleared, no DMA request or interrupt is generated following an A/D conversion. To select a specific mode, refer to Table 4-3 for available modes and associated bit patterns. Table 4-3.
Chapter 4 Register Map and Descriptions Table 4-3.
Chapter 4 Register Map and Descriptions Table 4-3.
Chapter 4 Register Map and Descriptions Table 4-3 for available modes and associated bit patterns. 3 DRVAIS Drive Analog Input Sense—This signal controls the AI SENSE signal at the I/O connector. AI SENSE is always used as an input in the NRSE input configuration mode irrespective of DRVAIS. If DRVAIS is set , then AI SENSE is connected to board ground unless the board is configured in the NRSE mode, in which case AI SENSE is used as an input.
Chapter 4 Register Map and Descriptions Command Register 4 Command Register 4 contains 16 bits that control the AT-MIO-16X board clock selection, serial DAC link over the RTSI bus, DAC mode selection, and miscellaneous configuration bits. Bits 8-15 of this register are cleared upon power up or following a reset condition. Bits 0-7 of this register are undefined upon power up and are not cleared after a reset condition. These bits should be initialized through software.
Chapter 4 Register Map and Descriptions Table 4-5. Board and RTSI Clock Selection Effect CLKMODEB0 CLKMODEB1 Bit Pattern RTSI Clock Board Clock X 0 No connection Internal, 10 MHz 0 1 Internal, 10 MHz Internal, 10 MHz 1 1 Driven onto board clock Received from RTSI clock 13 DAC1DSP DAC 1 DSP Link Enable—This bit controls the serial link from the AT-DSP2200 to DAC 1 of the analog output section. If DAC1DSP is set, then the serial link is enabled.
Chapter 4 Register Map and Descriptions update. If DACMB3 is set, the circuitry will determine whether to perform one read or two reads from the DAC FIFO depending on the data in the FIFO. See Table 4-6 for available modes and bit patterns. Table 4-6.
Chapter 4 Register Map and Descriptions Values can be directly written to the DAC, but not through the DAC FIFO. If DACGATE is cleared, updating of and writing to the DACs proceeds normally. 6 DB_DIS 5 CYCLICSTOP Cyclic Stop Enable—This bit controls when a DAC sequence terminates. If this bit is set when operating the DACs through the FIFO in a cyclic mode, the DAC circuitry will halt when the next end of buffer is encountered.
Chapter 4 Register Map and Descriptions If SRC3SEL is set, Source 3 is connected to the DAC FIFO retransmit signal. In the FIFO programmed cycle waveform modes, this bit should be set so the counter can access to the DAC FIFO retransmit signal. If SRC3SEL is cleared, Source 3 is connected to the SCANCLK signal. AT-MIO-16X User Manual 2 GATE2SEL Gate 2 Select—This bit is used to configure the signal connected to Gate 2 of the Am9513 Counter/Timer.
Chapter 4 Register Map and Descriptions Status Register 1 Status Register 1 contains 16 bits of AT-MIO-16X hardware status information, including interrupt, analog input status, analog output status, and data acquisition progress.
Chapter 4 Register Map and Descriptions data acquisition operation has completed. AT-MIO-16X User Manual 13 ADCFIFOHF* ADC FIFO Half-Full Flag—This bit reflects the state of the ADC IFO. If the appropriate conversion interrupts are enabled, see Table 4-3, and ADCFIFOHF* is clear, the current interrupt indicates at least 256 A/D conversions are available in the ADC FIFO. To clear the interrupt, read the ADC FIFO until it is empty, ADCFIFOEF* is clear.
Chapter 4 Register Map and Descriptions until cleared by strobing the DMATCB Clear Register. 9 OVERFLOW Overflow—This bit indicates whether the ADC FIFO has overflowed during a sample run. OVERFLOW is an error condition that occurs if the FIFO fills up with A/D conversion data and A/D conversions continue. If OVERFLOW is set, A/D conversion data has been lost because of FIFO overflow. If OVERFLOW is clear, no overflow has occurred.
Chapter 4 Register Map and Descriptions I/O modes, TMRREQ must be cleared by strobing the TMRREQ Clear Register. AT-MIO-16X User Manual 6 DACCOMP DAC Sequence Complete—This bit reflects the status of the DAC sequence termination circuitry. When the DAC sequence has normally completed, or ended on an error condition, the DACCOMP bit is set. If DACCOMP is set prematurely, this indicates an error condition. If interrupts are enabled, an interrupt will be generated on this condition.
Chapter 4 Register Map and Descriptions DACs, and DACCOMP is set, this is an error condition and should be handled appropriately. If DACFIFOEF* is set, then the DAC FIFO has at least one remaining point to be transferred. 2 EEPROMDATA EEPROM Data—This bit reflects the value of the data shifted out of the EEPROM using SCLK with EEPROMCS enabled. 1 EEPROMCD* EEPROM Chip Deselect—This bit reflects the status of the EEPROM chip select pin.
Chapter 4 Register Map and Descriptions Status Register 2 Status Register 2 contains 1 bit of AT-MIO-16X hardware status information for monitoring the status of the A/D conversion. Address: Base address + 1A (hex) Type: Read-only Word Size: 1-bit Bit Map: 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X ADC_BUSY* MSB LSB AT-MIO-16X User Manual Bit Name Description 15-1 X Don’t care bits.
Chapter 4 Register Map and Descriptions Analog Input Register Group The two registers making up the Analog Input Register Group control the analog input circuitry and can be used to read the ADC FIFO. Reading from the ADC FIFO Register location transfers data from the AT-MIO-16X ADC FIFO buffer to the PC. Writing to the CONFIGMEM Register location sets up channel configuration information for the analog input section.
Chapter 4 Register Map and Descriptions ADC FIFO Register Reading the ADC FIFO Register returns the oldest ADC conversion value stored in the ADC FIFO. Whenever the ADC FIFO is read, the value read is removed from the ADC FIFO, thereby leaving space for another ADC conversion value to be stored. Values are shifted into the ADC FIFO whenever an ADC conversion is complete. The ADC FIFO is emptied when all values it contains are read.
Chapter 4 Register Map and Descriptions (0x8000 to 0x7FFF) when the ADC is in bipolar mode. The A/D conversion result can be returned from the ADC FIFO as a two’s complement or straight binary value depending on the input mode set by the CHAN_BIP bit in the configuration memory location for the converted channel. If the analog input circuitry is configured for the input range 0 to +10 V, straight binary format is implemented.
Chapter 4 Register Map and Descriptions Table 4-8. Two’s Complement Mode A/D Conversion Values A/D Conversion Result Range: –10 to +10 V Input Voltage (Gain = 1) Decimal Hex –32,768 8000 –9.999695 V –32,767 8001 –5.0 V –16,384 C000 –1 FFFF 0.0 V 0 0000 305.2 µV 1 0001 5.0 V 16,384 4000 9.999695 V 32,767 7FFF –10.0 V –305.
Chapter 4 Register Map and Descriptions CONFIGMEM Register The CONFIGMEM Register controls the input channel-selection multiplexers, gain, range, and mode settings, and can contain up to 512 channel configuration settings for use in scanning sequences.
Chapter 4 Register Map and Descriptions 12 CHAN_BIP Channel Bipolar—This bit configures the ADC for unipolar or bipolar mode. When CHAN_BIP is clear, the ADC is configured for unipolar operation and values read from the ADC FIFO are in straight binary format. When CHAN_BIP is set, the ADC is configured for bipolar operation and values. The FIFO values are two’s complement and automatically sign extended. 11-10 0 Reserved—These bits must always be set to zero. 9-6 CHANSEL<3..
Chapter 4 Register Map and Descriptions Selected Analog Input Channels Single-Ended Differential (+) (–) 0111 7 7 and 15 1000 8 0 and 8 1001 9 1 and 9 1010 10 2 and 10 1011 11 3 and 11 1100 12 4 and 12 1101 13 5 and 13 1110 14 6 and 14 1111 15 7 and 15 CHANSEL<3..0> 5-3 © National Instruments Corporation CH_GAIN<2..0>Channel Gain Select–These three bits control the gain setting of the input PGIA for the selected channel.
Chapter 4 Register Map and Descriptions AT-MIO-16X User Manual CH_GAIN<2..0> Actual Gain 110 50 111 100 2 CHAN_LAST 1 CHAN_GHOST Channel Ghost—This bit is used to synchronize conversion for multiple-rate channel scanning. When this bit is set in any channel configuration value, the conversion occurs on the selected channel but the value is not saved in the ADC FIFO.
Chapter 4 Register Map and Descriptions Table 4-9. Input Configuration CHAN_SE CHAN_AIS Effect CHAN_CAL Bit Map PGIA (+) DIFF 0 0 X Channels 0 to 7 Channels 8 to 15 RSE 0 1 0 Channels 0 to 15 AI GND NRSE 0 1 1 Channels 0 to 15 AI SENSE Offset Calibration 1 X 0 AI GND AI GND Gain Calibration 1 X 1 Internal +5 Vref AI GND Input Mode PGIA (–) Note: X indicates a don’t care bit.
Chapter 4 Register Map and Descriptions Continual strobing of the CONFIGMEMLD Register with only one value in the list serves only to reload this one value. Continual strobing with more than one value in the memory sequences through the channel configuration list. In the single-channel data acquisition mode, only one value should be written and loaded into the channel configuration register.
Chapter 4 Register Map and Descriptions Analog Output Register Group The two registers making up the Analog Output Register Group access the two analog output channels. Data can be transferred to the DACs in one of three ways depending on the mode configuration in Command Register 4 according to Table 4-6. Data can be directly sent to the DACs from the local data bus, buffered from the local bus by the DAC FIFOs, or received serially from the AT-DSP2200 across the RTSI bus.
Chapter 4 Register Map and Descriptions Table 4-10. Analog Output Voltage Versus Digital Code (Unipolar Mode) Digital Code Voltage Output Decimal Hex Vref = 10 V 0 0000 0.0 V 1 0001 152.6 µV 16,384 4000 2.5 V 32,768 8000 5.0 V 49,152 C000 7.5 V 65,535 FFFF 9.
Chapter 4 Register Map and Descriptions Table 4-11. Analog Output Voltage Versus Digital Code (Bipolar Mode) (Continued) Digital Code Voltage Output Decimal Hex Reference = 10 V 16,384 4000 5.0 V 32,767 7FFF 9.999695 V Bit descriptions for the registers making up the Analog Output Register Group are given on the following pages.
Chapter 4 Register Map and Descriptions DAC0 Register Writing to the DAC0 Register loads the value written to the analog output DAC Channel 0 in immediate update mode. If posted update mode is used, the value written to the DAC0 Register is buffered and updated to the analog output DAC Channel 0 only after an access to the DAC Update Register or a timer trigger is received in one of the prescribed paths.
Chapter 4 Register Map and Descriptions DAC1 Register Writing to the DAC1 Register loads the value written to the analog output DAC Channel 1 in immediate update mode. If posted update mode is used, the value written to the DAC1 Register is buffered and updated to the analog output DAC Channel 1 only after an access to the DAC Update Register or a timer trigger is received in one of the prescribed paths.
Chapter 4 Register Map and Descriptions ADC Event Strobe Register Group The ADC Event Strobe Register Group consists of six registers that, when written to, cause the occurrence of certain events on the AT-MIO-16X board, such as clearing flags and starting A/D conversions. Bit descriptions of the six registers making up the ADC Event Strobe Register Group are given on the following pages.
Chapter 4 Register Map and Descriptions CONFIGMEMCLR Register Accessing the CONFIGMEMCLR Register clears all information in the channel configuration memory and resets the write pointer to the first location in the memory.
Chapter 4 Register Map and Descriptions CONFIGMEMLD Register Accessing the CONFIGMEMLD Register loads and sequences through the channel configuration memory.
Chapter 4 Register Map and Descriptions DAQ Clear Register Accessing the DAQ Clear Register location clears the data acquisition circuitry.
Chapter 4 Register Map and Descriptions DAQ Start Register Accessing the DAQ Start Register location initiates a multiple A/D conversion data acquisition operation. Note: Note: AT-MIO-16X User Manual Several other pieces of AT-MIO-16X circuitry must be set up before a data acquisition run can occur. See Chapter 5, Programming.
Chapter 4 Register Map and Descriptions Single Conversion Register Accessing the Single Conversion Register location initiates a single A/D conversion. Note: Address: Base address + 1D (hex) Type: Write-only Word Size: 8-bit Bit Map: Not applicable, no bits used Strobe Effect: Initiates a single ADC conversion A/D conversions can be initiated in one of two ways—by accessing the Single Conversion Register or by applying an active-low signal on the EXTCONV* signal.
Chapter 4 Register Map and Descriptions ADC Calibration Register Accessing the ADC Calibration Register location initiates an ADC calibration procedure. This register should be strobed after power up to assure the ADC is in a calibrated state.
Chapter 4 Register Map and Descriptions DAC Event Strobe Register Group The DAC Event Strobe Register Group consists of three registers that, when written to, cause the occurrence of certain events on the AT-MIO-16X board, such as clearing flags and updating the analog output DACs. Bit descriptions of the three registers making up the DAC Event Strobe Register Group are given on the following pages.
Chapter 4 Register Map and Descriptions TMRREQ Clear Register Accessing the TMRREQ Clear Register clears the TMRREQ and DACCOMP bits after a TMRTRIG* pulse is detected. Clearing TMRREQ when interrupt or DMA mode is enabled clears the respective interrupt or DMA request.
Chapter 4 Register Map and Descriptions DAC Update Register Accessing the DAC Update Register with posted update mode enabled updates both DAC0 and DAC1 simultaneously with the previously written values and removes DAC FIFO data for DAC0, DAC1, or both, as programmed. Address: Base address + 18 (hex) Type: Write-only Word Size: 16-bit Bit Map: Not applicable, no bits used.
Chapter 4 Register Map and Descriptions DAC Clear Register Accessing the DAC Clear Register clears parts of the DAC circuitry, including emptying the DAC FIFO.
Chapter 4 Register Map and Descriptions General Event Strobe Register Group The General Event Strobe Register Group consists of six registers that, when written to, cause the occurrence of certain events on the AT-MIO-16X board, such as clearing flags and starting A/D conversions. Bit descriptions of the six registers making up the General Event Strobe Register Group are given on the following pages.
Chapter 4 Register Map and Descriptions DMA Channel Clear Register Accessing the DMA Channel Clear Register clears the circuitry associated with dual-channel DMA operation. Two DMA channels are programmed for dual channel DMA. When the first DMA channel terminal count is reached, the circuitry automatically sequences the second DMA channel. When the second DMA channel terminal count is reached, the circuitry returns to the first DMA channel for servicing.
Chapter 4 Register Map and Descriptions DMATCA Clear Register Accessing the DMATCA Clear Register will clear the DMATCA signal in Status Register 1, and it will acknowledge the interrupt generated from the Channel A terminal counter interrupt. When the selected DMA Channel A reaches its terminal count, the DMATCA signal in the Status Register is asserted. If DMATC interrupts are enabled, an interrupt will also be generated.
Chapter 4 Register Map and Descriptions DMATCB Clear Register Accessing the DMATCB Clear Register clears the DMATCB signal in Status Register 1, and acknowledges the interrupt generated from the Channel B terminal counter interrupt. When the selected DMA Channel B terminal count is reached, the DMATCB signal in Status Register 1 is asserted. If DMATC interrupts are enabled, an interrupt will also be generated.
Chapter 4 Register Map and Descriptions External Strobe Register Accessing the External Strobe Register location generates an active low signal at the EXTSTROBE* output of the I/O connector. This signal has a minimum low time of 500 nsec. The EXTSTROBE* pulse is useful for several applications, including generating external general-purpose triggers and latching data into external devices, for example, from the digital output port.
Chapter 4 Register Map and Descriptions Calibration DAC 0 Load Register Accessing the Calibration DAC 0 Load Register loads the serial data previously shifted into one of the eight selected 8-bit calibration DACs.
Chapter 4 Register Map and Descriptions Calibration DAC 1 Load Register Accessing the Calibration DAC 1 Load Register loads the serial data shifted into the 12-bit ADC pregain offset calibration DACs.
Chapter 4 Register Map and Descriptions Am9513A Counter/Timer Register Group The three registers making up the Am9513A Counter/Timer Register Group access the onboard counter/timer. The Am9513A controls onboard data acquisition timing as well as general-purpose timing for the user. The Am9513A registers described here are the Am9513A Data Register, the Am9513A Command Register, and the Am9513A Status Register. The Am9513A contains 18 additional internal registers.
Chapter 4 Register Map and Descriptions Am9513A Data Register With the Am9513A Data Register, any of the 18 internal registers of the Am9513A can be written to or read from. The Am9513A Command Register must be written to in order to select the register to be accessed by the Am9513A Data Register.
Chapter 4 Register Map and Descriptions Am9513A Command Register The Am9513A Command Register controls the overall operation of the Am9513A Counter/Timer and controls selection of the internal registers accessed through the Am9513A Data Register.
Chapter 4 Register Map and Descriptions Am9513A Status Register The Am9513A Status Register contains information about the output pin status of each counter in the Am9513A. Address: Base address + 16 (hex) Type: Read-only Word Size: 16-bit Bit Map: 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X OUT5 OUT4 OUT3 OUT2 OUT1 BYTEPTR MSB LSB Bit Name Description 15-6 X Don’t care bits. 5-1 OUT<5..
Chapter 4 Register Map and Descriptions Digital I/O Register Group The two registers making up the Digital I/O Register Group monitor and control the AT-MIO-16X digital I/O lines. The Digital Input Register returns the digital state of the eight digital I/O lines. A pattern written to the Digital Output Register is driven onto the digital I/O lines when the digital output drivers are enabled (see the description for Command Register 2).
Chapter 4 Register Map and Descriptions Digital Input Register The Digital Input Register, when read, returns the logic state of the eight AT-MIO-16X digital I/O lines. Address: Base address + 1C (hex) Type: Read-only Word Size: 16-bit Bit Map: 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIO1 BDIO0 ADIO3 ADIO2 ADIO1 ADIO0 MSB LSB Bit Name Description 15-8 X Don’t care bits. 7-4 BDIO<3..
Chapter 4 Register Map and Descriptions Digital Output Register Writing to the Digital Output Register controls the eight AT-MIO-16X digital I/O lines. The Digital Output Register controls both ports A and B. When either digital port is enabled, the pattern contained in the Digital Output Register is driven onto the lines of the digital port.
Chapter 4 Register Map and Descriptions RTSI Switch Register Group The two registers making up the RTSI Switch Register Group, allow the AT-MIO-16X RTSI switch to be programmed for routing of signals on the RTSI bus trigger lines to and from several AT-MIO-16X signal lines. The RTSI switch is programmed by shifting a 56-bit routing pattern into the RTSI switch and then loading the internal RTSI Switch Control Register.
Chapter 4 Register Map and Descriptions RTSI Switch Shift Register The RTSI Switch Shift Register is written to in order to load the RTSI switch internal 56-bit Control Register with routing information for switching signals to and from the RTSI bus trigger lines. The RTSI Switch Shift Register is a 1-bit register and must be written to 56 times to shift the 56 bits into the internal register.
Chapter 4 Register Map and Descriptions RTSI Switch Strobe Register The RTSI Switch Strobe Register is written to in order to load the contents of the RTSI Switch Shift Register into the RTSI Switch Control Register, thereby updating the RTSI switch routing pattern. The RTSI Switch Strobe Register is written to after shifting the 56-bit routing pattern into the RTSI Switch Shift Register.
Chapter 5 Programming This chapter contains programming instructions for operating the circuitry on the AT-MIO-16X. Programming the AT-MIO-16X involves writing to and reading from the various registers on the board. The programming instructions list the sequence of steps to take.
Chapter 5 Programming Table 5-1. Am9513A Counter/Timer Allocations Counter DAQ Operation Waveform Operation 1 Scan division Updating/cycle counting/pulsed waveform 2 Scan division Updating/cycle counting/pulsed waveform 3 Sample interval Updating 4 Sample count N/A 5 Sample count (> 65,536) Updating/cycle counting Table 5-1 provides a general overview of the AT-MIO-16X resources to ensure there are no conflicts when using the counters/timers.
Chapter 5 4. Programming Disable all RTSI switch connections (see Programming the RTSI Switch section later in this chapter). This sequence leaves the AT-MIO-16X circuitry in the following state: • DMA and interrupts are disabled. • The DMA circuitry is cleared. • The outputs of counter/timers are in the high-impedance state. • The analog input circuitry is initialized. • The analog output is in immediate update mode. • The ADC and DAC FIFOs are cleared.
Chapter 5 Programming START Write 0xFFFF to the Am9513A Command Register Issue a master reset operation Write 0xFFEF to the Am9513A Command Register Enable 16-bit access mode Write 0xFF17 to the Am9513A Command Register Point to the master mode register Write 0xF000 to the Am9513A Data Register Load the master mode value ctr = 1 Write 0xFF00 + ctr to the Am9513A Command Register Point to the counter mode register Write 0x0004 to the Am9513A Data Register Store the counter mode value Write 0x
Chapter 5 Programming Programming the Analog Input Circuitry The analog input circuitry can be programmed for a number of different modes depending on the application. If single channels are to be monitored on an ad hoc basis, then the single conversion mode can be used. If a number of consecutive conversions on any one given channel are required, the single channel data acquisition mode should be used.
Chapter 5 Programming START Clear the A/D circuitry Select a single analog input channel, gain, mode, and range Initiate a single A/D conversion Read the A/D conversion result END Figure 5-2. Single Conversion Programming Generating a Single Conversion An A/D conversion can be initiated in one of two ways: a software-generated pulse or a hardware pulse. To initiate a single A/D conversion through software, access the Single Conversion Register.
Chapter 5 Programming Reading a Single Conversion Result A/D conversion results are available when ADCFIFOEF* is set in the Status Register and can be obtained by reading the ADC FIFO Register. To read the A/D conversion result, use the following steps: 1. Read the Status Register (16-bit read). 2. If the OVERRUN or OVERFLOW bits are set, an error occurred and data was lost. 3. If the ADCFIFOEF* bit is set, read the ADC FIFO Register to obtain the result.
Chapter 5 Programming In posttrigger sequences, the sample counter starts counting after receipt of the first trigger, while in the pretrigger acquisition mode, the sample counter does not start counting until a second trigger condition occurs. The data acquisition operation is initiated by writing to the DAQ Start Register or by a falling edge on the EXTTRIG* signal.
Chapter 5 Programming START Clear the A/D circuitry Program a single analog input channel, gain, mode, and range Program the sample-interval counter Program the sample counter Enable a single-channel data acquisition operation Apply a trigger Service the data acquisition operation END Figure 5-3.
Chapter 5 Programming Programming Data Acquisition Sequences with Channel Scanning The preceding data acquisition programming sequence programs the AT-MIO-16X for multiple A/D conversions on a single input channel. The AT-MIO-16X can also be programmed for scanning multiple-analog input channels with different gain, mode, and range settings during the data acquisition operation.
Chapter 5 Programming START Clear the A/D circuitry Program multiple analog input channels, gains, modes, and ranges Program the sample-interval counter Program the sample counter Enable a scanning data acquisition operation Apply a trigger Service the data acquisition operation END Figure 5-4. Scanning Data Acquisition Programming Setting the SCANEN bit in conjunction with the DAQEN bit in Command Register 1 enables scanning during multiple A/D conversions.
Chapter 5 Programming Interval-Channel Scanning Data Acquisition Follow the programming steps listed in Figure 5-5 to program scanned multiple A/D conversions with a scan interval (pseudo-simultaneous) for posttrigger and pretrigger modes, as well as internal and external timing. The instructions in the blocks of the following flow chart are enumerated in the Data Acquisition Programming Functions section later in this chapter.
Chapter 5 Programming START Clear the A/D circuitry Program multiple analog input channels, gains, modes, and ranges Program the sample-interval counter Program the sample counter Program the scan-interval counter Enable an interval scanning data acquisition operation Apply a trigger Service the data acquisition operation END Figure 5-5.
Chapter 5 Programming Setting the SCANEN bit in conjunction with the DAQEN bit in Command Register 1 enables scanning during multiple A/D conversions. The SCANEN bit must be set regardless of the type of scanning used (continuous or interval); otherwise, only a single channel is scanned. Setting the SCN2 bit in Command Register 1 enables the use of a scan interval during multiple A/D conversions. The scan-interval counter gives each cycle through the scan sequence a time interval.
Chapter 5 Programming Programming Single-Analog Input Channel Configurations The analog input channel, gain, mode, and range for single conversion and single channel acquisition are selected by writing a single configuration value to the CONFIGMEM Register. This register offers a window into the channel configuration memory. The CONFIGMEMLD Register must then be strobed to load this channel configuration information.
Chapter 5 Programming configuration memory, perform the following write operations where N is the number of entries in the scan sequence: • Strobe the CONFIGMEMCLR Register. • For i = 0 to N-1, use the following steps: • a. Write the desired analog channel selection and gain setting to the CONFIGMEM Register (this loads the configuration memory at location i ). b. If i = N-1, also set the LASTONE bit when writing to the CONFIGMEM Register. Strobe the CONFIGMEMLD Register.
Chapter 5 Programming found in Appendix C, AMD Am9513A Data Sheet. Use one of the following mode values: 8225 — Selects 5-MHz clock (from SOURCE2 pin) 8B25 — Selects 1-MHz clock 8C25 — Selects 100-kHz clock 8D25 — Selects 10-kHz clock 8E25 — Selects 1-kHz clock 8F25 — Selects 100-Hz clock 8525 — Selects signal at SOURCE5 input as clock (counts the rising edge of the signal, 6 MHz maximum) 3. Write FF0B to the Am9513A Command Register to select the Counter 3 Load Register. 4.
Chapter 5 Programming Sample Counts 2 through 65,536 Use the following programming sequence to program the sample counter for sample counts up to 65,536. The minimum permitted sample count is 2. All writes are 16-bit operations. All values given are hexadecimal. 1. Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register. 2. Write 1025 to the Am9513A Data Register to store the Counter 4 mode value for posttrigger acquisition modes.
Chapter 5 Programming 1. Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register. 2. Write 1025 to the Am9513A Data Register to store the Counter 4 mode value for posttrigger acquisition modes. Write 9025 to the Am9513A Data Register to store the Counter 4 mode value for pretrigger acquisition modes. 3. Write FF0C to the Am9513A Command Register to select the Counter 4 Load Register. 4.
Chapter 5 Programming acquisition operation is terminated when Counter 4 and Counter 5 reach zero. Programming the Scan-Interval Counter Counter 2 of the Am9513A Counter/Timer is used as the scan-interval counter. Counter 2 can be programmed to generate a pulse once every N counts. N is referred to as the scan interval, which is the time between successive scan sequences programmed into the mux-channel gain memory. N can be between 2 and 65,536.
Chapter 5 7. Programming Entries stored in the mux-channel gain memory should be scanned once during a scan interval. The following condition must be satisfied: scan interval ≥ sample interval * x, where x is the number of entries in the scan sequence. Write the desired scan interval to the Am9513A Data Register to store the Counter 2 load value: 8. – If the scan interval is between 2 and FFFF (65,535 decimal), write the scan interval to the Am9513A Data Register.
Chapter 5 Programming Servicing the Data Acquisition Operation Once the data acquisition operation is initiated with the application of a trigger, the operation must be serviced by reading the ADC FIFO. The ADC FIFO can be serviced in two different ways. One method is to monitor the ADCFIFOEF* to read the A/D conversion result every time one becomes available. Another method is to monitor the ADCFIFOHF* flag and read in values only when the ADC FIFO is at least half-full.
Chapter 5 Programming Resetting a Single Am9513A Counter/Timer To reset a particular counter in the Am9513A, use the following programming sequence. All writes are 16-bit operations. All values given are hexadecimal. The equation {2 ^ (ctr - 1)} means {2 “raised to” (ctr - 1)}. If ctr is equal to 4, then 2 ^ (ctr - 1) results in 2 ^ 3, or 2 * 2 * 2, or 8. This result can also be obtained by shifting 1 left three times.
Chapter 5 Programming START Write 0xFFC0 + 2 ^ (ctr -1) to the Am9513A Command Register Disarm X mode Write 0xFF00 + ctr to the Am9513A Command Register Point to the Counter X mode register Write 0x0004 to the Am9513A Data Register Write 0xFF08 + ctr to the Am9513A Command Register Write 0x0003 to the Am9513A Data Register Store the Counter X mode value Point to the Counter X load register Store a nonterminal count value Write 0xFF40 + 2 ^ (ctr -1) to the Am9513A Command Register Load Counter
Chapter 5 Programming Programming the Analog Output Circuitry The voltages at the analog output circuitry output pins (pins DAC0 OUT and DAC1 OUT on the AT-MIO-16X I/O connector) are controlled by loading the DAC in the analog output channel with a 16-bit digital code. The DAC is loaded by writing the digital code to the DAC0 and DAC1 Registers, and then the converted output is available at the I/O connector.
Chapter 5 Programming Cyclic Waveform Generation The simplest mode of waveform generation is the cyclic mode in which an internal or external timing signal is used to update the DACs. In this case, DAC updating begins when the timing signal starts, and ends when the timing signal is removed. A special case of this mode occurs when the buffer fits entirely within the DAC FIFO where it is cycled through.
Chapter 5 Programming START Clear the analog output circuitry including the DAC FIFO Internal update ? No Yes Set the A4RCV bit in Command Register 2 Clear the A4RCV bit in Command Register 2 Select the update counter via RTSI programming Program the update interval counter Program the cycle counter Set the waveform generation mode Enable updating Service update requests END Figure 5-7.
Chapter 5 Programming Programmed Cycle Waveform Generation A superset of the waveform functionality exists if DAC data buffer is less than or equal to 2,048 for one channel, or less than or equal 1,024 per DAC for two channels. In these cases, the entire buffer resides wholly within the DAC FIFO where the waveform circuitry cycles through the buffer when the end is reached. This removes a large burden on the PC bus for continually updating data in the DAC FIFO.
Chapter 5 Programming START Clear the analog output circuitry including the DAC FIFO Internal update ? No Yes Set the A4RCV bit in Command Register 2 Clear the A4RCV bit in Command Register 2 Select the update counter via RTSI programming Program the update interval counter Program the cycle counter Set the waveform generation mode Enable updating Service update requests END Figure 5-8.
Chapter 5 Programming One disadvantage of the programmed cycle waveform generation is that it uses yet another counter to perform the cycle counting. For this mode, the SRC3SEL bit in Command Register 4 must be set so that the programmed counter can count the buffer retransmit signals from the source line of Counter 3. Counter 1, 2, or 5 can be used to count buffer cycles in this mode. If Counter 5 is being used for the update signal, then only Counters 1 and 2 are available for cycle counting.
Chapter 5 Programming START Clear the analog output circuitry including the DAC FIFO Internal update ? No Yes Set the A4RCV bit in Command Register 2 Clear the A4RCV bit in Command Register 2 Select the update counter via RTSI programming Program the update interval counter Program the cycle counter Program the cycle interval counter Set the waveform generation mode Enable updating Service update requests END Figure 5-9.
Chapter 5 Programming sequence of events continues ad infinitum and does not stop until the update signal is removed or the DAC circuitry is cleared. This sequence requires that the GATE2SEL signal in addition to the SRC3SEL signal be set in Command Register 4. This allows Counter 1 to count the buffer retransmit signals from the source line of Counter 3 while Counter 2 is gated by the signal at its own gate pin.
Chapter 5 Programming sequence. All writes are 16-bit operations. All values given are hexadecimal. 1. Write FF00 + n to the Am9513A Command Register to select the Counter n Mode Register. 2. Write the mode value to the Am9513A Data Register to store the Counter n mode value. Am9513A counter mode information can be found in Appendix C, AMD Am9513A Data Sheet.
Chapter 5 Programming Programming the Waveform Cycle Counter Select the appropriate counter (1, 2, or 5) from the Am9513A Counter/Timer to be used for counting DAC buffer cycles. To program the cycle counter, complete the following programming sequence. All writes are 16-bit operations. All values given are hexadecimal. 1. Write FF00 + n to the Am9513A Command Register to select the Counter n Mode Register. 2. Write 0325 to the Am9513A Data Register to store the Counter n mode value.
Chapter 5 2. Programming Write the mode value to the Am9513A Data Register to store the Counter 2 mode value. Am9513A counter mode information can be found in Appendix C, AMD Am9513A Data Sheet. C225 — Selects 5-MHz clock (from SOURCE2 pin) CB25 — Selects 1-MHz clock CC25 — Selects 100-kHz clock CD25 — Selects 10-kHz clock CE25 — Selects 1-kHz clock CF25 — Selects 100-Hz clock C525 — Selects signal at SOURCE5 input as clock (counts the rising edge of the signal, 6 MHz maximum) 3.
Chapter 5 Programming Clear Register before exiting the interrupt routine. This clears the interrupt request. The best method of servicing update requests is with DMA since this is done in parallel with the PC CPU. If DMA is enabled, DMA requests are generated when TMRREQ is set. When the DMA controller acknowledges the request, TMRREQ is automatically cleared. An error is indicated in timer waveform generation when the DACCOMP bit in Status Register 1 is set prematurely.
Chapter 5 Programming If any digital I/O line is not driven, it floats to an indeterminate value. If more than one device is driving any digital I/O line, the voltage at that line may also be indeterminate. In these cases, the digital line has no meaningful logic value, and reading the Digital Input Register may return either 1 or 0 for the state of the digital line.
Chapter 5 Programming Table 5-2.
Chapter 5 Note: Note: Programming If both the A2DRV and A2RCV bits are set, the GATE1 signal is driven by the signal OUT2. This arrangement is probably not desirable. • To drive the RTSI switch pin A4 with the signal OUT5, set the A4DRV bit in Command Register 2. Otherwise, clear the A4DRV bit. • To drive the signal TMRTRIG* from pin A4 of the RTSI switch, set the A4RCV bit in Command Register 2. Otherwise, clear the A4RCV bit.
Chapter 5 Programming Bit Number 55 A6 51 47 A5 A4 43 A3 39 35 A2 31 A1 27 A0 23 B6 B5 19 B4 15 11 B3 7 B2 MSB 3 B1 0 B0 LSB A0 Control Bit Number S2 S1 S0 OUTEN 31 30 29 28 Figure 5-10. RTSI Switch Control Pattern In Figure 5-10, the fields labeled A6 through A0 and B6 through B0 are the 4-bit control fields for each RTSI switch pin of the same name. The 4-bit control field for pin A0 is shown in Figure 5-10.
Chapter 5 Programming To program the RTSI switch, complete these steps: 1. 2. 3. Calculate the 56-bit pattern based on the desired signal routing. a. Clear the OUTEN bit for all input pins and for all unused pins. b. Select the signal source pin for all output pins by setting bits S2 through S0 to the source pin number. c. Set the OUTEN bit for all output pins. For i = 0 to 55, follow these steps: a. Copy bit i of the 56-bit pattern to bit 0 of an 8-bit temporary variable. b.
Chapter 5 Programming 3. Program the DMA controller to service DMA requests from the AT-MIO-16X board. Refer to the IBM Personal Computer AT Technical Reference manual for more information on DMA controller programming. 4. If a DMA terminal count is received after the DMA service, write 0 to either the appropriate DMATC Clear Register to clear the DMATCA or DMATCB bits in Status Register 1. Once steps 1 through 3 are completed, the DMA controller is programmed to acknowledge requests.
Chapter 5 Programming Interrupt Programming Seven different interrupts are generated by the AT-MIO-16X board: • Whenever a conversion is available to be read from the ADC FIFO • Whenever the ADC FIFO is more than half-full • Whenever a data acquisition sequence completes • Whenever a DMA terminal count is received • Whenever a falling edge on the TMRTRIG* pin of the Am9513A is detected • Whenever the DAC FIFO is less than full • Whenever the DAC FIFO is half-full These interrupts can be enab
Chapter Calibration Procedures 6 This chapter discusses the calibration resources and procedures for the AT-MIO-16X analog input and analog output circuitry. The calibration process involves reading offset and gain errors from the analog input and analog output sections and writing values to the appropriate calibration DACs to null out the errors.
Chapter 6 Calibration Procedures 120 Factory Information 118 Factory Reference 107 Factory Bipolar Area 96 Factory Unipolar Area 85 Load Area 74 User Area 7 63 User Area 6 52 User Area 5 41 User Area 4 30 User Area 3 19 User Area 2 08 User Area 1 00 Area Information ADC Pregain Offset MSB ADC Pregain Offset LSB DAC Channel 1 Offset DAC Channel 0 Offset DAC Channel 1 Gain DAC Channel 0 Gain ADC Postgain Offset Fine ADC Postgain Offset Coarse ADC Gain Fine ADC Gain Coarse User Refe
Chapter 6 Calibration Procedures Table 6-1.
Chapter 6 Calibration Procedures Table 6-1.
Chapter 6 1111 = P 1110 = O . . . . . . 0010 = C 0001 = B 0000 = A Revision Calibration Procedures 1111 = 15 1110 = 14 . . . . . . 0010 = 2 0001 = 1 0000 = 0 Subrevision 7 6 5 4 3 2 1 MSB 0 LSB Figure 6-2. Revision and Subrevision Field If the Revision and Subrevision Field contain the binary value 00100010, this signifies that the accessed AT-MIO-16X board is at Revision C and Subrevision 2.
Chapter 6 Calibration Procedures 0110 = 16,384 0101 = 8,192 0100 = 4,096 0011 = 2,048 0010 = 1,024 0001 = 512 0000 = 256 ADC FIFO Length DAC FIFO Length 7 6 5 4 3 2 1 0110 = 16,384 0101 = 8,192 0100 = 4,096 0011 = 2,048 0010 = 1,024 0001 = 512 0000 = 256 0 MSB LSB Figure 6-4.
Chapter 6 Calibration Procedures be XXXXX000. If the analog input section is calibrated using the utility library functions and the constants are saved to User Area 7, then the ADC Range bit in the area information field for User Area 7 is set or cleared according to the mode in which the analog input section was calibratedolar. The same holds true for the analog output section. Calibration Equipment Requirements Normal self-calibration requires no external calibration equipment.
Chapter 6 Calibration Procedures It is important to realize that inaccuracy of the internal voltage reference results only in gain error. Offset error is unaffected. If an application can tolerate slight gain inaccuracy, there should not be a need to redetermine the value of the onboard reference. Calibration DACs There are eight 8-bit DACs (CALDAC<0..7>) and one 12-bit DAC (CALDAC8) on the AT-MIO-16X that are used for calibration. These DACs are described in Table 6-2. Table 6-2.
Chapter 6 Calibration Procedures a two's complement binary number in the onboard EEPROM for subsequent use by the analog input calibration routines. Because the onboard reference is very stable with respect to time and temperature, it is seldom necessary to use the reference calibration routine. Every year should be sufficient, or whenever operating the board at an ambient temperature that is more than 10° C from the temperature at which the reference value was last determined.
Chapter 6 Calibration Procedures CALDAC1 until the measured voltage is equal to the value of the reference as stored in the onboard EEPROM. Once the board is calibrated at a gain of 1, there is only a small residual gain error (±0.02% maximum) at the other gains. The gain error is always calibrated immediately after the offsets are calibrated.
Chapter 6 Calibration Procedures output to 5 V and adjusts CALDAC4 and CALDAC5 until it measures 5 V between each analog output and AO GND. The gain error is always calibrated immediately after the offset is calibrated. Notice that CALDAC4 and CALDAC5 adjust the gain by varying the values of the internal DAC references. Hence, the gain of an analog output channel cannot be adjusted under software control if the channel is using an external reference (but the offset can still be adjusted).
Appendix A Specifications This appendix lists the specifications of the AT-MIO-16X. These are typical at 25° C unless otherwise stated. The operating temperature range is 0° to 70° C. A warmup time of at least 15 minutes is required. Analog Input Number of input channels ...................16 single-ended, 8 differential Analog resolution ...............................16-bit, 1 in 65,536 Maximum sampling rate .....................100 ksamples/sec Relative accuracy ................................±1.
Appendix A Specifications Input impedance ................................. 100 GΩ in parallel with 100 pF Gains .................................................. 1, 2, 5, 10, 20, 50, and 100, software-selectable Pregain offset error After calibration .......................... ±3 µV maximum Before calibration ........................ ±2.2 mV maximum Temperature coefficient............... ±5 µV/° C Postgain offset error After calibration .......................... ±381 µV maximum Before calibration .....
Appendix A Specifications Long-term stability.......................15 ppm 1, 000 h (75 µV/ 1, 000 h ) Explanation of Analog Input Specifications Linear Errors Pregain offset error is the amount of possible voltage offset error in the circuitry before the gain stage. Its contribution to total offset error is multiplied by the gain. Postgain offset error is the amount of possible voltage offset error in the circuitry following the gain stage.
Appendix A Specifications Table A-2. Equivalent Gain Errors in 16-Bit Systems Error at Full-Scale Gain Error Range LSB % of FSR % of Gain PPM of Gain 0 to 10 V 1 0.001526% 0.001526% 15.26 ppm –10 to 10 V 1 0.001526% 0.003052% 30.52 ppm Nonlinear Errors Relative accuracy is a measure of the (non)linearity of an analog system. It indicates the maximum deviation of the averaged analog-input-to-digital-output transfer curve from an endpoint-fit straight line.
Appendix A Specifications Multiple-Channel Scanning Acquisition Rates When scanning among channels with different voltages, the analog circuitry on the AT-MIO-16X needs time to settle from one voltage to the next. Because of its complex transient response, the AT-MIO-16X is not always able to settle to full 16-bit accuracy within 10 µsec, which is the shortest guaranteed sampling interval. Table A-3 lists the typical voltage settling times to within three different percentages of full-scale range.
Appendix A Specifications the same gain and all the signals are within 10% of the full-scale range of each other (for example, within 2 V of each other with a ±10-V range), the circuitry settles to full 16-bit accuracy (±0.5 LSB) in 10 µsec and the channels can be scanned at the full rate of 100 ksamples/sec. Analog Output Number of output channels ................ 2 Type of DAC...................................... 16-bit, multiplying Data transfers .....................................
Appendix A Specifications Output voltage ranges .........................0 to 10 V, unipolar mode; ±10 V, bipolar mode, (software-selectable) Current drive capability ......................±5 mA (short-circuit protected) 2 kΩ minimum load, 1,000 pF maximum capacitive load Output settling time to ±0.003% FSR......................................10 µsec for a 20 V step Output slew rate ..................................5 V/µsec Output noise .......................................
Appendix A Specifications Differential nonlinearity in a DAC is a measure of deviation of code width from 1 LSB. For a DAC, code width is the difference between the analog values produced by consecutive digital codes. A specification of ±0.5 LSB differential nonlinearity ensure that the code width is always greater than 0.5 LSB (guaranteeing monotonicity) and less than 1.5 LSB. Digital I/O Compatibility ..................................... TTL-compatible Output current source capability.........
Appendix A Specifications Power Requirement (from PC I/O Channel) Power consumption.............................2.0 A typical at +5 VDC Power available at I/O connector ........4.75 V to 5.25 V at 1 A Physical Board dimensions ...............................13.3 by 4.5 in. I/O connector ......................................50-pin male ribbon-cable connector or 68-pin male shielded cable connector Environment Operating component temperature ......0° to +70° C StorageTemperature .........................
Appendix B I/O Connector This appendix describes the pinout and signal names for the AT-MIO-16X 50-pin I/O connector and the 68-pin I/O connector. Figure B-1 shows the AT-MIO-16X 50-pin I/O connector.
Appendix B I/O Connector AI GND 1 2 AI GND ACH0 3 4 ACH8 ACH1 5 6 ACH9 ACH2 7 8 ACH3 9 10 ACH10 ACH11 ACH4 11 12 ACH12 ACH5 13 14 ACH13 ACH6 ACH7 AI SENSE 15 16 ACH14 17 18 ACH15 19 20 DAC0 OUT DAC1 OUT AO GND 21 22 23 24 EXTREF DIG GND ADIO0 25 26 BDIO0 ADIO1 27 28 ADIO2 29 30 BDIO1 BDIO2 ADIO3 31 32 DIG GND 33 34 BDIO3 +5 V +5 V EXTSTROBE* 35 36 SCANCLK 37 38 EXTTRIG* EXTGATE* 39 40 SOURCE1 OUT1 41 42 EXTCONV* GATE1 43 44 EXTTMRTRIG* GATE2 SOURC
Appendix B I/O Connector Figure B-2 shows the pin assignments for the AT-MIO-16X 68-pin I/O connector.
Appendix B I/O Connector Table B-1. Signal Connection Descriptions 68-Pin Pins 50-Pin Pins 24, 27, 29, 32, 56, 59, 64, 67 1-2 AI GND Analog Input Ground—These pins are the reference point for single-ended measurements and the bias current return point for differential measurements. 68, 33, 65, 30, 28, 60, 25, 57, 34, 66, 31, 63, 61, 26, 58, 23 3-18 ACH<0..15> Analog Input Channels 0 through 15—In differential mode, the input is configured for up to eight channels.
Appendix B I/O Connector Table B-1. Signal Connection Descriptions (Continued) 68-Pin Pins 50-Pin Pins 8, 14 34, 35 +5 V +5 VDC Source—These pins are fused for up to 1 A of +5 V supply. 46 36 SCANCLK Scan Clock—This pin pulses once for each A/D conversion in the scanning modes. The low-to-high edge indicates when the input signal can be removed from the input or switched to another signal.
Appendix B I/O Connector Table B-1. Signal Connection Descriptions (Continued) 68-Pin Pins 50-Pin Pins 40 43 OUT1 OUTPUT1—This pin is from the Am9513A Counter 1 signal. 6 44 EXTTMRTRIG* External Timer Trigger—If selected, a high-to-low edge on EXTTMRTRIG* results in the output DACs being updated with the value written to them in the posted update mode. EXTTMRTRIG* will also generate a timed interrupt if enabled. 5 45 GATE2 GATE2—This pin is from the Am9513A Counter 2 signal.
Appendix AMD Am9513A Data Sheet1 C This appendix contains the manufacturer data sheet for the AMD Am9513A System Timing Controller integrated circuit (Advanced Micro Devices, Inc.) data sheet. This controller is used on the AT-MIO-16X. 1. Copyright © Advanced Micro Devices, Inc. 1989. Reprinted with permission of copyright owner. All rights reserved. Advanced Micro Devices, Inc. 1990 Data Book Personal Computer Products: Processors, Coprocessors, Video, and Mass Storage.
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-2 © National Instruments Corporation
Appendix C © National Instruments Corporation C-3 AMD Am9513A Data Sheet AT-MIO-16X User Manual
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-4 © National Instruments Corporation
Appendix C © National Instruments Corporation C-5 AMD Am9513A Data Sheet AT-MIO-16X User Manual
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-6 © National Instruments Corporation
Appendix C © National Instruments Corporation C-7 AMD Am9513A Data Sheet AT-MIO-16X User Manual
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-8 © National Instruments Corporation
Appendix C © National Instruments Corporation C-9 AMD Am9513A Data Sheet AT-MIO-16X User Manual
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-10 © National Instruments Corporation
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Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-12 © National Instruments Corporation
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Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-14 © National Instruments Corporation
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Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-16 © National Instruments Corporation
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Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-18 © National Instruments Corporation
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Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-20 © National Instruments Corporation
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Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-22 © National Instruments Corporation
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Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-24 © National Instruments Corporation
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Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-26 © National Instruments Corporation
Appendix C © National Instruments Corporation C-27 AMD Am9513A Data Sheet AT-MIO-16X User Manual
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-28 © National Instruments Corporation
Appendix C © National Instruments Corporation C-29 AMD Am9513A Data Sheet AT-MIO-16X User Manual
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-30 © National Instruments Corporation
Appendix C © National Instruments Corporation C-31 AMD Am9513A Data Sheet AT-MIO-16X User Manual
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-32 © National Instruments Corporation
Appendix C © National Instruments Corporation C-33 AMD Am9513A Data Sheet AT-MIO-16X User Manual
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-34 © National Instruments Corporation
Appendix C © National Instruments Corporation C-35 AMD Am9513A Data Sheet AT-MIO-16X User Manual
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-36 © National Instruments Corporation
Appendix C © National Instruments Corporation C-37 AMD Am9513A Data Sheet AT-MIO-16X User Manual
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Appendix C © National Instruments Corporation C-39 AMD Am9513A Data Sheet AT-MIO-16X User Manual
Appendix C AMD Am9513A Data Sheet AT-MIO-16X User Manual C-40 © National Instruments Corporation
Appendix Customer Communication D For your convenience, this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation. When you contact us, we need the information on the Technical Support Form and the configuration form, if your manual contains one, about your system configuration to answer your questions as quickly as possible.
Fax-on-Demand Support Fax-on-Demand is a 24-hour information retrieval system containing a library of documents on a wide range of technical information. You can access Fax-on-Demand from a touch-tone telephone at (512) 418-1111. E-Mail Support (currently U.S. only) You can submit technical support questions to the applications engineering team through e-mail at the Internet address listed below. Remember to include your name, address, and phone number so we can contact you with solutions and suggestions.
Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
AT-MIO-16X Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: AT-MIO-16X User Manual Edition Date: October 1997 Part Number: 320640B-01 Please comment on the completeness, clarity, and organization of the manual.
Glossary Prefix Meanings Value p- pico- 10-12 n- nano- 10-9 µ- micro- 10-6 m- milli- 10-3 k- kilo- 103 M- mega- 106 G- giga- 109 Numbers/Symbols % percent + positive of, or plus – negative of, or minus / per ° degree Ω ohm A A amperes AC alternating current © National Instruments Corporation G-1 AT-MIO-16X User Manual
Glossary AC coupled allowing the transmission of AC signals while blocking DC signals A/D analog-to-digital ADC analog-to-digital converter—an electronic device, often an integrated circuit, that converts an analog voltage to a digital number ADC resolution the resolution of the ADC, which is measured in bits. An ADC with 16 bits has a higher resolution, and thus a higher degree of accuracy, than a 12-bit ADC.
Glossary B b bit—one binary digit, either 0 or 1 B byte—eight related bits of data, an eight-bit binary number. Also used to denote the amount of memory required to store one byte of data. bandwidth the range of frequencies present in a signal, or the range of frequencies to which a measuring device can respond base address a memory address that serves as the starting address for programmable registers. All other addresses are located by adding to the base address.
Glossary bus master a type of a plug-in board or controller with the ability to read and write devices on the computer bus C C Celsius cache high-speed processor memory that buffers commonly used instructions or data to increase processing throughput CalDAC calibration DAC capacitively coupled cascading process of extending the counting range of a counter chip by connecting to the next higher counter channel pin or wire lead to which you apply or from which you read the analog or digital signal.
Glossary common-mode range the input range over which a circuit can handle a common-mode signal common-mode signal the mathematical average voltage, relative to the computer’s ground, of the signals from a differential input common-mode voltage any voltage present at the instrumentation amplifier inputs with respect to amplifier ground compensation range the range of a parameter for which compensating adjustment can be made conditional retrieval a method of triggering in which you simulate an anal
Glossary D D/A digital-to-analog.
Glossary derivative control a control action with an output that is proportional to the rate of change of the error signal. Derivative control anticipates the magnitude difference between the process variable and the setpoint. device a plug-in data acquisition board, card, or pad that can contain multiple channels and conversion devices. Plug-in boards, PCMCIA cards, and devices such as the DAQPad-1200, which connects to your computer parallel port, are all examples of DAQ devices.
Glossary drivers software that controls a specific hardware device such as a DAQ board or a GPIB interface board DSP digital signal processing dual-access memory memory that can be sequentially accessed by more than one controller or processor but not simultaneously accessed. Also known as shared memory.
Glossary external trigger a voltage pulse from an external source that triggers an event such as A/D conversion F F farads false triggering triggering that occurs at an unintended time fetch-and-deposit a data transfer in which the data bytes are transferred from the source to the controller, and then from the controller to the target Fieldbus an all-digital communication network used to connect process instrumentation and control systems; it will ultimately replace existing 4–20 mA analog standar
Glossary Some common example of floating signal sources are batteries, transformers, or thermocouples.
Glossary handle pointer to a pointer to a block of memory; handles reference arrays and strings. An array of strings is a handle to a block of memory containing handles to strings. handler a device driver that is installed as part of the operating system of the computer handshaked digital I/O a type of digital acquisition/generation where a device or module accepts or transfers data after a digital pulse has been received. Also called latched digital I/O.
Glossary sine wave added in a 4:1 amplitude ratio. DIN—A 250 Hz sine wave and an 8 kHz sine wave added in a 4:1 amplitude ratio. CCIF—A 14 kHz sine wave and a 15 kHz sine wave added in a 1:1 amplitude ratio. immediate digital I/O a type of digital acquisition/generation where LabVIEW updates the digital lines or port states immediately or returns the digital value of an input line. Also called nonlatched digital I/O. in.
Glossary interrupt level the relative priority at which a device can interrupt interval scanning scanning method where there is a longer interval between scans than there is between individual channels comprising a scan I/O input/output—the transfer of data to/from a computer system involving communications channels, operator interface devices, and/or data acquisition and control interfaces IOH current, output high IOL current, output low IRQ interrupt request ISA industry standard architectur
Glossary L LabVIEW laboratory virtual instrument engineering workbench latch latched digital I/O a type of digital acquisition/generation where a device or module accepts or transfers data after a digital pulse has been received. Also called handshaked digital I/O. LED light-emitting diode library a file containing compiled object modules, each comprised of one of more functions, that can be linked to other object modules that make use of these functions. NIDAQMSC.
Glossary MB megabytes of memory MBLT eight-byte block transfers in which both the Address bus and the Data bus are used to transfer data Mbytes/s a unit for data transfer that means 1 million or 106 bytes/s memory buffer See buffer.
Glossary NIST National Institute of Standards and Technology nodes execution elements of a block diagram consisting of functions, structures, and subVIs noise an undesirable electrical signal—Noise comes from external sources such as the AC power line, motors, generators, transformers, fluorescent lights, soldering irons, CRT displays, computers, electrical storms, welders, radio transmitters, and internal sources such as semiconductors, resistors, and capacitors.
Glossary operating system base-level software that controls a computer, runs programs, interacts with users, and communicates with installed hardware or peripheral devices optical coupler, optocoupler a device designed to transfer electrical signals by utilizing light waves to provide coupling with electrical isolation between input and output. Sometimes called optoisolator or photocoupler.
Glossary PCMCIA an expansion bus architecture that has found widespread acceptance as a de facto standard in notebook-size computers. It originated as a specification for add-on memory cards written by the Personal Computer Memory Card International Association.
Glossary ppm parts per million pretriggering the technique used on a DAQ board to keep a continuous buffer filled with data, so that when the trigger conditions are met, the sample includes the data leading up to the trigger condition propagation the transmission of a signal through a computer system propagation delay the amount of time required for a signal to pass through a circuit proportional control a control action with an output that is to be proportional to the deviation of the controlled
Glossary R RAM random-access memory real time a property of an event or system in which data is processed as it is acquired instead of being accumulated and processed at a later time referenced signal sources signal sources with voltage signals that are referenced to a system ground, such as the earth or a building ground. Also called grounded signal sources. relative accuracy a measure in LSB of the accuracy of an ADC. It includes all nonlinearity and quantization errors.
Glossary RTSI Real-Time System Integration RTSI bus real-time system integration bus—the National Instruments timing bus that connects DAQ boards directly, by means of connectors on top of the boards, for precise synchronization of functions S s seconds S samples sample counter the clock that counts the output of the channel clock, in other words, the number of samples taken. On boards with simultaneous sampling, this counter counts the output of the scan clock and hence the number of scans.
Glossary SE single-ended—a term used to describe an analog input that is measured with respect to a common ground self-calibrating a property of a DAQ board that has an extremely stable onboard reference and calibrates its own A/D and D/A circuits without manual adjustments by the user sensor a device that responds to a physical stimulus (heat, light, sound, pressure, motion, flow, and so on), and produces a corresponding electrical signal settling time the amount of time required for a voltage to r
Glossary S/s samples per second—used to express the rate at which a DAQ board samples an analog signal STC system timing controller strain gauge a thin conductor, which is attached to a material, that detects stress or vibrations in that material. The conductor’s resistance is a function of the applied force.
Glossary thermistor a semiconductor sensor that exhibits a repeatable change in electrical resistance as a function of temperature. Most thermistors exhibit a negative temperature coefficient. thermocouple a temperature sensor created by joining two dissimilar metals. The junction produces a small voltage as a function of the temperature. throughput rate the data, measured in bytes/s, for a given continuous operation, calculated to include software overhead.
Glossary update rate the number of output updates per second V V volts VDC volts direct current VDMAD virtual DMA driver VI virtual instrument—(1) a combination of hardware and/or software elements, typically used with a PC, that has the functionality of a classic stand-alone instrument (2) a LabVIEW software module (VI), which consists of a front panel user interface and a block diagram program VIH volts, input high VIL volts, input low Vin volts in VISA a new driver software architecture
Glossary word the standard number of bits that a processor or memory manipulates at one time. Microprocessors typically use 8, 16, or 32-bit words. working voltage the highest voltage that should be applied to a product in normal use, normally well under the breakdown voltage for safety margin. See also Breakdown Voltage.
Index Numbers ADC_BUSY* bit, 4-30 ADC Calibration Register, 4-52 ADC conversion timing, 3-8 ADC Event Strobe Register Group, 4-46 to 4-52 ADC Calibration Register, 4-52 CONFIGMEMCLR Register description, 4-47 programming multiple-analog input channel configurations, 5-16 programming single-analog input channel configurations, 5-15 CONFIGMEMLD Register description, 4-48 programming multiple-analog input channel configurations, 5-16 programming single-analog input channel configurations, 5-15 DAQ Clear Regi
Index resource allocation considerations, 5-1 to 5-2 sample counters, 5-17 to 5-20 sample-interval counter, 5-16 to 5-17 scan interval counter, 5-20 to 5-21 update-interval counter, 5-32 to 5-33 waveform cycle counter, 5-34 waveform cycle interval counter, 5-34 to 5-36 register map, 4-2 resetting after data acquisition operation, 5-23 to 5-24 Am9513A System Timing Controller data sheet, C-1 to C-40 initializing, 5-3 to 5-4 programming, 5-37 timing I/O circuitry, 3-25 to 3-29 analog data acquisition rates m
Index gain error, A-3 postgain offset error, A-3 pregain offset error, A-3 list of specifications, A-1 to A-2 noise, A-4 nonlinear errors, A-4 differential nonlinearity, A-4 relative accuracy, A-4 system noise, A-4 analog output overview, 1-2 signal connections, 2-29 to 2-30 analog output circuitry, 3-15 to 3-18 block diagram, 3-16 calibration, 3-17 to 3-18, 6-10 to 6-11 clearing, 5-32 configuration, 3-17 description, 3-16 to 3-17 programming, 5-25 analog output configuration, 2-11 to 2-12.
Index digital I/O connections, 2-31 to 2-32 BDIO<3..
Index INTCHB<2..0>, 4-19 INTGATE, 4-6 I/O_INT, 4-15 OUT<5..1>, 4-67 OUTEN, 5-40 OVERFLOW, 4-27, 5-7, 5-22 OVERRUN, 4-27, 5-7, 5-22 RETRIG_DIS, 4-6 RSI, 4-72 RTSITRIG, 4-8 S2 through S0 bits, 5-40 SCANDIV, 4-6, 5-15 SCANEN, 4-7, 5-11, 5-14 SCLK, 4-5 to 4-6 SCN2, 4-7, 5-14 SDATA, 4-5 SRC3SEL, 4-23 to 4-24, 5-30, 5-32 TMRREQ, 4-27 to 4-28, 5-32, 5-35, 5-43 board and RTSI clock selection. See Command Register 4; RTSI bus clock. board configuration. See configuration.
Index ComponentWorks software, 1-4 concatenating counters, 2-39 CONFIGCLK signal, 3-29 CONFIGMEM Register description, 4-35 to 4-40 programming multiple-analog input channel configurations, 5-16 single-analog input channel configurations, 5-15 CONFIGMEMCLR Register description, 4-47 programming multiple-analog input channel configurations, 5-16 single-analog input channel configurations, 5-15 CONFIGMEMLD Register description, 4-48 programming multiple-analog input channel configurations, 5-16 single-analog
Index counter/timer. See Am9513A Counter/Timer Register Group; Am9513A System Timing Controller. customer communication, xvii, D-1 to D-2 cyclic waveform generation. See DAC waveform circuitry and timing; waveform generation programming.
Index analog output connections, 2-29 description (table), 2-17, B-4 programming analog output circuitry, 5-25 DAC0REQ bit, 4-18 to 4-19 DAC1 Register description, 4-45 programming analog output circuitry, 5-25 DAC1DSP bit, 4-21 DAC1OUT signal analog output connections, 2-29 description (table), 2-17, B-4 programming analog output circuitry, 5-25 DAC1REQ bit, 4-18 DACCMPLINT bit, 4-14 DACCOMP bit clearing analog output circuitry, 5-32 description, 4-28 servicing update requests, 5-36 DACFIFOEF* bit descrip
Index flow chart, 5-6 generating single conversions, 5-6 reading single conversion result, 5-7 using SCONVERT or EXTCONV* signal, 5-5 to 5-6 single-analog input channel configurations, 5-15 single-channel data acquisition sequence, 5-7 to 5-9 waveform cycle counter, 5-34 waveform cycle interval counter, 5-34 to 5-36 waveform generation functions, 5-32 data acquisition rates multiple-channel scanning rates, A-5 to A-6 single-channel rates, A-4 data acquisition timing circuitry block diagram, 3-5 definition,
Index DIOPAEN bit description, 4-14 programming digital I/O circuitry, 5-36 DIOPBEN bit description, 4-13 programming digital I/O circuitry, 5-36 DMA Channel Clear Register, 4-58 DMA channels configuring, 2-7 PC I/O channel interface, 3-4 DMA operations, programming, 5-41 to 5-42 dual-channel interleaved mode, 5-42 procedure, 5-41 to 5-42 servicing update requests, 5-35 to 5-36 single-channel interleaved mode, 5-42 DMA request generation controlling with bits in Command Register 3, 4-13 to 4-19 DMA and int
Index description (table), 2-18, B-5 generating single conversions, 5-5 to 5-6 programming sample counter(s), 5-17 programming sample-interval counter, 5-16 RTSI switch, 3-30 single-channel data acquisition, 3-9 to 3-10 timing connections, 2-34 updating DACs, 5-32 External Strobe Register, 4-61 EXTGATE* signal description (table), 2-18, B-5 timing connections, 2-36 EXTREF signal analog output connections, 2-29 to 2-30 analog output reference selection, 2-11 description (table), 2-17, B-4 EXTREFDAC0 bit, 4-
Index F description, 4-24 pulsed cyclic waveform generation, 5-30 GATE5 signal (table), 2-18, B-6 General Event Strobe Register Group, 4-57 to 4-63 Calibration DAC 0 Load Register, 4-62 Calibration DAC 1 Load Register, 4-63 DMA Channel Clear Register, 4-58 DMATCA Clear Register clearing analog output circuitry, 5-32 description, 4-59 interrupt programming, 5-43 programming DMA operations, 5-41 DMATCB Clear Register clearing analog output circuitry, 5-32 description, 4-60 interrupt programming, 5-43 progra
Index I PC I/O channel interface, 3-4 programming, 5-43 interval channel scanning definition, 5-10 programming, 5-12 to 5-14 interval scanning data acquisition timing, 3-14 INTGATE bit, 4-6 I/O connectors cabling considerations 50-pin I/O connector, 2-43 to 2-44 68-pin I/O connector, 2-44 exceeding maximum ratings (warning), 2-14 pin assignments 50-pin connector (figure), 2-15, B-2 68-pin connector (figure), 2-16, B-3 signal descriptions (table), 2-17 to 2-19 I/O_INT bit, 4-15 immediate update mode, 3-18
Index description (table), 2-18, B-6 RTSI switch signal connections (table), 5-38 selecting internal update counter, 5-32 OUT3 signal, 5-32 OUT5 signal description (table), 2-19, B-6 RTSI switch signal connections (table), 5-38 selecting internal update counter, 5-32 OUTEN bit, 5-40 output polarity selection, 2-12 OVERFLOW bit ADC FIFO overflow condition, 5-7 description, 4-27 servicing data acquisition operation, 5-22 OVERRUN bit ADC overrun condition, 5-7 description, 4-27 servicing data acquisition oper
Index servicing data acquisition operations, 5-22 single-analog input channel configurations, 5-15 waveform cycle counter, 5-34 waveform cycle interval counter, 5-34 to 5-36 waveform generation functions, 5-32 data acquisition sequences with channel scanning, 5-10 to 5-11 continuous channel scanning, 5-10 to 5-11 interval-channel scanning, 5-12 to 5-14 digital I/O circuitry, 5-36 to 5-37 initialization Am9513A, 5-3 to 5-4 AT-MIO-16X, 5-2 to 5-3 register programming considerations, 5-1 resource allocation c
Index R Analog Output Register Group, 4-41 to 4-43 analog output voltage versus digital code bipolar mode (table), 4-42 to 4-43 unipolar mode (table), 4-42 formula for voltage output versus digital code, 4-42 Calibration DAC 0 Load Register, 4-62 Calibration DAC 1 Load Register, 4-63 Command Register 1, 4-5 to 4-8 Command Register 2 description, 4-9 to 4-12 interrupt programming, 5-43 programming digital I/O circuitry, 5-36 Command Register 3, 4-13 to 4-19 Command Register 4, 4-20 to 4-24 CONFIGMEM Regist
Index description, 4-60 interrupt programming, 5-43 programming DMA operations, 5-41 External Strobe Register, 4-61 General Event Strobe Register Group, 4-57 to 4-63 programming considerations, 5-1 register map, 4-1 to 4-2 register sizes, 4-3 RTSI Switch Register Group, 4-71 to 4-73 RTSI Switch Shift Register, 4-72 RTSI Switch Strobe Register, 4-73 Single Conversion Register, 4-51 Status Register 1 description, 4-25 to 4-29 servicing update requests, 5-36 Status Register 2, 4-30 TMRREQ Clear Register clear
Index SCANDIV bit description, 4-6 programming multiple-analog input channel configurations, 5-15 SCANEN bit continuous channel scanning data acquisition, 5-11 description, 4-7 interval-channel scanning data acquisition, 5-14 SCLK bit, 4-5 to 4-6 SCN2 bit description, 4-7 interval-channel scanning data acquisition, 5-14 SDATA bit, 4-5 signal connections analog input, 2-19 to 2-20 analog input configurations common-mode signal rejection, 2-29 differential connections DIFF input configuration, 2-22 floating
Index posttrigger data acquisition timing, 3-10 to 3-11 pretrigger data acquisition timing, 3-11 to 3-12 programming sequence, 5-7 to 5-9 sample-interval timer, 3-9 specifications, A-4 single-ended connections description, 2-26 to 2-37 floating signal sources (RSE), 2-27 grounded signal sources (NRSE), 2-28 when to use, 2-26 single-read timing, 3-8 to 3-9 software programming choices ComponentWorks, 1-4 LabVIEW and LabWindows/CVI, 1-4 NI-DAQ driver software, 1-5 to 1-6 register-level programming, 1-6 Virtu
Index waveform timing circuitry, 3-20 to 3-22 data acquisition timing circuitry, 3-8 to 3-12 block diagram, 3-5 data acquisition rates, 3-15 multiple-channel data acquisition, 3-12 to 3-15 single-channel data acquisition, 3-9 to 3-12 single-read timing, 3-8 to 3-9 digital I/O circuitry, 3-24 to 3-25 functional overview, 3-1 to 3-2 PC I/O channel interface circuitry, 3-2 to 3-5 RTSI bus interface circuitry, 3-29 to 3-30 timing I/O circuitry, 3-25 to 3-29 time-lapse measurements, 2-38 timing circuitry.
Index W TMRREQ Clear Register clearing analog output circuitry, 5-32 description, 4-54 DMA operations, 5-41 interrupt programming, 5-43 programming DMA operations, 5-41 servicing update requests, 5-35 to 5-36 TMRREQ signal DAC waveform timing circuitry, 3-20 interrupt programming, 5-43 servicing update requests, 5-35 to 5-36 TMRTRIG* signal controlled by A4RCV bit, 4-9 programming analog output circuitry, 5-25 RTSI switch, 3-30 servicing update requests, 5-35 trigger, applying, 5-21 two's complement mode
