Network Card User Manual

Index
AT E Series User Manual I-6 ni.com
G
general-purpose timing signal connections
FREQ_OUT signal, 4-50
GPCTR0_GATE signal, 4-45
GPCTR0_OUT signal, 4-46
GPCTR0_SOURCE signal, 4-44
GPCTR0_UP_DOWN signal, 4-46
GPCTR1_GATE signal, 4-47
GPCTR1_OUT signal, 4-48
GPCTR1_SOURCE signal, 4-47
GPCTR1_UP_DOWN signal, 4-48
GPCTR0_GATE signal, 4-45
GPCTR0_OUT signal
AT-MIO-16E-1, AT-MIO-16E-2 and
AT-MIO-64E-3 (table), 4-9
AT-MIO-16E-10 and AT-MIO-16DE-10
(table), 4-11
AT-MIO-16XE-10 and AT-AI-16XE-10
(table), 4-13
AT-MIO-16XE-50 (table), 4-14
description (table), 4-8
waveform generation timing
connections, 4-46
GPCTR0_SOURCE signal, 4-44
GPCTR0_UP_DOWN signal, 4-46
GPCTR1_GATE signal, 4-47
GPCTR1_OUT signal
AT-MIO-16E-1, AT-MIO-16E-2 and
AT-MIO-64E-3 (table), 4-9
AT-MIO-16E-10 and AT-MIO-16DE-10
(table), 4-11
AT-MIO-16XE-10 and AT-AI-16XE-10
(table), 4-12
AT-MIO-16XE-50 (table), 4-14
description (table), 4-7
waveform generation timing connections,
4-48
GPCTR1_SOURCE signal, 4-47
GPCTR1_UP_DOWN signal, 4-48
ground-referenced signal sources
description, 4-17
differential connections, 4-21
single-ended connections (NRSE
configuration), 4-25
H
hardware installation, 2-1
hardware overview
analog input
considerations for selecting input
ranges, 3-10
dither, 3-10
input modes, 3-6
input polarity and range, 3-7
multiple-channel scanning
considerations, 3-11
analog output
output polarity selection, 3-13
reference selection, 3-13
reglitch selection, 3-14
analog trigger, 3-14
block diagram, 3-15
AT-AI-16XE-10 block diagram, 3-5
AT-MIO-16E-1 and AT-MIO-16E-2
block diagram, 3-1
AT-MIO-16E-10 and AT-MIO-16DE-10
block diagram, 3-3
AT-MIO-16XE-10 block diagram, 3-4
AT-MIO-16XE-50 block diagram, 3-6
AT-MIO-64E-3 block diagram, 3-2
digital I/O, 3-18
timing signal routing
board and RTSI clocks, 3-20
programmable function inputs, 3-20
RTSI triggers, 3-20
help
professional services, D-1
technical support, D-1