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AT E Series User Manual

Multifunction I/O Devices for the PC AT

AT E Series User Manual

May 2002 Edition

Part Number 370507A-01

Summary of content (184 pages)

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DAQ AT E Series User Manual Multifunction I/O Devices for the PC AT AT E Series User Manual May 2002 Edition Part Number 370507A-01
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Support Worldwide Technical Support and Product Information ni.
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Important Information Warranty The AT E Series devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
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Compliance FCC/Canada Radio Frequency Interference Compliance* Determining FCC Class The Federal Communications Commission (FCC) has rules to protect wireless communications from interference. The FCC places digital electronics into two classes. These classes are known as Class A (for use in industrial-commercial locations only) or Class B (for use in residential or commercial locations). Depending on where it is operated, this product could be subject to restrictions in the FCC rules.
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Canadian Department of Communications This Class B digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations. Cet appareil numérique de la classe B respecte toutes les exigences du Règlement sur le matériel brouilleur du Canada. Compliance to EU Directives Readers in the European Union (EU) must refer to the Manufacturer’s Declaration of Conformity (DoC) for information** pertaining to the CE Mark compliance scheme.
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Contents About This Manual Conventions ...................................................................................................................xi National Instruments Documentation ............................................................................xii Related Documentation..................................................................................................xiii Chapter 1 Introduction About the AT E Series ......................................................................
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Contents Dither .............................................................................................................. 3-10 Multiple-Channel Scanning Considerations ................................................... 3-11 Analog Output ............................................................................................................... 3-13 Analog Output Reference Selection................................................................ 3-13 Analog Output Polarity Selection ..............
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Contents SISOURCE Signal ............................................................................4-39 SCANCLK Signal.............................................................................4-40 EXTSTROBE* Signal ......................................................................4-41 Waveform Generation Timing Connections ...................................................4-41 WFTRIG Signal ................................................................................4-41 UPDATE* Signal........
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Contents Appendix D Technical Support and Professional Services Glossary Index AT E Series User Manual x ni.
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About This Manual This manual describes the electrical and mechanical aspects of each device in the AT E Series product line and contains information concerning their operation and programming. Unless otherwise noted, text applies to all devices in the AT E Series.
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About This Manual bold Bold text denotes items that you must select or click in the software, such as menu items and dialog box options. Bold text also denotes parameter names. italic Italic text denotes variables, emphasis, a cross reference, or an introduction to a key concept. This font also denotes text that is a placeholder for a word or value that you must supply. NI-DAQ NI-DAQ refers to the NI-DAQ software for PC compatibles unless otherwise noted. PC PC refers to the PC AT series computers.
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About This Manual or the NI-DAQ documentation to help you write your application. If you have a large and complicated system, it is worthwhile to look through the software documentation before you configure the hardware. • Accessory installation guides or manuals—If you are using accessory products, read the terminal block and cable assembly installation guides. They explain how to physically connect the relevant pieces of the system. Consult these guides when you are making the connections.
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1 Introduction This chapter describes the AT E Series devices, lists what you need to get started, describes the optional software and optional equipment, and explains how to unpack the AT E Series device. About the AT E Series Thank you for buying an NI AT E Series device. The AT E Series devices are the first completely Plug and Play-compatible multifunction analog, digital, and timing I/O devices for the PC AT and compatible computers.
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Chapter 1 Introduction interface and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ devices in the PC. The AT E Series devices can interface to an SCXI system so that you can acquire over 3,000 analog signals from thermocouples, RTDs, strain gauges, voltage sources, and current sources. You can also acquire or generate digital signals for communication and control. SCXI is the instrumentation front end for plug-in DAQ devices.
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Chapter 1 Introduction Software Programming Choices When programming National Instruments DAQ hardware, you can use an NI application development environment (ADE) or other ADEs. In either case, you use NI-DAQ. NI-DAQ NI-DAQ, which shipped with the AT E Series device, has an extensive library of functions that you can call from the ADE. These functions allow you to use all the features of the AT E Series device.
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Chapter 1 Introduction National Instruments ADE Software LabVIEW features interactive graphics, a state-of-the-art interface, and a powerful graphical programming language. The LabVIEW Data Acquisition VI Library, a series of virtual instruments for using LabVIEW with National Instruments DAQ hardware, is included with LabVIEW.
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Chapter 1 Introduction Optional Equipment NI offers a variety of products to use with the AT E Series device, including cables, connector blocks, and other accessories, as follows: • Cables and cable assemblies, shielded and ribbon • Connector blocks, shielded and unshielded 50-, 68-, and 100-pin screw terminals • RTSI bus cables • SCXI modules and accessories for isolating, amplifying, exciting, and multiplexing signals for relays and analog output.
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Chapter 1 Introduction Unpacking The AT E Series device is shipped in an antistatic package to prevent electrostatic damage to the device. Electrostatic discharge can damage several components on the device. Caution Never touch the exposed pins of connectors. To avoid such damage in handling the device, take the following precautions: • Ground yourself using a grounding strap or by holding a grounded object.
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Chapter 1 Introduction pollution degree stated in Appendix A, Specifications. Pollution is foreign matter in a solid, liquid, or gaseous state that can produce a reduction of dielectric strength or surface resistivity. The following is a description of pollution degrees: • Pollution degree 1 means no pollution or only dry, nonconductive pollution occurs. The pollution has no influence. • Pollution degree 2 means that only nonconductive pollution occurs in most cases.
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Chapter 1 Introduction • Installation Category III is for measurements performed in the building installation. This category is a distribution level referring to hardwired equipment that does not rely on standard building insulation. Examples of Installation Category III include measurements on distribution circuits and circuit breakers.
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2 Installing and Configuring the Device This chapter explains how to install and configure the AT E Series device. Installing the Software Complete the following steps to install the software before installing the DAQ device. 1. Install the application development environment (ADE), such as LabVIEW or Measurement Studio, according to the instructions on the CD and the release notes. 2. Install NI-DAQ according to the instructions on the CD and the DAQ Quick Start Guide included with the device.
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Chapter 2 Installing and Configuring the Device 6. Insert the AT E Series device into an EISA or 16-bit ISA slot. It may be a tight fit, but do not force the device into place. 7. Screw the mounting bracket of the AT E Series device to the back panel rail of the computer. 8. Visually verify the installation. Make sure the device is not touching other devices or components and is fully inserted in the slot. 9. Replace the cover. 10. Plug in and turn on the computer.
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Chapter 2 Installing and Configuring the Device Application software can query the Configuration Manager to determine the resources assigned to each device without your involvement. The Plug and Play software is installed as a device driver or as an integral component of the computer BIOS. Switchless Data Acquisition You can use an AT E Series device in a non-Plug and Play system as a switchless DAQ device.
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Chapter 2 Installing and Configuring the Device The following tables provide information concerning possible conflicts when configuring the AT E Series device. Table 2-1.
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Chapter 2 Installing and Configuring the Device Table 2-1.
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Chapter 2 Installing and Configuring the Device Table 2-2.
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3 Hardware Overview This chapter presents an overview of the hardware functions on the AT E Series device. Figure 3-1 shows the block diagram for the AT-MIO-16E-1 and AT-MIO-16E-2.
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Chapter 3 Hardware Overview Figure 3-2 shows the block diagram for the AT-MIO-64E-3.
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Chapter 3 Hardware Overview Figure 3-3 shows the block diagram for the AT-MIO-16E-10 and AT-MIO-16DE-10.
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Chapter 3 Hardware Overview Figure 3-4 shows a block diagram for the AT-MIO-16XE-10.
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Chapter 3 Hardware Overview Figure 3-5 shows a block diagram for the AT-AI-16XE-10.
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Chapter 3 Hardware Overview Figure 3-6 shows a block diagram for the AT-MIO-16XE-50.
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Chapter 3 Hardware Overview 12 channels—four differentially configured channels and eight single-ended channels. Table 3-1 describes the three input configurations. Table 3-1. Available Input Configurations for the AT E Series Configuration Description DIFF A channel configured in DIFF mode uses two analog channel input lines. One line connects to the positive input of the device programmable gain instrumentation amplifier (PGIA), and the other connects to the negative input of the PGIA.
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Chapter 3 Hardware Overview AT-MIO-16E-10, and AT-MIO-16DE-10 have gains of 0.5, 1, 2, 5, 10, 20, 50, and 100 and are suited for a wide variety of signal levels. With the proper gain setting, you can use the full resolution of the ADC to measure the input signal. Table 3-2 shows the overall input range and precision according to the input range configuration and gain used. Table 3-2. Actual Range and Measurement Precision Range Configuration Gain Actual Input Range Precision1 0 to +10 V 1.0 2.0 5.
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Chapter 3 Hardware Overview You can calibrate the AT-MIO-16XE-10, AT-AI-16XE-10, and AT-MIO-16XE-50 AI circuitry for either a unipolar or bipolar polarity. If you mix unipolar and bipolar channels in the scan list and you are using NI-DAQ, then NI-DAQ loads the calibration constants appropriate to the polarity for which AI channel 0 is configured.
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Chapter 3 Hardware Overview Considerations for Selecting Input Ranges Which input polarity and range you select depends on the expected range of the incoming signal. A large input range can accommodate a large signal variation but reduces the voltage resolution. Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range. For best results, you should match the input range as closely as possible to the expected range of the input signal.
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Chapter 3 LSBs 6.0 LSBs 6.0 4.0 4.0 2.0 2.0 0.0 0.0 –2.0 –2.0 –4.0 –4.0 Hardware Overview –6.0 –6.0 0 100 200 300 400 0 500 a. Dither disabled; no averaging 100 200 300 400 500 b. Dither disabled; average of 50 acquisitions LSBs 6.0 LSBs 6.0 4.0 4.0 2.0 2.0 0.0 0.0 –2.0 –2.0 –4.0 –4.0 –6.0 –6.0 0 100 200 300 400 500 0 c. Dither enabled; no averaging 100 200 300 400 500 d. Dither enabled; average of 50 acquisitions Figure 3-7.
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Chapter 3 Hardware Overview When scanning among channels at various gains, the settling times may increase. When the PGIA switches to a higher gain, the signal on the previous channel may be well outside the new, smaller range. For instance, suppose a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1, and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1.
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Chapter 3 Hardware Overview Analog Output ♦ AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3, AT-MIO-16E-10, and AT-MIO-16DE-10 The AT E Series devices supply two channels of AO voltage at the I/O connector. You can select the reference and range for the AO circuitry through software. The reference can be either internal or external, whereas the range can be either bipolar or unipolar. ♦ AT-MIO-16XE-50 The AT-MIO-16XE-50 supplies two channels of AO voltage at the I/O connector.
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Chapter 3 Hardware Overview Selecting a bipolar range for a particular DAC means that any data written to that DAC is interpreted as two’s complement format. In two’s complement mode, data values written to the AO channel can be either positive or negative. If you select unipolar range, data is interpreted in straight binary format. In straight binary mode, data values written to the AO channel range must be positive.
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Chapter 3 Hardware Overview the full-scale range of the selected channel, and the resolution is that range divided by 256 for the AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3, and divided by 4,096 for the AT-MIO-16XE-10 and AT-AI-16XE-10. The PFI0/TRIG1 pin is a high-impedance input. Therefore, it is susceptible to crosstalk from adjacent pins, which can result in false triggering when the pin is left unconnected.
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Chapter 3 Hardware Overview lowValue Trigger Figure 3-9. Below-Low-Level Analog Triggering Mode In above-high-level analog triggering mode, the trigger is generated when the signal value is greater than highValue. LowValue is unused. highValue Trigger Figure 3-10. Above-High-Level Analog Triggering Mode In inside-region analog triggering mode, the trigger is generated when the signal value is between the lowValue and the highValue. highValue lowValue Trigger Figure 3-11.
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Chapter 3 Hardware Overview In high-hysteresis analog triggering mode, the trigger is generated when the signal value is greater than highValue, with the hysteresis specified by lowValue. highValue lowValue Trigger Figure 3-12. High-Hysteresis Analog Triggering Mode In low-hysteresis analog triggering mode, the trigger is generated when the signal value is less than lowValue, with the hysteresis specified by highValue. highValue lowValue Trigger Figure 3-13.
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Chapter 3 Hardware Overview Digital I/O The AT E Series devices contain eight lines of DIO for general-purpose use. You can individually configure each line through software for either input or output. The AT-MIO-16DE-10 has 24 additional DIO lines, configured as three 8-bit ports: PA<0..7>, PB<0..7>, and PC<0..7>. You can configure each port for both input and output in various combinations, with some handshaking capabilities. At system startup and reset, the digital I/O ports are all high impedance.
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Chapter 3 Hardware Overview RTSI Trigger<0..6> CONVERT* PFI<0..9> Sample Interval Counter TC GPCTR0_OUT Figure 3-14. CONVERT* Signal Routing This figure shows that CONVERT* can be generated from a number of sources, including the external signals RTSI<0..6> and PFI<0..9> and the internal signals Sample Interval Counter TC and GPCTR0_OUT.
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Chapter 3 Hardware Overview Programmable Function Inputs The 10 PFIs are connected to the signal routing multiplexer for each timing signal, and software can select one of the PFIs as the external source for a given timing signal. It is important to note that any of the PFIs can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously.
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Chapter 3 Hardware Overview DAQ-STC TRIG1 TRIG2 CONVERT* WFTRIG GPCTR0_SOURCE RTSI Switch RTSI Bus Connector UPDATE* Trigger 7 GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE Clock GPCTR1_GATE Switch RTSI_OSC (20 MHz) Figure 3-15. RTSI Bus Signal Connection Refer to the Timing Connections section of Chapter 4, Connecting Signals, for a description of the signals shown in Figure 3-15.
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4 Connecting Signals This chapter describes how to make input and output signal connections to the AT E Series device using the device I/O connector. Table 4-1.
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Chapter 4 Connecting Signals ACH8 ACH1 AIGND ACH10 ACH3 AIGND ACH4 AIGND ACH13 ACH6 AIGND ACH15 1 DAC0OUT 1 DAC1OUT EXTREF2 DIO4 DGND DIO1 DIO6 DGND +5V DGND DGND PFI0/TRIG1 PFI1/TRIG2 DGND +5V DGND PFI5/UPDATE* PFI6/WFTRIG DGND PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 1 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 ACH0 AIGND ACH9 ACH2 AIGND ACH11 AISENSE A
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Chapter 4 AIGND AIGND ACH0 ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DAC0OUT DAC1OUT EXTREF AOGND DGND DIO0 DIO4 DIO1 DIO5 DIO2 DIO6 DIO3 DIO7 DGND +5V +5V SCANCLK EXTSTROBE* FI0/TRIG1 PFI1/TRIG2 PFI2/CONVERT* PFI3/GPCTR1_SOURCE PFI4/GPCTR1_GATE GPCTR1_OUT PFI5/UPDATE* PFI6/WFTRIG PFI7/STARTSCAN PFI8/GPCTR0_SOURCE PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Chapter 4 Connecting Signals AIGND AIGND ACH0 ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DAC0OUT DAC1OUT EXTREF AOGND DGND DIO0 DIO4 DIO1 DIO5 DIO2 DIO6 DIO3 DIO7 DGND +5V +5V SCANCLK EXTSTROBE* PFI0/TRIG1 PFI1/TRIG2 PFI2/CONVERT* PFI3/GPCTR1_SOURCE PFI4/GPCTR1_GATE GPCTR1_OUT PFI5/UPDATE* PFI6/WFTRIG PFI7/STARTSCAN PFI8/GPCTR0_SOURCE PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
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Chapter 4 Connecting Signals I/O Connector Signal Descriptions Table 4-2. I/O Signal Summary for the AT E Series Signal Name Reference Direction Description — — Analog Input Ground—These pins are the reference point for single-ended measurements and the bias current return point for differential measurements. All three ground references—AIGND, AOGND, and DGND—are connected together on the AT E Series device. ACH<0..
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Chapter 4 Connecting Signals Table 4-2. I/O Signal Summary for the AT E Series (Continued) Signal Name Reference Direction Description PA<0..7> DGND Input or Output Port A—These pins are port A of the extra digital I/O signals on the AT-MIO-16DE-10. PB<0..7> DGND Input or Output Port B—These pins are port B of the extra digital I/O signals on the AT-MIO-16DE-10. PC<0..7> DGND Input or Output Port C—These pins are port C of the extra digital I/O signals on the AT-MIO-16DE-10.
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Chapter 4 Connecting Signals Table 4-2. I/O Signal Summary for the AT E Series (Continued) Signal Name Reference Direction Description DGND Input PFI3/Counter 1 Source—As an input, this is one of the PFIs. PFI3/GPCTR1_SOURCE Output PFI4/GPCTR1_GATE DGND As an output, this is the GPCTR1_SOURCE signal. This signal reflects the actual source connected to the general-purpose counter 1. Input PFI4/Counter 1 Gate—As an input, this is one of the PFIs.
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Chapter 4 Connecting Signals Table 4-2. I/O Signal Summary for the AT E Series (Continued) Signal Name Reference Direction Description GPCTR0_OUT DGND Output Counter 0 Output—This output is from the general-purpose counter 0 output. FREQ_OUT DGND Output Frequency Output—This output is from the frequency generator output. Table 4-3.
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Chapter 4 Connecting Signals Table 4-3. I/O Signal Summary for the AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 (Continued) Drive Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias PFI1/TRIG2 DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI2/CONVERT* DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI3/GPCTR1_SOURCE DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI4/GPCTR1_GATE DIO — Vcc +0.
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Chapter 4 Connecting Signals Table 4-4. I/O Signal Summary for the AT-MIO-16E-10 and AT-MIO-16DE-10 Signal Name Drive Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias ACH<0..15> AI 100 GΩ in parallel with 50 pF 35/25 — — — ±200 pA AISENSE AI 100 GΩ in parallel with 50 pF 35/25 — — — ±200 pA AIGND AO — — — — — — DAC0OUT AO 0.1 Ω Short-circuit to ground 5 at 10 5 at –10 15 V/µs — DAC1OUT AO 0.
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Chapter 4 Connecting Signals Table 4-4. I/O Signal Summary for the AT-MIO-16E-10 and AT-MIO-16DE-10 (Continued) Drive Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias PFI4/GPCTR1_GATE DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu GPCTR1_OUT DO — — 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI5/UPDATE* DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.
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Chapter 4 Connecting Signals Table 4-5. I/O Signal Summary for the AT-MIO-16XE-10 and AT-AI-16XE-10 Signal Name Drive Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias ACH<0..15> AI 100 GΩ in parallel with 100 pF 25/15 — — — ±1 nA AISENSE AI 100 GΩ in parallel with 100 pF 25/15 — — — ±1 nA AIGND AO — — — — — — DAC0OUT AO 0.1 Ω Short-circuit to ground 5 at 10 5 at –10 5 V/µs — DAC1OUT AO 0.
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Chapter 4 Connecting Signals Table 4-5. I/O Signal Summary for the AT-MIO-16XE-10 and AT-AI-16XE-10 (Continued) Drive Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias PFI6/WFTRIG DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI7/STARTSCAN DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI8/GPCTR0_SOURCE DIO — Vcc +0.5 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI9/GPCTR0_GATE DIO — Vcc +0.5 3.
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Chapter 4 Connecting Signals Table 4-6. I/O Signal Summary for the AT-MIO-16XE-50 (Continued) Drive Impedance Input/ Output Protection (Volts) On/Off Source (mA at V) Sink (mA at V) Rise Time (ns) Bias VCC DO 0.1 Ω Short-circuit to ground 1A — — — DIO<0..7> DIO — Vcc +0.5 13 at (Vcc –0.4) 24 at 0.4 1.1 50 kΩ pu1 SCANCLK DO — — 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu EXTSTROBE* DO — — 3.5 at (Vcc –0.4) 5 at 0.4 1.5 50 kΩ pu PFI0/TRIG1 DIO — Vcc +0.5 3.
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Chapter 4 Connecting Signals Table 4-6. I/O Signal Summary for the AT-MIO-16XE-50 (Continued) Signal Name FREQ_OUT Drive Impedance Input/ Output Protection (Volts) On/Off DO — — Source (mA at V) Sink (mA at V) Rise Time (ns) Bias 3.5 at (Vcc–0.4) 5 at 0.4 1.5 50 kΩ pu 1 DIO<6..7> are also pulled down with a 50 kΩ resistor.
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Chapter 4 Connecting Signals In NRSE mode, the AISENSE and AISENSE2 signals are connected internally to the negative input of the AT E Series device PGIA when their corresponding channels are selected. In DIFF and RSE modes, these signals are left unconnected. AIGND is an AI common signal that is routed directly to the ground tie point on the AT E Series devices. You can use this signal for a general analog ground tie point to the AT E Series device if necessary.
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Chapter 4 Connecting Signals You must reference all signals to ground either at the source device or at the device. If you have a floating source, you should reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors. See the Differential Connections for Nonreferenced or Floating Signal Sources section later in this chapter. If you have a grounded source, you should not reference the signal to AIGND.
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Chapter 4 Connecting Signals Input Configurations You can configure the AT E Series device for one of three input modes—NRSE, RSE, or DIFF. The following sections discuss the use of single-ended and differential measurements and considerations for measuring both floating and ground-referenced signal sources. Figure 4-5 summarizes the recommended input configuration for both types of signal sources. AT E Series User Manual 4-18 ni.
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Chapter 4 Connecting Signals Signal Source Type Input Floating Signal Source (Not Connected to Building Ground) Grounded Signal Source Examples • Ungrounded Thermocouples • Signal Conditioning with Isolated Outputs • Battery Devices Examples • Plug-in Instruments with Nonisolated Outputs ACH(+) + V 1 – Differential (DIFF) ACH(–) ACH(+) + + V 1 – – ACH(–) + – R AIGND AIGND See text for information on bias resistors.
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Chapter 4 Connecting Signals Differential Connection Considerations (DIFF Input Configuration) A differential connection is one in which the AT E Series device AI signal has its own reference signal or signal return path. These connections are available when the selected channel is configured in DIFF input mode. The input signal is tied to the positive input of the PGIA, and its reference signal, or return, is tied to the negative input of the PGIA.
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Chapter 4 Connecting Signals Differential Connections for Ground-Referenced Signal Sources Figure 4-6 shows how to connect a ground-referenced signal source to an AT E Series device channel configured in DIFF input mode. ACH+ GroundReferenced Signal Source + Vs + – Programmable Gain Instrumentation Amplifier PGIA ACH– – CommonMode Noise and Ground Potential Vm + Measured Voltage – + Vcm – Input Multiplexers AISENSE AIGND I/O Connector Selected Channel in DIFF Configuration Figure 4-6.
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Chapter 4 Connecting Signals Differential Connections for Nonreferenced or Floating Signal Sources Figure 4-7 shows how to connect a floating signal source to an AT E Series device channel configured in DIFF input mode. ACH+ Floating Signal Source + Bias Resistors (see text) Vs + – Programmable Gain Instrumentation Amplifier PGIA + ACH– – Measured Voltage Vm – Bias Current Return Paths Input Multiplexers AISENSE AIGND I/O Connector Selected Channel in DIFF Configuration Figure 4-7.
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Chapter 4 Connecting Signals as to the negative input of the PGIA, without any resistors at all. This connection works well for DC-coupled sources with low source impedance (less than 100 Ω). However, for larger source impedances, this connection leaves the differential signal path significantly out of balance. Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground.
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Chapter 4 Connecting Signals Single-Ended Connection Considerations A single-ended connection is one in which the AT E Series device AI signal is referenced to a ground that can be shared with other input signals. The input signal is tied to the positive input of the PGIA, and the ground is tied to the negative input of the PGIA. When every channel is configured for single-ended input, up to 16 analog input channels are available (up to 64 channels on the AT-MIO-64E-3).
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Chapter 4 Connecting Signals Single-Ended Connections for Floating Signal Sources (RSE Configuration) Figure 4-8 shows how to connect a floating signal source to an AT E Series device channel configured for RSE mode. ACH Floating Signal Source Programmable Gain Instrumentation Amplifier + + Vs PGIA – + Input Multiplexers – AISENSE Measured Voltage Vm – AIGND I/O Connector Selected Channel in RSE Configuration Figure 4-8.
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Chapter 4 Connecting Signals Figure 4-9 shows how to connect a grounded signal source to an AT E Series device channel configured for NRSE mode. ACH+ I/O Connector GroundReferenced Signal Source + Vs + – Programmable Gain Instrumentation Amplifier PGIA ACH– – CommonMode Noise and Ground Potential Vm + Measured Voltage – Input Multiplexers AISENSE + Vcm AIGND – Selected Channel in NRSE Configuration Figure 4-9.
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Chapter 4 Connecting Signals that (Vin+) + (Vin–) added to the gain times (Vin+) – (Vin–) must be within ±26 V of AIGND. At gains of 10 and 100, this is roughly equivalent to restricting the two input voltages to within ±8 V of AIGND. Analog Output Signal Connections The AO signals are DAC0OUT, DAC1OUT, EXTREF, and AOGND. Note DAC0OUT and DAC1OUT are not available on the AT-AI-16XE-10. EXTREF is not available on the AT-MIO-16XE-10, AT-AI-16XE-10, or AT-MIO-16XE-50.
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Chapter 4 Connecting Signals EXTREF DAC0OUT External Reference Signal (Optional) + Channel 0 + Vref – VOUT 0 Load – AOGND – VOUT 1 Load DAC1OUT + Channel 1 Analog Output Channels I/O Connector Figure 4-10. AO Connections The external reference signal can be either a DC or an AC signal. The device multiplies this reference signal by the DAC code (divided by the full-scale DAC code) to generate the output voltage. Digital I/O Signal Connections The digital I/O signals are DIO<0..7> and DGND.
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Chapter 4 Connecting Signals Figure 4-11 shows signal connections for three typical DIO applications. +5 V LED DIO<4..7> TTL Signal DIO<0..3> +5 V Switch DGND I/O Connector Figure 4-11. DIO Connections Figure 4-11 shows DIO<0..3> configured for digital input and DIO<4..7> configured for digital output. Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the figure.
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Chapter 4 Connecting Signals Under no circumstances should you connect these +5 V power pins directly to analog or digital ground or to any other voltage source on the AT E Series device or any other device. Doing so can damage the AT E Series device and the PC. NI is not liable for damage resulting from such a connection. Caution Timing Connections Exceeding the maximum input voltage ratings, which are listed in Tables 4-3 through 4-6, can damage the AT E Series device and the PC.
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Chapter 4 Connecting Signals PFI0/TRIG1 PFI2/CONVERT* TRIG1 Source CONVERT* Source DGND I/O Connector Figure 4-12. TIO Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins. The source for each of these signals is software selectable from any of the PFIs when you want external control.
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Chapter 4 Connecting Signals depends upon the particular timing signal being controlled. The detection requirements for each timing signal are listed within the section that discusses that individual signal. In edge-detection mode, the minimum pulse width required is 10 ns. This applies for both rising-edge and falling-edge polarity settings. There is no maximum pulse-width requirement in edge-detect mode.
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Chapter 4 Connecting Signals TRIG1 TRIG2 Don't Care STARTSCAN CONVERT* Scan Counter 3 2 1 0 2 2 2 1 0 Figure 4-14. Typical Pretriggered Acquisition TRIG1 Signal Any PFI pin can externally input the TRIG1 signal, which is available as an output on the PFI0/TRIG1 pin. Refer to Figures 4-13 and 4-14 for the relationship of TRIG1 to the DAQ sequence. As an input, the TRIG1 signal is configured in the edge-detection mode.
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Chapter 4 Connecting Signals Figures 4-15 and 4-16 show the input and output timing requirements for the TRIG1 signal. tw Rising-Edge Polarity Falling-Edge Polarity tw= 10 ns minimum Figure 4-15. TRIG1 Input Signal Timing tw tw = 50 to 100 ns Figure 4-16. TRIG1 Output Signal Timing The device also uses the TRIG1 signal to initiate pretriggered DAQ operations. In most pretriggered applications, the TRIG1 signal is generated by a software trigger.
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Chapter 4 Connecting Signals before TRIG2 can be recognized. After the scan counter decrements to zero, it is loaded with the number of posttrigger scans to acquire while the acquisition continues. The device ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero. After the selected edge of TRIG2 is received, the device acquires a fixed number of scans and the acquisition stops. This mode acquires data both before and after receiving TRIG2.
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Chapter 4 Connecting Signals STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal, which is available as an output on the PFI7/STARTSCAN pin. Refer to Figures 4-13 and 4-14 for the relationship of STARTSCAN to the DAQ sequence. As an input, the STARTSCAN signal is configured in the edge-detection mode. You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge. The selected edge of the STARTSCAN signal initiates a scan.
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Chapter 4 Connecting Signals tw STARTSCAN tw = 50 to 100 ns a. Start of Scan Start Pulse CONVERT* STARTSCAN toff = 10 ns minimum toff b. Scan in Progress, Two Conversions per Scan Figure 4-20. STARTSCAN Output Signal Timing The CONVERT* pulses are masked off until the device generates the STARTSCAN signal. If you are using internally generated conversions, the first CONVERT* appears when the onboard sample interval counter reaches zero.
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Chapter 4 Connecting Signals CONVERT* Signal Any PFI pin can externally input the CONVERT* signal, which is available as an output on the PFI2/CONVERT* pin. Refer to Figures 4-13 and 4-14 for the relationship of CONVERT* to the DAQ sequence. As an input, the CONVERT* signal is configured in the edge-detection mode. You can select any PFI pin as the source for CONVERT* and configure the polarity selection for either rising or falling edge.
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Chapter 4 Connecting Signals The ADC switches to hold mode within 60 ns of the selected edge. This hold-mode delay time is a function of temperature and does not vary from one conversion to the next. Separate the CONVERT* pulses by at least one conversion period. The sample interval counter on the AT E Series device normally generates the CONVERT* signal unless you select some external source.
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Chapter 4 Connecting Signals Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source. Figure 4-23 shows the timing requirements for the SISOURCE signal. tp tw tw tp = 50 ns minimum tw = 23 ns minimum Figure 4-23. SISOURCE Signal Timing SCANCLK Signal SCANCLK is an output-only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A/D conversion begins.
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Chapter 4 Connecting Signals EXTSTROBE* Signal EXTSTROBE* is an output-only signal that generates either a single pulse or a sequence of eight pulses in the hardware-strobe mode. An external device can use this signal to latch signals or to trigger events. In the single-pulse mode, software controls the level of the EXTSTROBE* signal. A 10 µs and a 1.2 µs clock are available for generating a sequence of eight pulses in the hardware-strobe mode.
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Chapter 4 Connecting Signals Figures 4-26 and 4-27 show the input and output timing requirements for the WFTRIG signal. tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 4-26. WFTRIG Input Signal Timing tw tw = 50 to 100 ns Figure 4-27. WFTRIG Output Signal Timing UPDATE* Signal Any PFI pin can externally input the UPDATE* signal, which is available as an output on the PFI5/UPDATE* pin. As an input, the UPDATE* signal is configured in the edge-detection mode.
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Chapter 4 Connecting Signals When using an external UPDATE signal, you must apply at least one more external update pulse than the number of points that you want to generate. This is necessary for proper hardware operation, otherwise the device does not indicate that the waveform generation is complete. Figures 4-28 and 4-29 show the input and output timing requirements for the UPDATE* signal. tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 4-28.
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Chapter 4 Connecting Signals UISOURCE Signal Any PFI pin can externally input the UISOURCE signal, which is not available as an output on the I/O connector. The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE* signal. You must configure the PFI pin you select as the source for the UISOURCE signal in the level-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low.
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Chapter 4 Connecting Signals As an output, the GPCTR0_SOURCE signal reflects the actual clock connected to general-purpose counter 0, even if another PFI is externally inputting the source clock. This output is set to high-impedance at startup. Figure 4-31 shows the timing requirements for the GPCTR0_SOURCE signal. tp tw tw tp = 50 ns minimum tw = 23 ns minimum Figure 4-31. GPCTR0_SOURCE Signal Timing The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low.
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Chapter 4 Connecting Signals Figure 4-32 shows the timing requirements for the GPCTR0_GATE signal. tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 4-32. GPCTR0_GATE Signal Timing in Edge-Detection Mode GPCTR0_OUT Signal This signal is available only as an output on the GPCTR0_OUT pin. The GPCTR0_OUT signal reflects the terminal count (TC) of general-purpose counter 0. You have two software-selectable output options—pulse on TC and toggle output polarity on TC.
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Chapter 4 Connecting Signals GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal, which is available as an output on the PFI3/GPCTR1_SOURCE pin. As an input, the GPCTR1_SOURCE signal is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge.
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Chapter 4 Connecting Signals As an output, the GPCTR1_GATE signal monitors the actual gate signal connected to general-purpose counter 1, even if the gate is being externally generated by another PFI. This output is set to high-impedance at startup. Figure 4-35 shows the timing requirements for the GPCTR1_GATE signal. tw Rising-Edge Polarity Falling-Edge Polarity tw = 10 ns minimum Figure 4-35.
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Chapter 4 Connecting Signals leave the DIO7 pin free for general use. Figure 4-37 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of the AT E Series device.
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Chapter 4 Connecting Signals If an internal timebase clock is used, the gate signal cannot be synchronized with the clock. In this case, gates applied close to a source edge take effect either on that source edge or on the next one. This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources.
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Chapter 4 Connecting Signals Table 4-7. Port C Signal Assignments (Continued) Group A Programming Mode Mode 2 PC7 PC6 OBFA* ACKA* PC5 IBFA Group B PC4 PC3 STBA* INTRA PC2 I/O PC1 I/O PC0 I/O * Indicates that the signal is active low. This section lists the timing specifications for handshaking with the AT-MIO-16DE-10 port C circuitry. The handshaking lines STB* and IBF synchronize input transfers. The handshaking lines OBF* and ACK* synchronize output transfers.
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Chapter 4 Connecting Signals Mode 1 Input Timing Figure 4-38 details the timing specifications for an input transfer in Mode 1. T1 T2 T4 STB * T7 IBF T6 INTR RD * T3 T5 DATA Name Description Minimum Maximum T1 STB* Pulse Width 100 — T2 STB* = 0 to IBF = 1 — 150 T3 Data before STB* = 1 20 — T4 STB* = 1 to INTR = 1 — 150 T5 Data after STB* = 1 50 — T6 RD* = 0 to INTR = 0 — 200 T7 RD* = 1 to IBF = 0 — 150 All timing values are in nanoseconds. Figure 4-38.
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Chapter 4 Connecting Signals Mode 1 Output Timing Figure 4-39 details the timing specifications for an output transfer in Mode 1. T3 WR* T4 OBF* T1 T6 INTR T5 ACK* DATA T2 Name Description Minimum Maximum T1 WR* = 0 to INTR = 0 — 250 T2 WR* = 1 to Output — 200 T3 WR* = 1 to OBF* = 0 — 150 T4 ACK* = 0 to OBF* = 1 — 150 T5 ACK* Pulse Width 100 — T6 ACK* = 1 to INTR = 1 — 150 All timing values are in nanoseconds. Figure 4-39.
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Chapter 4 Connecting Signals Mode 2 Bidirectional Timing Figure 4-40 details the timing specifications for bidirectional transfers in Mode 2.
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Chapter 4 Connecting Signals Field Wiring Considerations Environmental noise can seriously affect the accuracy of measurements made with the AT E Series device if you do not take proper care when running signal wires between signal sources and the device. The following recommendations apply mainly to AI signal routing to the device, although they also apply to signal routing in general.
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Calibrating the Device 5 This chapter discusses the calibration procedures for the AT E Series device. NI-DAQ includes calibration functions for performing all of the steps in the calibration process. Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments. On the AT E Series devices, these adjustments take the form of writing values to onboard calibration DACs (CalDACs).
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Chapter 5 Calibrating the Device vary with time and temperature. It is better to self-calibrate when the device is installed in the environment in which it is used. Self-Calibration The AT E Series device can measure and correct for almost all of its calibration-related errors without any external signal connections. The NI software provides a self-calibration method you can use.
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Chapter 5 Calibrating the Device a 16-bit device, the external reference should be at least ±0.001% (±10 ppm) accurate. For a detailed calibration procedure for the AT E Series device, refer to the E Series Calibration Procedure by clicking Manual Calibration Procedures at ni.com/calibration. Other Considerations The CalDACs adjust the gain error of each AO channel by adjusting the value of the reference voltage supplied to that channel.
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A Specifications This appendix lists the specifications of each device in the AT E Series. These specifications are typical at 25 °C unless otherwise noted. AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Analog Input Input Characteristics Number of channels AT-MIO-16E-1, AT-MIO-16E-2 ............................... 16 single-ended or 8 differential (software selectable) AT-MIO-64E-3 ............................... 64 single-ended or 32 differential (software selectable) Type of ADC.........................
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Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Input signal ranges Range (Software Selectable) Input Range Bipolar Unipolar 20 V ±10 V — 10 V ±5 V 0 to 10 V 5V ±2.5 V 0 to 5 V 2V ±1 V 0 to 2 V 1V ±500 mV 0 to 1 V 500 mV ±250 mV 0 to 500 mV 200 mV ±100 mV 0 to 200 mV 100 mV ±50 mV 0 to 100 mV Input coupling.........................................DC Max working voltage (signal + common mode) ........................
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Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Transfer Characteristics Relative accuracy ................................... ±0.5 LSB typ dithered, ±1.5 LSB max undithered DNL ....................................................... ±0.5 LSB typ, ±1.0 LSB max No missing codes ................................... 12 bits, guaranteed Offset error Pregain error after calibration ......... ±12 µV max Pregain error before calibration ...... ±2.
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Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Dynamic Characteristics Bandwidth Small Signal (–3dB) Large Signal (1% THD) AT-MIO-16E-1 1.6 MHz 1 MHz AT-MIO-16E-2, AT-MIO-64E-3 1 MHz 300 kHz Settling time for full-scale step Accuracy* Gain AT-MIO-16E-1 ±0.012% (±0.5 LSB) ±0.024% (±1 LSB) ±0.098% (±4 LSB) 0.5 2 µs typ 3 µs max 1.5 µs typ 2 µs max 1.5 µs typ 2 µs max 1 2 µs typ 3 µs max 1.5 µs typ 2 µs max 1.3 µs typ 1.5 µs max 2 to 50 2 µs typ 3 µs max 1.
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Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 System noise (LSBrms not including quantization) AT-MIO-16E-1 AT-MIO-16E-2, AT-MIO-64E-3 Gain Noise, Dither Off Noise, Dither On 0.5 to 10 0.25 0.5 20 0.4 0.6 50 0.5 0.7 100 0.8 0.9 0.5 to 20 0.15 0.5 50 0.3 0.6 100 0.5 0.7 Crosstalk, DC to 100 kHz Adjacent channels ........................... –75 dB All other channels ........................... –90 dB Stability Offset temperature coefficient Pregain ..
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Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Non-FIFO mode waveform generation 1 channel ..................................800 kS/s (system dependent) 2 channel ..................................400 kS/s (system dependent) Type of DAC ..........................................Double buffered, multiplying FIFO buffer size .....................................2,048 samples Data transfers ..........................................DMA, interrupts, programmed I/O DMA modes .......
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Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Voltage Output Ranges .................................................... ±10 V, 0 to 10 V, ±EXTREF, 0 to EXTREF (software selectable) Output coupling...................................... DC Output impedance .................................. 0.1 Ω max Current drive .......................................... ±5 mA max Protection ............................................... Short-circuit to ground Power-on state................
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Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Digital I/O Number of channels................................8 input/output Compatibility ..........................................TTL/CMOS Digital logic levels Level Min Max Input low voltage 0V 0.8 V Input high voltage 2V 5V Input low current (Vin = 0 V) — –320 µA Input high current (Vin = 5 V) — 10 µA Output low voltage (IOL = 24 mA) — 0.4 V Output high voltage (IOH = 13 mA) 4.35 V — Power-on state .......
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Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Min source pulse duration...................... 10 ns in edge-detect mode Min gate pulse duration.......................... 10 ns in edge-detect mode Data transfers ......................................... DMA, interrupts, programmed I/O DMA modes........................................... Single transfer, demand transfer Triggers Analog Trigger Source..................................................... ACH<0..
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Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 RTSI Trigger lines............................................7 Calibration Recommended warm-up time.................15 min Calibration interval .................................1 year External calibration reference.................>6 and <10 V Onboard calibration reference Level ................................................5.000 V (±3.
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Appendix A Specifications for AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common-mode voltage. Channel-to-earth..................................... 42 V, Installation Category II Channel-to-channel ................................ 42 V, Installation Category II Environmental Operating temperature............................ 0 to 55 °C Storage temperature ............................... –20 to 70 °C Humidity ..........
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Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 appropriate product family, followed by the product, and a link to the DoC appears in Adobe Acrobat format. Click the Acrobat icon to download or read the DoC. AT-MIO-16E-10 and AT-MIO-16DE-10 Analog Input Input Characteristics Number of channels................................16 single-ended or 8 differential, software selectable Type of ADC ..........................................Successive approximation Resolution .......................
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Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Inputs protected...................................... ACH<0..15>, AISENSE FIFO buffer size ..................................... 512 samples Data transfers ......................................... DMA, interrupts, programmed I/O Transfer rate (1 word = 8 bits) ............... 50 kwords/s DMA modes........................................... Single transfer, demand transfer Configuration memory size....................
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Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Input offset current .................................±100 pA CMRR (all input ranges) ........................90 dB, DC to 60 Hz Dynamic Characteristics Bandwidth Small signal (–3 dB)........................150 kHz Large signal (1% THD) ...................120 kHz Settling time for full-scale step1 .............10 µs max to ±0.5 LSB accuracy System noise (not including quantization) Gain Noise, Dither Off Noise, Dither On 0.5 to 10 0.
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Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Max update rate...................................... 100 kS/s, system dependent Type of DAC.......................................... Double buffered, multiplying FIFO buffer size ..................................... None Data transfers ......................................... DMA, interrupts, programmed I/O DMA modes...........................................
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Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Output impedance...................................0.1 Ω max Current drive...........................................±5 mA max Protection................................................Short-circuit to ground Power-on state ........................................0 V (±200 mV) External reference input Range...............................................±11 V Overvoltage protection ....................
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Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Digital logic levels Level Min Max Input low voltage 0V 0.8 V Input high voltage 2V 5V Input low current (Vin = 0 V) — –320 µA Input high current (Vin = 5 V) — 10 µA Output low voltage (IOL = 24 mA) — 0.4 V Output high voltage (IOH = 13 mA) 4.35 V — Min Max Input low voltage 0V 0.
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Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Timing I/O Number of channels................................2 up/down counter/timers, 1 frequency scaler Resolution Counter/timers .................................24 bits Frequency scalers ............................4 bits Compatibility ..........................................TTL/CMOS Base clocks available Counter/timers .................................20 MHz, 100 kHz Frequency scaler..............................
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Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Calibration Recommended warm-up time ................ 15 min Calibration interval ................................ 1 year External calibration reference ................ >6 and <10V Onboard calibration reference Level ............................................... 5.000 V (±3.5 mV) (over full operating temperature, actual value stored in EEPROM) Temperature coefficient .................. ±5 ppm/°C max Long-term stability .....................
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Appendix A Specifications for AT-MIO-16E-10 and AT-MIO-16DE-10 Environmental Operating temperature ............................0 to 55 °C Storage temperature ................................–20 to 70 °C Humidity .................................................10 to 90% RH, noncondensing Maximum altitude...................................2,000 meters Pollution degree (indoor use only) .........
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Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 AT-MIO-16XE-10 and AT-AI-16XE-10 Analog Input Input Characteristics Number of channels ............................... 16 single-ended or 8 differential (software-selectable) Type of ADC.......................................... Successive approximation Resolution .............................................. 16 bits, 1 in 65,536 Maximum sampling rate ........................
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Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 FIFO buffer size......................................512 samples Data transfers ..........................................DMA, interrupts, programmed I/O DMA modes ...........................................Single transfer, demand transfer Configuration memory size ....................512 words Transfer Characteristics Relative accuracy....................................±0.75 LSB typ, ±1 LSB max DNL .........................................
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Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 CMRR, DC to 60 Hz Range CMRR (Bipolar) CMRR (Unipolar) 20 V 92 dB — 10 V 97 dB 92 dB 5V — 97 dB 4V 101 dB — 2V 104 dB 101 dB 1V 105 dB 104 dB 100 mV to 500 mV 105 dB 105 dB Dynamic Characteristics Bandwidth All gains .......................................... 255 kHz Settling time for full-scale step Accuracy* ±0.00076% (±0.5 LSB) ±0.0015% (±1 LSB) ±0.
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Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Crosstalk, DC to 100 kHz Adjacent channels............................–75 dB max All other channels............................–90 dB max Stability Offset temperature coefficient Pregain.............................................±5 µV/°C Postgain ...........................................±120 µV/°C Gain temperature coefficient ..................±7 ppm/°C Analog Output (AT-MIO-16XE-10 only) Output Characteristics Number of channels........
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Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Gain error (relative to internal reference) After calibration .............................. ±30.5 ppm max Before calibration ........................... ±2,000 ppm max Voltage Output Range ..................................................... ±10 V, 0 to 10 V (software selectable) Output coupling...................................... DC Output impedance .................................. 0.1 Ω Current drive ..................................
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Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Level Min Max Input low current — –320 µA Input high current — 10 µA Output low voltage (IOL = 24 mA) — 0.4 V Output high voltage (IOH = 13 mA) 4.35 V — Power-on state ........................................Input (high-impedance) Data transfers ..........................................Programmed I/O Max transfer rate (1 word = 8 bits).........50 kwords/s, system dependent Constant sustainable rate ........................
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Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Triggers Analog Trigger Source..................................................... ACH<0..15>, PFI0/TRIG1 Level....................................................... ± Full-scale, internal; ±10 V, external Slope....................................................... Positive or negative (software selectable) Resolution .............................................. 12 bits, 1 in 4,096 Hysteresis ..............................................
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Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Calibration Recommended warm-up time.................15 min Calibration interval .................................1 year External calibration reference.................>6 and <9.999V Onboard calibration reference Level ................................................5.000 V (±1.0 mV) (over full operating temperature, actual value stored in EEPROM) Temperature coefficient...................±0.6 ppm/°C max Long-term stability ...................
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Appendix A Specifications for AT-MIO-16XE-10 and AT-AI-16XE-10 Environmental Operating temperature............................ 0 to 55 °C Storage temperature ............................... –20 to 70 °C Humidity ................................................ 10 to 90% RH, noncondensing Maximum altitude .................................. 2,000 meters Pollution degree (indoor use only).........
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Appendix A Specifications for AT-MIO-16XE-50 AT-MIO-16XE-50 Analog Input Input Characteristics Number of channels................................16 single-ended or 8 differential (software-selectable) Type of ADC ..........................................Successive approximation Resolution ...............................................16 bits, 1 in 65,536 Maximum sampling rate .........................
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Appendix A Specifications for AT-MIO-16XE-50 Data transfers ......................................... DMA, interrupts, programmed I/O DMA modes........................................... Single transfer, demand transfer Configuration memory size.................... 512 words Transfer Characteristics Relative accuracy ................................... ±0.5 LSB typ, ±1 LSB max DNL ....................................................... ±0.5 LSB typ, ±1 LSB max No missing codes ...........................
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Appendix A Specifications for AT-MIO-16XE-50 CMRR, DC to 60 Hz Range CMRR (Bipolar) CMRR (Unipolar) 20 V 80 dB — 10 V 86 dB 80 dB 5V — 86 dB 2V 100 dB — 1V — 100 dB 200 mV 120 dB — 100 mV — 120 dB Dynamic Characteristics Bandwidth Range Small Signal (–3dB) 5 to 20 V 63 kHz 1 to 2 V 57 kHz 100 to 200 mV 33 kHz Settling time for full-scale step Accuracy* ±0.0015% (±1 LSB) ±0.
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Appendix A Specifications for AT-MIO-16XE-50 System noise (LSBrms including quantization noise) Range Bipolar Unipolar 1 to 20 V 1.0 1.0 100 to 200 mV 1.2 1.6 Crosstalk, DC to 20 kHz Adjacent channels ........................... –85 dB max All other channels ........................... –100 dB max Stability Offset temperature coefficient Pregain ............................................ ±1 µV/°C Postgain........................................... ±12 µV/°C Gain temperature coefficient........
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Appendix A Specifications for AT-MIO-16XE-50 Offset error After calibration...............................±0.5 mV max Before calibration ............................±85 mV max Gain error (relative to calibration reference) After calibration...............................±0.01% of output max Before calibration ............................±1% of output max Voltage Output Range ......................................................±10 V Output coupling ......................................
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Appendix A Specifications for AT-MIO-16XE-50 Digital logic levels Level Min Max Input low voltage 0V 0.8 V Input high voltage 2V 5V Input low current (Vin = 0 V) — –320 µA Input high current (Vin = 5 V) — 10 µA Output low voltage (IOL = 24 mA) — 0.4 V Output high voltage (IOH = 13 mA) 4.35 V — Power-on state........................................ Input (high-impedance) Data transfers ......................................... Programmed I/O Max transfer rate (1 word = 8 bits) ........
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Appendix A Specifications for AT-MIO-16XE-50 Data transfers ..........................................DMA, interrupts, programmed I/O DMA modes ...........................................Single transfer Triggers Digital Trigger Compatibility ..........................................TTL Response .................................................Rising or falling edge Pulse width .............................................10 ns min RTSI Trigger Lines ..........................................
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Appendix A Specifications for AT-MIO-16XE-50 Physical Dimensions (not including connectors) ..................... 33.8 by 9.9 cm (13.3 by 3.9 in) I/O connector.......................................... 68-pin male SCSI-II type Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common-mode voltage. Channel-to-earth..................................... 42 V, Installation Category II Channel-to-channel ................................
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Appendix A Specifications for Maximum Signal Ratings for AT Series Devices Electromagnetic Compatibility CE, C-Tick, and FCC Part 15 (Class A) Compliant Electrical emissions ................................EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immunity ................................Evaluated to EN 61326:1998, Table 1 For full EMC compliance, you must operate this device with shielded cabling. In addition, all covers and filler panels must be installed.
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Appendix A Signal Name Specifications for Maximum Signal Ratings for AT Series Devices AT-MIO-16E-1 AT-MIO-16E-2 AT-MIO-64E-3 AT-MIO-16XE-10 AT-AI-16XE-10 AT-MIO-16E-10 AT-MIO-16DE-10 AT-MIO-16XE-50 On On On Off Off Off EXTREF ±25 V1 ±15 V1 ±35 V ±25 V ±25 V2 ±15 V2 PFI0 5.5 to –0.5 V3 ±35 V4 5.5 to –0.5 V3 ±0.5 V5 5.5 to –0.5 V3 ±0.5 V5 PFI<1..9> 5.5 to –0.5 V3 ±0.5 V5 5.5 to –0.5 V3 ±0.5 V5 5.5 to –0.5 V3 ±0.5 V5 DIO 5.5 to –0.5 V3 ±0.5 V5 5.5 to –0.5 V3 ±0.5 V5 5.
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Appendix A Specifications for Maximum Signal Ratings for AT Series Devices If any signal should fall outside of the specified limits for any of the input signals, do not connect it to the DAQ device. Before proceeding, add signal-conditioning circuitry to the signal in question to either attenuate or clip the voltage signal. If dynamic (for example, AC) signals are connected to the inputs, you must anticipate or calculate the maximum voltage that the signal may attain.
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Optional Cable Connector Descriptions B This appendix describes the connectors on the optional cables for the AT E Series devices. Figure B-1 shows the pin assignments for the 68-pin MIO connector. This connector is available when you use the SH6868-EP or R6868 cable assemblies with the AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16XE-10, AT-AI-16XE-10, or AT-MIO-16XE-50.
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Appendix B Optional Cable Connector Descriptions ACH8 ACH1 AIGND ACH10 ACH3 AIGND ACH4 AIGND ACH13 ACH6 AIGND ACH15 1 DAC0OUT 1 DAC1OUT EXTREF2 DIO4 DGND DIO1 DIO6 DGND +5V DGND DGND PFI0/TRIG1 PFI1/TRIG2 DGND +5V DGND PFI5/UPDATE* PFI6/WFTRIG DGND PFI9/GPCTR0_GATE GPCTR0_OUT FREQ_OUT 1 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 ACH0 AIGND ACH9 ACH2 AIGND ACH11 AISENSE 12 11 10 9 8 7 6 5 46 45 44 43 42 41 40 39
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Appendix B Optional Cable Connector Descriptions Figure B-2 shows the pin assignments for the 68-pin DIO connector. This is the other 68-pin connector available when you use the SH1006868 cable assembly with the AT-MIO-16DE-10.
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Appendix B Optional Cable Connector Descriptions Figure B-3 shows the pin assignments for the 68-pin extended AI connector. This is the other 68-pin connector available when you use the SH1006868 cable assembly with the AT-MIO-64E-3.
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Appendix B Optional Cable Connector Descriptions Figure B-4 shows the pin assignments for the 50-pin MIO connector. This connector is available when you use the SH6850 or R6850 cable assemblies with the AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16XE-10, AT-AI-16XE-10, or AT-MIO-16XE-50. It is also one of the two 50-pin connectors available when you use the R1005050 cable assembly with the AT-MIO-16DE-10 or AT-MIO-64E-3.
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Appendix B Optional Cable Connector Descriptions Figure B-5 shows the pin assignments for the 50-pin DIO connector. This is the other 50-pin connector available when you use the R1005050 cable assembly with the AT-MIO-16DE-10.
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Appendix B Optional Cable Connector Descriptions Figure B-6 shows the pin assignments for the 50-pin extended AI connector. This is the other 50-pin connector available when you use the R1005050 cable assembly with the AT-MIO-64E-3.
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C Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of the AT E Series device. General Information What are the AT E Series devices? The AT E Series devices are switchless and jumperless, enhanced MIO devices that use the DAQ-STC for timing. What is the DAQ-STC? The DAQ-STC is the new system timing control ASIC (application-specific integrated circuit) designed by NI and is the backbone of the AT E Series devices.
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Appendix C Common Questions relationship. Notice, however, that some AT E Series devices have settling times that vary with gain and accuracy. Refer to Appendix A, Specifications, for exact specifications What type of 5 V protection do the AT E Series devices have? The AT E Series devices have 5 V lines equipped with a self-resetting 1 A fuse.
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Appendix C Common Questions What version of NI-DAQ must I have to program my AT E Series device? You must have version 4.9.0 or later for the AT-MIO-16XE-10 and AT-AI-16XE-10, version 4.8.0 or later for the AT-MIO-16E-1, and version 4.6.1 or later for all other AT E Series devices. For AT-MIO-16E-10 and AT-MIO-16DE-10 users, you must have version 5.04 for Windows 3.1x, or 5.1 or later for Windows 95 and Windows NT.
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Appendix C Common Questions I’m using the DACs to generate a waveform, but I discovered with a digital oscilloscope that there are glitches on the output signal. Is this normal? When it switches from one voltage to another, any DAC produces glitches due to released charges. The largest glitches occur when the most significant bit (MSB) of the D/A code switches. You can build a lowpass deglitching filter to remove some of these glitches, depending on the frequency and nature of the output signal.
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Appendix C 4. Common Questions Initiate AO waveform generation. If you are using NI-DAQ, call WFM_Group_Control with operation set to 1 (start). If you are using LabVIEW, you can invoke AO Control VI with control code set to 0 (start). Can I programmatically enable different channels on an E Series board to acquire in different modes? For example, Channel 0 is differential and Channel 1 is RSE. Different channels on an E Series device can be enabled to acquire in different modes.
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Appendix C Common Questions next channel, for example channel 1, is selected, the accumulated charge (current) leaks backward through that channel. If the output impedance of the source connected to channel 1 is high enough, the resulting reading can somewhat reflect the voltage trends in channel 0. To circumvent this problem, you must use a voltage follower (op-amp with unity gain) for each high impedance source before connecting up to the DAQ device or decrease the rate at which each channel is sampled.
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Appendix C Common Questions Channel 0 Channel 1 Interchannel Delay Scan Interval Figure C-2. Comparing Interchannel Delay and Scan Interval Timing and Digital I/O What types of triggering can be implemented in hardware on my AT E Series device? Digital triggering is supported by hardware on every AT E Series MIO device. In addition, the AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3, AT-MIO-16XE-10, and AT-AI-16XE-10 support analog triggering in hardware.
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Appendix C Common Questions The counter/timer examples supplied with NI-DAQ are not compatible with an AT E Series device. Where can I find examples to illustrate the use of the DAQ-STC as a general-purpose counter/timer? If you are using the NI-DAQ language interface and a C compiler under DOS, a new subdirectory called GPCTR, which lies beneath the examples directory, contains 16 examples of the most common uses of the DAQ-STC.
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Appendix C Common Questions acquisition completes. The above error occurs because NI-DAQ disarms the counter from generating any more requests in the interrupt service routine. Due to interrupt latencies, it is possible that the counter may have generated some spurious requests which the DMA controller may not satisfy because it has already transferred the required number of points. What are the PFIs and how do I configure these lines? PFIs are Programmable Function Inputs.
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Appendix C Common Questions What are the power-on states of the PFI and DIO lines on the I/O connector? At system power-on and reset, both the PFI and DIO lines are set to high impedance by the hardware. This means that the device circuitry is not actively driving the output either high or low. However, these lines may have pull-up or pull-down resistors connected to them as shown in Tables 4-2 to 4-5. These resistors weakly pull the output to either a logic high or logic low state.
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Technical Support and Professional Services D Visit the following sections of the National Instruments Web site at ni.com for technical support and professional services: • Support—Online technical support resources include the following: – Self-Help Resources—For immediate answers and solutions, visit our extensive library of technical support resources available in English, Japanese, and Spanish at ni.com/support.
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Glossary Prefix Meaning Value p- pico- 10 –12 n- nano- 10 –9 µ- micro- 10 – 6 m- milli- 10 –3 k- kilo- 10 3 M- mega- 10 6 G- giga- 10 9 Numbers/Symbols % percent ± plus or minus ° degrees / per + positive of, or plus – negative of, or minus Ω ohms 000 +5V square root of +5 VDC source signal A A amperes A/D analog-to-digital © National Instruments Corporation G-1 AT E Series User Manual
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Glossary AC alternating current ACH analog input channel signal ADC A/D converter AIGATE analog input gate signal AIGND analog input ground signal AISENSE analog input sense signal AISENSE2 analog input sense 2 signal ANSI American National Standards Institute AOGND analog output ground signal ASIC application-specific integrated circuit B BIOS basic input/output system or built-in operating system C C Celsius CalDAC calibration DAC channel rate reciprocal of the interchannel del
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Glossary DAC0OUT analog channel 0 output signal DAC1OUT analog channel 1 output signal DAQ data acquisition DC direct current DGND digital ground signal DIFF differential mode DIO digital input/output DMA direct memory access DNL differential nonlinearity E EEPROM electrically erasable programmable read-only memory EISA Extended Industry Standard Architecture EXTREF external reference signal EXTSTROBE external strobe signal F FIFO first-in-first-out FREQ_OUT frequency output si
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Glossary GPCTR1_OUT general purpose counter 1 output signal GPCTR0_SOURCE general purpose counter 0 clock source signal GPCTR1_SOURCE general purpose counter 1 clock source signal H h hour hex hexadecimal Hz hertz I interchannel delay amount of time that passes between sampling consecutive channels. The interchannel delay must be short enough to allow sampling of all the channels in the channel list, within the scan interval.
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Glossary M MB megabytes of memory min minimum min.
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Glossary S s seconds S samples SCANCLK scan clock signal scan interval controls how often a scan is initialized. The scan interval is regulated by STARTSCAN.
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Glossary V V volts VDC volts direct current VIH volts, input high VIL volts, input low Vin volts in VOH volts, output high VOL volts, output low Vref reference voltage W WFTRIG waveform generation trigger signal © National Instruments Corporation G-7 AT E Series User Manual
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Index Symbols differential connections for floating signal sources, 4-22 AISENSE signal analog input connections, 4-15 AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-8 AT-MIO-16E-10 and AT-MIO-16DE-10 (table), 4-10 AT-MIO-16XE-10 and AT-AI-16XE-10 (table), 4-12 AT-MIO-16XE-50 (table), 4-13 description (table), 4-5 AISENSE2 signal analog input connections, 4-15 AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-8 description (table), 4-5 amplifier characteristics AT-MIO-16E-1, AT-MIO-16E-2 and A
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Index AT-MIO-16E-10 and AT-MIO-16DE-10 dynamic characteristics, A-16 output characteristics, A-14 stability, A-16 transfer characteristics, A-15 voltage output, A-15 AT-MIO-16XE-10 dynamic characteristics, A-25 output characteristics, A-24 stability, A-25 transfer characteristics, A-24 voltage output, A-25 AT-MIO-16XE-50 dynamic characteristics, A-34 output characteristics, A-33 stability, A-34 transfer characteristics, A-33 voltage output, A-34 analog trigger block diagram, 3-15 specifications, AT-MIO-16E
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Index calibration adjusting for gain error, 5-3 external calibration, 5-2 loading calibration constants, 5-1 self-calibration, 5-2 charge injection, 3-12 clocks, board and RTSI, 3-20 commonly asked questions.
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Index description, 4-20 ground-referenced signal sources, 4-21 nonreferenced or floating signal sources, 4-22 single-ended connections, 4-24 floating signal sources (RSE), 4-25 grounded signal sources (NRSE), 4-25 when to use, 4-20 digital I/O common questions about, C-7 operation, 3-18 signal connections, 4-28 specifications AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3, A-8 AT-MIO-16E-10 and AT-MIO-16DE-10, A-16 AT-MIO-16XE-10 and AT-AI-16XE-10, A-25 AT-MIO-16XE-50, A-34 digital ports A, B, and C timing sp
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Index analog output reference selection, 3-13 AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-8 AT-MIO-16E-10 and AT-MIO-16DE-10 (table), 4-10 description (table), 4-5 EXTSTROBE* signal AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-8 AT-MIO-16E-10 and AT-MIO-16DE-10 (table), 4-10 AT-MIO-16XE-10 and AT-AI-16XE-10 (table), 4-12 AT-MIO-16XE-50 (table), 4-14 description (table), 4-6 timing connections, 4-30 AT-MIO-16XE-10 and AT-AI-16XE-10 (table), 4-12 AT-MIO-16XE-50 (table), 4-14 description
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Index G ground-referenced signal sources description, 4-17 differential connections, 4-21 single-ended connections (NRSE configuration), 4-25 general-purpose timing signal connections FREQ_OUT signal, 4-50 GPCTR0_GATE signal, 4-45 GPCTR0_OUT signal, 4-46 GPCTR0_SOURCE signal, 4-44 GPCTR0_UP_DOWN signal, 4-46 GPCTR1_GATE signal, 4-47 GPCTR1_OUT signal, 4-48 GPCTR1_SOURCE signal, 4-47 GPCTR1_UP_DOWN signal, 4-48 GPCTR0_GATE signal, 4-45 GPCTR0_OUT signal AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table),
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Index I AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-643-3, AT-MIO-16E-10, and AT-MIO-16DE-10, 3-7 actual range and measurement precision (table), 3-8 AT-MIO-16XE-10, AT-AI-16XE-10, and AT-MIO-16XE-50, 3-8 AT-MIO-16XE-10, AT-MIO-16XE-50 actual range and measurement precision (table), 3-9 mixing bipolar and unipolar channels (note), 3-9 selection considerations, 3-10 installation See also configuration common questions about, C-2 hardware installation, 2-1 unpacking AT E series boards, 1-6 instrument drivers, D-1 in
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Index PB<0..7> signal AT-MIO-16E-10 and AT-MIO-16DE-10 (table), 4-10 description (table), 4-6 PC<0..
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Index AT-MIO-16XE-10 and AT-AI-16XE-10 (table), 4-13 AT-MIO-16XE-50 (table), 4-14 description (table), 4-7 PFI9/GPCTR0_GATE signal AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 (table), 4-9 AT-MIO-16E-10 and AT-MIO-16DE-10 (table), 4-11 AT-MIO-16XE-10 and AT-AI-16XE-10 (table), 4-13 AT-MIO-16XE-50 (table), 4-14 description (table), 4-7 PFIs (programmable function inputs), 4-31 common questions about, C-9, C-10 overview, 4-30 signal routing, 3-18 PGIA (programmable gain instrumentation amplifier) common-mode
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Index AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3, A-10 AT-MIO-16E-10 and AT-MIO-16DE-10, A-18 AT-MIO-16XE-10 and AT-AI-16XE-10, A-27 AT-MIO-16XE-50, A-36 power requirement specifications AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3, A-10 AT-MIO-16E-10 and AT-MIO-16DE-10, A-19 AT-MIO-16XE-10 and AT-AI-16XE-10, A-28 pretriggered data acquisition, 4-32 professional services, D-1 programmable function inputs (PFIs). See PFIs (programmable function inputs) programmable gain instrumentation amplifier.
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Index UPDATE* signal, 4-42 WFTRIG signal, 4-41 types of signal sources, 4-17 floating, 4-17 ground-referenced, 4-17 single-ended connections description, 4-24 floating signal sources (RSE), 4-25 grounded signal sources (NRSE), 4-25 when to use, 4-24 SISOURCE signal, 4-39 software programming choices register-level programming, 1-4 software drivers, D-1 specifications AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 analog input, A-1 amplifier characteristics, A-3 dynamic characteristics, A-4 input characteristi
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Index triggers analog trigger, A-27 digital trigger, A-27 RTSI, A-27 AT-MIO-16XE-50 analog input amplifier characteristics, A-31 dynamic characteristics, A-32 input characteristics, A-30 transfer characteristics, A-31 analog output dynamic characteristics, A-34 output characteristics, A-33 stability, A-34 transfer characteristics, A-33 voltage output, A-34 bus interface, A-36 digital I/O, A-34 physical, A-37 timing I/O, A-35 triggers digital trigger, A-36 RTSI, A-36 stability analog input specifications AT
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Index GPCTR1_SOURCE signal, 4-47 GPCTR1_UP_DOWN signal, 4-48 programmable function input connections, 4-31 waveform generation timing connections UNISOURCE signal, 4-44 UPDATE* signal, 4-42 WFTRIG signal, 4-41 timing I/O specifications AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3, A-8 AT-MIO-16E-10 and AT-MIO-16DE-10, A-18 AT-MIO-16XE-10 and AT-AI-16XE-10, A-26 AT-MIO-16XE-50, A-35 timing signal routing board and RTSI clocks, 3-20 programmable function inputs, 3-20 RTSI triggers, 3-20 training customer, D-1
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Index V triggers analog, 3-14 block diagram, 3-15 RTSI triggers, 3-20 specifications AT-MIO-16E-1, AT-MIO-16E-2 and AT-MIO-64E-3 analog trigger, A-9 digital trigger, A-9 RTSI, A-10 AT-MIO-16E-10 and AT-MIO-16DE-10 digital trigger, A-18 RTSI, A-18 AT-MIO-16XE-10 and AT-AI-16XE-10 analog trigger, A-27 digital trigger, A-27 RTSI, A-27 AT-MIO-16XE-50 digital trigger, A-36 RTSI, A-36 troubleshooting resources, D-1 troubleshooting.