DAQ 653X User Manual High-Speed Digital I/O Devices for PCI, PXI ™, CompactPCI, AT, EISA, and PCMCIA Bus Systems 653X User Manual January 2001 Edition Part Number 321464C-01
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Important Information Warranty The AT-DIO-32HS, DAQCard-6533 for PCMCIA, PCI-6534, PCI-DIO-32HS, PXI-6533, and PXI-6534 devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
Compliance FCC/Canada Radio Frequency Interference Compliance* Determining FCC Class The Federal Communications Commission (FCC) has rules to protect wireless communications from interference. The FCC places digital electronics into two classes. These classes are known as Class A (for use in industrialcommercial locations only) or Class B (for use in residential or commercial locations). Depending on where it is operated, this product could be subject to restrictions in the FCC rules.
• • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. Canadian Department of Communications This Class B digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations. Cet appareil numérique de la classe B respecte toutes les exigences du Règlement sur le matériel brouilleur du Canada.
Conventions The following conventions appear in this manual: <> Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name—for example, DBIO<3..0>. » The » symbol leads you through nested menu items and dialog box options to a final action. The sequence File»Page Setup»Options directs you to pull down the File menu, select the Page Setup item, and select Options from the last dialog box.
Contents Chapter 1 Getting Started with Your 653X 653X Device Overview ..................................................................................................1-1 Control Lines ...................................................................................................1-1 What You Need to Get Started ......................................................................................1-2 Choosing Your Programming Software ....................................................................
Contents Choosing Whether or Not to Use a Programmable Delay .............................. 2-8 Choosing Continuous or Finite Data Transfer ................................................ 2-9 Finite Transfers................................................................................. 2-9 Continuous Input .............................................................................. 2-9 Continuous Output............................................................................
Contents External REQ Signal Source ...........................................................................3-2 Handshaking I/O Timing Diagrams...............................................................................3-4 Comparing the Different Handshaking Protocols ...........................................3-4 Using the Burst Protocol .................................................................................3-5 Using Asynchronous Protocols ..................................................
Getting Started with Your 653X 1 The 653X User Manual describes installing, configuring, setting up, and programming applications for your AT-DIO-32HS, DAQCard-6533 for PCMCIA, PCI-6534, PCI-DIO-32HS, PXI-6533, PXI-6534, or PCI/PXI-7030/6533 device. 653X Device Overview With 653X devices, you can use your computer or chassis as a digital I/O tester, logic analyzer, or system controller for laboratory testing, production testing, and industrial process monitoring and control.
Chapter 1 Getting Started with Your 653X Use Group 1 and 2 to: • Generate or receive digital patterns and waveforms timed by a TTL clock • Transfer data between two devices using one of six configurable handshaking protocols • Acquire a digital pattern every time the state of a data line changes What You Need to Get Started To begin using your 653X device, you need the following: ❑ One or more of the following devices: – AT-DIO-32HS – DAQCard-6533 for PCMCIA – PCI-6534 – PCI-DIO-32HS – PXI
Chapter 1 Getting Started with Your 653X Choosing Your Programming Software When programming your National Instruments measurement hardware, you can use either National Instruments application software or another application development environment (ADE). National Instruments Application Software LabVIEW and LabVIEW RT feature interactive graphics, a state-of-the-art user interface, and a powerful graphical programming language.
Chapter 1 Getting Started with Your 653X Using LabVIEW, Measurement Studio, or VirtualBench software greatly reduces the development time for your data acquisition and control application. NI-DAQ Driver Software The NI-DAQ driver software shipped with your 653X device has an extensive library of functions that you can call from your application programming environment. These functions allow you to use all the features of your 653X device.
Chapter 1 Getting Started with Your 653X To download a free copy of the most recent version of NI-DAQ, click Download Software at ni.com. Find NI-DAQ compatibility for your device using the following table: NI-DAQ Version Device Supported Windows Mac PCI-DIO-32HS Version 5.0 or later Version 6.1.0 or later AT-DIO-32HS Version 5.0 or later N/A PXI-6533 Version 5.1 or later Version 6.1.3 or later DAQCard-6533 for PCMCIA Version 5.1 or later Version 6.1.0 or later PXI-6534 Version 6.
Chapter 1 Getting Started with Your 653X Remove the device from the package and inspect the device for loose components or any sign of damage. Notify National Instruments if the device appears damaged in any way. Do not install a damaged device into your computer. Store your 653X device in the antistatic envelope when not in use. Installing Your 653X Device The following are general installation instructions.
Chapter 1 Getting Started with Your 653X Installing the PXI-6533, PXI-6534, or PXI-7030/6533 You can install a PXI-653X or PXI-7030/6533 device any available 5 V peripheral slot in your PXI or CompactPCI chassis. Your PXI device has connections to several reserved lines on the CompactPCI J2 connector. Before installing a PXI device in a CompactPCI system that uses J2 connector lines for purposes other than PXI, see Appendix C, Connecting Signals with Accessories. Note 1.
Chapter 1 Getting Started with Your 653X 5. Insert the AT-DIO-32HS into an AT (16-bit ISA) or EISA slot. It can be a tight fit, but do not force the device into place. 6. Screw the mounting bracket of the AT-DIO-32HS to the back panel rail of the computer. 7. Visually verify the installation. Make sure the device is not touching other boards or components and is fully inserted in the slot. 8. Replace the cover of the computer. 9. Plug in and turn on your computer.
Chapter 1 Getting Started with Your 653X To create a virtual channel, or to learn about other capabilities of MAX, read the MAX online help by selecting Help»Help Topics and select NI-DAQ from the menu. In Mac OS To view and test current resource allocation: 1. Open the NI-DAQ Configuration Utility. 2. Select the device you want to configure. 3. Click the Configure button. 4. Press the Test Resources button to test hardware resources.
2 Using Your 653X To begin using your 653X device, navigate this chapter in the following order: Tip 1. Choose the correct mode of operation to perform using the table below. 2. Follow the instructions for the application you want to perform. 3. Refer to pinout diagrams in Appendix C, Connecting Signals with Accessories, when you are ready to connect your devices and/or accessories. See the glossary for definitions to digital I/O terms used throughout this chapter.
Chapter 2 Using Your 653X Controlling and Monitoring Static Digital Lines—Unstrobed I/O This section explains how to control and monitor static digital lines through software-timed reads and writes to and from the digital lines of your 653X device. Configuring Digital Lines For unstrobed I/O, the direction of each of the 32 data lines is individually configurable.
Chapter 2 Using Your 653X Advantages of using the wired-OR driver include: • The ability to connect two or more wired-OR outputs together without damaging the drivers. • The ability to connect wired-OR outputs to open-collector drivers, to GND signals, or to switches connecting to GND signals, without damaging the drivers. • The ability to use wired-OR outputs bidirectionally.
Chapter 2 Using Your 653X Table 2-1. Port 4 Lines Direction Line Input Output (standard) I/O Pins 0 STOPTRIG 1 1 STOPTRIG 2 2 REQ 1 3 REQ 2 0 PCLK 1 1 PCLK 2 2 ACK 1 3 ACK 2 Connecting Signals Connect digital input signals to the I/O connector using the pinout diagrams, Figures C-1, 653X I/O Connector 68-Pin Assignments, and C-2, 68-to-50-Pin Adapter Pin Assignments. Creating a Program Using the following flowcharts as a guide, create a program to perform unstrobed I/O.
Chapter 2 No Only One Line? Yes DIG_Prt_Config DIG_Line_Config Read? Read? Yes Yes No DIG_In_prt DIG_Out_prt Done? Using Your 653X No DIG_In_Line No DIG_Out_Line Done? No Figure 2-1. Programming Unstrobed I/O in NI-DAQ s Yes Read from Digital Line VI Single Line? Write to Digital Line VI No Read from Digital Port VI Write to Digital Port VI Figure 2-2.
Chapter 2 Using Your 653X • LabVIEW—Use one of the top-level VIs: the Read From Digital Line VI to read from a digital port, and the Write to Digital Line VI to write to a digital port. The digital channel number is 4 and the port width is 4. If one of the control/timing lines is used or reserved and you are using the write or read port VIs, use the Line Mask parameter in the DIO Port Write VI to mask out the appropriate lines.
Chapter 2 Using Your 653X Deciding Which Handshaking Protocol to Use The 653X device supports several different handshaking protocols to communicate with your peripheral device. The protocol you select will determine the timing of the ACK and REQ signals. From the perspective of the 653X device, the peripheral device requests the transfer of data by signaling on the REQ line. The 653X device acknowledges it is ready to transfer data by signaling on the ACK line.
Chapter 2 Using Your 653X To set the direction of the PCLK signal: • NI-DAQ C interface—Set the ND_CLOCK_REVERSE_MODE to ND_ON in Set_DAQ_Device_Info. • LabVIEW—Set the Clock Reverse Mode attribute to ON in the DIO Parameter VI. For more information on LabVIEW VIs and NI-DAQ functions, consult the LabVIEW Help and the NI-DAQ Function Reference Help.
Chapter 2 Using Your 653X PCLK Period in ns PCLK Frequency in MHz 500 2 600 1.66 700 1.43 The state machine diagrams in Chapter 3, Timing Diagrams, show more precisely where this delay occurs in the handshaking sequence. Choosing Continuous or Finite Data Transfer You can transfer data indefinitely to/from computer memory or finitely by specifying the number of points you want to transfer.
Chapter 2 Using Your 653X You have the option to allow it to regenerate data that has already been outputted. As in continuous input, you specify the device to allow regeneration though the oldDataStop parameter in the DIG_DB_Config function and the Data Overwrite/Regenerate parameter in the Digital Buffer Control VI, called by the DIO Start VI.
Chapter 2 ACK Confirm REQ Ready I/O 653X Device Using Your 653X I/O Your Peripheral Device Figure 2-3. Connecting Signals If you are using the burst protocol, make the connection to the appropriate PCLK pin on the 653X device. Choosing the Startup Sequence To avoid invalid or missing data when the ACK and REQ lines change polarity to either active-high or active-low, start a transfer using one of the following methods: • Control the configuration and use an initialization order.
Chapter 2 Using Your 653X Controlling the startup sequence does not apply to buffered (block) operations. In a buffered operation, the NI-DAQ C interface configures and enables the 653X device at the same time, when you start the actual data transfer. For buffered operations, control the line polarities as a start-up method.
Chapter 2 Using Your 653X DIG_Grp_Config Yes DIG_Grp_Mode Read? No DIG_Block_In No Is the next half buffer ready? DIG_DB_HalfReady DIG_Block_Out Yes DIG_DB_Transfer Yes Continuous? DIG_DB_Config No No DIG_Block_In Yes Yes Read? Acquisition Complete? DIG_Block_Check No DIG_Block_Out No Acquisition Complete? Yes DIG_Block_Clear Figure 2-4.
Chapter 2 Using Your 653X DIG_Grp_Config DIG_Grp_Mode Input? No Yes DIG_Grp_Status Ready? DIG_Out_Grp No DIG_Grp_Status Yes Ready? No DIG_In_Grp Yes Done? No Done? No Yes Yes DIO_Grp_Config* DIO_Grp_Config *Clear Configuration Figure 2-5. Programming Unbuffered Handshaking I/O in NI-DAQ 653X User Manual 2-14 ni.
Chapter 2 Buffered Operation? Yes Using Your 653X DIO Config VI No Burst Mode? Digital Group Config VI No DIO Start VI Yes Digital Single Read VI Reverse PCLK Direction? Digital Group Config VI Finite Buffer? No No DIO Read VI Yes Yes Resets lines to default states. DIO Read VI Yes Done? No DIO Parameter VI Reverse PCLK Direction? Yes DIO Parameter VI No DIO Clear VI Figure 2-6.
Chapter 2 Using Your 653X Buffered Operation? Yes DIO Config VI No DIO Write VI Digital Group Config VI Digital Single Write VI Digital Group Config VI Resets the lines to default states. Burst Mode? No DIO Start VI Yes Reverse PCLK Direction? Finite Buffer? No No DIO Write VI Yes Yes DIO Wait VI Yes Done? No DIO Parameter VI Reverse PCLK Direction? Yes DIO Parameter VI No DIO Clear VI Figure 2-7.
Chapter 2 Using Your 653X The preloading process will cause a small delay between the start command in software and the actual start of data transfer. If this is a concern, you may disable the preloading by calling the following function/VI before the software start command: • NI-DAQ C interface—In the Set_DAQ_Device_Info function, set the ND_FIFO_Transfer_COUNT to ND_NONE. • LabVIEW—In the DIO Parameter VI, set the Scarabs Preload Enable attribute to OFF.
Chapter 2 Using Your 653X Deciding Transfer Direction You can choose to send data from your 653X device to the peripheral device (output), or from the peripheral device to your 653X device (input). Choosing an Internal or External REQ Source In pattern I/O, the 653X device acquires/generates data on every falling or rising edge (programmable) of the REQ signal. The REQ signal can be generated internally or based on the clock of a peripheral device.
Chapter 2 Using Your 653X For example, if you specify a timebase of 100 kHz and a timebase divisor of 25, the resulting acquisition/generation rate would be 4 kHz. 100 kHz/25 = 4 kHz. If you are using a version of NI-DAQ prior to version 6.8, the minimum value for timebase divisor is 2. Note In LabVIEW, you can specify the transfer rate directly using the Digital Clock Config VI (called by the DIO Start VI). The software will choose the closest transfer rate by selecting the frequency and divisor.
Chapter 2 Using Your 653X data is in the buffer, transfer stops. If the stop trigger arrives before all the pretrigger data is acquired, NI-DAQ returns an error. STOPTRIG REQ Pretrigger Data Posttrigger Data Figure 2-9.
Chapter 2 • Using Your 653X The polarity (whether to trigger on data that matches or mismatches the specified pattern) For example, if you want to start acquisition when the two least significant bits of your data are 1 and 0, you would specify your trigger parameters to match those in Figure 2-11. Pattern to Detect X X X X X X 1 0 Mask 0 0 0 0 0 0 1 1 Polarity Postive: Search for Match Figure 2-11.
Chapter 2 Using Your 653X the Data Overwrite/Regenerate parameter in the Digital Buffer Control VI, called by the DIO Start VI. Continuous Output Similarly, with continuous output, the 653X device continuously reads data from computer memory. As the device retrieves data from the buffer, call the DIG_DB_Transfer function or the DIO Write VI to write the data.
Chapter 2 Using Your 653X Monitoring Data Transfer To monitor your data transfer once data transfer starts: • Transfer Direction Input NI-DAQ C interface—Call DIG_Block_Check to monitor finite data transfer. For continuous transfers, use Get_DAQ_Device_Info to obtain the cumulative transfer count (DIG_Block_Check does not return the number of buffer iterations completed).
Chapter 2 Using Your 653X If you are using external start and/or stop triggers, connect to the appropriate pins—start trigger (ACK/STARTTRIG) and/or stop trigger (STOPTRIG). Creating a Program Using the following flowcharts as a guide, create a program to perform pattern I/O. Figures 2-13 and 2-14 display flowcharts for C programming using NI-DAQ, while Figure 2-14 shows a LabVIEW programming flowchart.
Chapter 2 Using Your 653X No DIG_Block_In Yes Read? Is the next half buffer ready? DIG_DB_HalfReady No DIG_Block_Out Yes DIG_Grp_Config DIG_DB_Transfer DIG_Block_PG_Config Acquisition Complete? No No Trigger? DIG_DB_Config Yes Yes DIG_Trigger_Config DIG_Block_Clear Figure 2-13.
Chapter 2 Using Your 653X If you are performing a finite pattern output operation, you can call the DIO Wait VI instead of the DIO Write VI after the DIO Start VI. For more information about these VIs, see the LabVIEW Help. Note By default, for output buffered transfers the 6534 device will preload the on board memory with data before starting the output operation. This is done to eliminate or reduce the impact of the PCI bus bandwidth limitations and increase the overall transfer rate.
Chapter 2 Using Your 653X Table 2-4. Port and Timing Controller Combinations (Continued) Transfer Width 16 bits 32 bits Possible Port Combinations Timing Controllers That Can Be Used Port 0, Port 1 Group 1 Port 2, Port 3 Group 2 Port 0, Port 1, Port 2, Port 3 Group 1 Deciding Which Lines You Want to Monitor You need to specify which of the lines in your acquisition you want to monitor for changes.
Chapter 2 Using Your 653X The three types of trigger signals available are the start trigger, the stop trigger, or the start and stop trigger. Start Trigger A start trigger is a trigger that initiates a pattern I/O upon receipt of a hardware trigger on the ACK (STARTTRIG) pin. ACK (STARTTRIG) REQ Posttrigger Data Figure 2-16. Starting Data Transfer Using a Trigger Stop Trigger When using a stop trigger, transfer starts upon a software command.
Chapter 2 Using Your 653X ACK (STARTTRIG) STOPTRIG REQ Pretrigger Data Posttrigger Data Figure 2-18. Using a Start and Stop Trigger Pattern-Matching Trigger Instead of using an external signal on the start/stop trigger pins on the I/O connector, you may start or stop (not both) an operation once a user-specified digital pattern is matched.
Chapter 2 Using Your 653X Value to Detect X X X X X X 1 0 Pattern 0 0 0 0 0 0 1 0 Mask 0 0 0 0 0 0 1 1 Polarity Postive: Search for Match Figure 2-19. Pattern-Detection Trigger Example To prevent a transient data value during line switching from falsely causing a match, set a valid pattern for at least 60 ns to guarantee detection. In addition, keep glitches to less than 20 ns to guarantee rejection.
Chapter 2 Using Your 653X Choosing DMA or Interrupt Transfers When using DMA (by default), the 6534 device transfers data in 32-byte blocks and the 6533 device transfers data in 4 byte blocks. Therefore, at any time during a continuous operation, there may be up to 31 bytes (or 3 bytes for 6533 devices) of data in an internal device FIFO. You can use interrupt driven transfers if you need to retrieve data immediately as it is acquired.
Chapter 2 Using Your 653X DIG_Grp_Config No DIG_Block_In Is the next half buffer ready? DIG_DB_HalfReady DIG_Block_PG_Config DIG_Trigger_Config Yes DIG_DB_Transfer DIG_DB_Config Specify data mask here No Acquisition Complete? Yes DIG_Block_Clear Figure 2-20. Programming Change Detection (Continuous) in NI-DAQ DIG_Grp_Config DIG_Block_Clear DIG_Block_PG_Config Yes DIG_Trigger_Config DIG_Block_In DIG_Block_Check Acquisition Complete? No Specify data mask here Figure 2-21.
Chapter 2 Using Your 653X DIO Config VI Trigger Config VI Specify data mask here DIO Start VI DIO Read VI Done? No Yes DIO Clear VI Figure 2-22.
3 Timing Diagrams This chapter contains timing diagrams for the handshaking and pattern I/O modes. You can use these diagrams to get a detailed understanding about what happens in hardware when using these modes. Note All timing diagrams are in nanoseconds. Pattern I/O Timing Diagrams Use pattern I/O to transfer data at a timed interval upon the rising or falling edge of the REQ signal. The REQ signal can be generated internally by the 653X device or supplied externally via the I/O connector.
Chapter 3 Timing Diagrams Programmable = Interval x Timebase tc dtp will remove bar Programmable = One Timebase tw REQ if Active High REQ if Active Low Data Valid (Output Mode) tp 30 ns Max Data Valid (Input Mode) tsu th 30 ns Min 0 ns Min Parameter t tw* tp tsu th * c Description Cycle time Width of pulse Propagation time to valid output data Setup time Hold time * The 6534 devices will transfer data at 20 MHz when the cycle time (tc) for REQ pulse is 50 ns and width of the REQ pulse (tw) is
Chapter 3 Timing Diagrams during, or after the REQ edge. If STARTRIG is asserted too close to the REQ edge, it may not be recognized until the next REQ edge. To avoid this uncertainty, you can observe an optional setup time of 15 ns, in other words, assert STARTRIG at least 15 ns before the start of the REQ pulse. The STARTRIG signal is synchronized to the REQ edge using a flip-flop. Because of this synchronization flip-flop, there is a one REQ-pulse delay after STARTRIG before the data capture begins.
Chapter 3 Timing Diagrams Handshaking I/O Timing Diagrams This section compares of the handshaking I/O protocols and includes timing diagrams for each: • Handshaking sequence for input operation • State machine for input operation • Timing specification for input operation • Handshaking sequence for output operation • State machine for output operation • Timing specification for output operation Comparing the Different Handshaking Protocols For an overview of all handshaking protocols supporte
Chapter 3 Timing Diagrams Table 3-1. Handshaking Protocol Characteristics (Continued) REQ/ACK Protocol Which REQ Edge Requests Transfer Polarity Where the Programmable Delay Is Located Complementary Protocol(s) Synchronous Protocol Burst Programmable Neither (level REQ) Clock speed Burst * Asynchronous protocols can compensate automatically to cable length, yet for synchronous protocols, you need to select an appropriate speed for your cable when configuring your device.
Chapter 3 Timing Diagrams PCLK ACK REQ Data In Valid D1 D2 D3 D5 D4 = data transfer occurs Figure 3-3. Burst Transfer Example (Input) PCLK ACK REQ Data Out Valid D1 D2 D3 D4 D5 = data transfer occurs Figure 3-4. Burst Transfer Example (Output) Since data is transferred only when both the 653X device and the peripheral device are ready (and thus ACK and REQ are asserted), it is not reasonable to expect data to arrive at consistent intervals.
Chapter 3 Timing Diagrams The 653X device can either drive an output clock signal onto the PCLK line or receive an input clock signal from the PCLK line. By default, the PCLK line is set for input during output transfers, and set for output during input transfers. If you are using long cables, slow down the PCLK clock signal to compensate for the decrease in data setup time.
Chapter 3 Timing Diagrams tpc tpw PCLK tah tpa ACK trh trs REQ tdis tdih Data In Valid Parameter Description Minimum Maximum Input Parameters trs Setup time from REQ valid to PCLK 12 — trh tdis tdih Hold time from PCLK to REQ invalid 0 — Setup time from input data valid to PCLK 4 — Hold time from PCLK to input data invalid 6 — 50 7001 tpc/2 – 5 tpc/2 + 5 PCLK to ACK valid — 18 Hold time from PCLK to ACK invalid 3 — Output Parameters tpc tpw tpa tah PCLK cycle time PCLK
Chapter 3 Timing Diagrams tpc tpw tpl PCLK tah tpa ACK trh trs REQ tpdo tdoh Data Out Valid Parameter Description Minimum Maximum Input Parameters tpc tpw PCLK cycle time 50 — PCLK high pulse duration 20 — tpl PCLK low pulse duration 20 — trs Setup time from REQ valid to PCLK falling edge 1 — trh Hold time from PCLK to REQ invalid 0 — PCLK to ACK valid — 22 Hold time from PCLK to ACK invalid 3 — PCLK to output data valid — 28 Hold time from PCLK to output data inv
Chapter 3 Timing Diagrams tpc tpw tpl PCLK tah tpa ACK trs trh tdis tdih REQ Data In Valid Parameter Description Minimum Maximum PCLK cycle time 50 — PCLK high pulse duration 20 — PCLK low pulse duration Setup time from REQ valid to PCLK falling edge 20 — 1 — trh tdis Hold time from PCLK to REQ invalid Setup time from input data valid to PCLK falling edge 0 — 0 — tdih Hold time from PCLK to input data valid 0 — PCLK to ACK valid — 22 Hold time from PCLK to ACK invalid
Chapter 3 Timing Diagrams tpc tpw PCLK tah tpa ACK trh trs REQ tdoh tpdo Data Out Valid Parameter Description Minimum Maximum Setup time from REQ valid to PCLK 12 — Hold time from PCLK to REQ invalid 0 — 50 7001 tpc/2 – 5 tpc/2 + 5 PCLK to ACK valid — 18 Hold time from PCLK to ACK invalid 3 — PCLK to output data valid — 28 Input Parameters trs trh Output Parameters tpc tpw tpa tah tpdo tdoh PCLK cycle time Hold time from PCLK to output data invalid 4 — tdis tdih Setup
Chapter 3 Timing Diagrams Using Asynchronous Protocols All handshaking protocols except burst are asychronous. The asynchronous protocols include 8255 emulation, level ACK, leading edge, trailing edge, and long pulse. When using these protocols, you have the following options: • You can change the polarity of the ACK and REQ signals (except for 8255-emulation). The diagrams in this chapter show active-high signals.
Chapter 3 Timing Diagrams 653X device terminology differs from 8255 terminology. • Input—The REQ line carries the 8255 STB (Strobe) input signal, and the 653X device ACK line carries the 8255 IBF (Input Buffer Full) output signal. • Output—The REQ line carries the 8255 ACK input signal, and the 653X device ACK line carries the 8255 OBF (Output Buffer Full) output signal. 3 1 ACK 5 REQ 2 4 ACK and REQ are shown as active low. Steps 1-5 are repeated for each transfer.
Chapter 3 Timing Diagrams When REQ Unasserted, Latch Input Data Wait Programmable For Delay REQ Clear ACK When REQ Asserted Wait For Space Send ACK When 6533 Device has space for data, input data. Wait For REQ Initial State: ACK Set Figure 3-10. 8255 Emulation Input State Machine 653X User Manual 3-14 ni.
Chapter 3 Timing Diagrams 4 1 ACK 6 3 REQ 2 5 ACK and REQ are shown as active low. Steps 1-6 are repeated for each transfer. Reference Point Action Steps 1 When the 653X device has data to output, it asserts the ACK signal, then waits for the peripheral device to assert REQ to indicate it is ready to accept data 2 The peripheral device asserts a REQ signal to accept the data.
Chapter 3 Timing Diagrams Initial State: ACK Cleared Wait For REQ When REQ Unasserted Wait For Data Programmable Delay When 6533 Device has data to output, output data. Output Data, Then Send ACK Clear ACK When REQ Asserted Wait For REQ Figure 3-12. 8255 Emulation Output State Machine 653X User Manual 3-16 ni.
Chapter 3 Timing Diagrams ta*r tr*a taa* ACK tr*r trr* REQ tdir trdi Data In Valid tdoa* trdo Data Out Valid ACK and REQ are shown as active low Parameter Description Minimum Maximum REQ low duration 75 — REQ high duration 75 — ACK falling edge to REQ rising edge 0 — Input data valid to REQ rising edge 0 — REQ rising edge to input data invalid 10 — ACK high duration 100 — REQ falling edge to ACK rising edge — 150 Output data valid to ACK falling edge 25 — REQ rising
Chapter 3 Timing Diagrams Using the Level-ACK Protocol In level-ACK protocol, the 653X device asserts the ACK signal when ready for a transfer and holds the ACK signal level until an active-going edge occurs on the REQ line. After the REQ edge occurs, the 653X device deasserts the ACK signal until the device is ready for another transfer. 1 3 4 ACK REQ 2 Initial State ACK and REQ are shown as active high. Steps 1-4 are repeated for each transfer.
Chapter 3 Timing Diagrams Initial State: ACK Cleared Wait For REQ When REQ Asserted Clear ACK Wait For Space Programmable Delay When 6533 Device has space for data, input data.* Programmable Delay When REQ Unasserted Wait For REQ Send ACK * With REQ-edge latching enabled, the data input is from the last active-going REQ edge. Figure 3-15.
Chapter 3 Timing Diagrams taa* ACK tra* tar tr*r trr* REQ tdir(1) Input Data Valid (REQ-edge latching) trdi tdir(2) tadi Input Data Valid (REQ-edge latching disabled) ACK and REQ are shown as active high Parameter Description Minimum Maximum REQ pulse width 75 — REQ inactive duration 75 — ACK to next REQ 0 — Input data setup to REQ active (with REQ-edge latching) 0 — Input data hold from REQ active (with REQ-edge latching) 10 — tdir(2) Input data setup to REQ (with REQ-edge la
Chapter 3 Timing Diagrams With REQ edge latching enabled (default), the REQ edge determines when data will be latched. Input data valid has to be held before the active going REQ edge a minimum of trdi ns. With REQ edge disabled, input data valid has to be held tadi after the next active going ACK signal edge is asserted. Note Initial State 1 3 4 ACK REQ 2 Reference Point Initial State ACK and REQ are shown as active high. Steps 1-4 are repeated for each transfer. Action Steps ACK is deasserted.
Chapter 3 Timing Diagrams Initial State: ACK Cleared When REQ Asserted Wait For REQ Clear ACK Wait For Data Programmable Delay When 6533 Device has data to output, output data.* Programmable Delay When REQ Unasserted Wait For REQ Send ACK * With REQ-edge latching enabled, the data output is delayed until the next inactive-going REQ edge. Figure 3-18. Level ACK Output State Machine 653X User Manual 3-22 ni.
Chapter 3 Timing Diagrams taa* ACK tar tr*r trr* REQ tra* Output Data Valid (REQ-edge latching) tdoa tr*do trdo Output Data Valid (REQ-edge latching disabled) ACK and REQ are shown as active high Parameter Description Minimum Maximum REQ pulse width 75 — REQ inactive duration 75 — ACK to next REQ 0 — Input Parameters trr* tr*r tar Output Parameters 1 taa* tra* ACK pulse width 225 — REQ to ACK inactive 100 200 tr*do REQ inactive to new output data (with REQ-edge latching)
Chapter 3 Timing Diagrams Using Protocols Based on Signal Edges The 653X device can communicate via pulses on the ACK and REQ lines. The three edge protocols are: • Trailing-edge protocol—The trailing edge of the ACK or REQ pulse indicates that the 653X device or peripheral device is ready for a transfer.
Chapter 3 Timing Diagrams Using the Trailing-Edge Protocol ACK 1 3 Data Latched REQ 2 Initial State ACK and REQ are shown as active high. Steps 1-2 are repeated for each transfer. Reference Point Action Steps Initial State ACK is deasserted. The 653X device waits for the peripheral device to pulse REQ to indicate it has data. 1 The 653X device sends an ACK pulse of programmable width when ready to receive data.
Chapter 3 Timing Diagrams taa* ta*r* ACK tr*r trr* REQ tr*di tdir* Input Data Valid (REQ-edge latching) tdir Input Data Valid (REQ-edge latching disabled) tadi ACK and REQ are shown as active high Parameter Description Minimum Maximum Input Parameters trr* tr*r tdir* REQ pulse width 75 — REQ inactive duration 75 — Input data setup to REQ inactive (with REQ-edge latching) 0 — tr*di Input data hold from REQ inactive (with REQ-edge latching) 10 — tdir Input data setup to REQ (wi
Chapter 3 Timing Diagrams Initial State ACK 1 REQ 2 ACK and REQ are shown as active high. Steps 1-2 are repeated for each transfer. Reference Point Initial State Action Steps ACK is deasserted. 1 The 653X device sends an ACK pulse of programmable width. This indicates new, valid output data. 2 The peripheral device responds with a REQ pulse. The trailing edge of the REQ pulse deasserts the ACK signal and requests additional data. Figure 3-23.
Chapter 3 Timing Diagrams taa* ta*r* ACK tr*r trr* REQ tr*do(1) Output Data Valid (REQ-edge latching) tdoa tr*do(2) Output Data Valid (REQ-edge latching disabled) ACK and REQ are shown as active high Parameter Description Minimum Maximum Input Parameters trr* tr*r REQ pulse width 75 — REQ inactive duration 75 — ta*r* ACK inactive to next REQ inactive 0 — 2251 2752 Output Parameters taa* ACK pulse width tr*do(1) REQ inactive to new output data (with REQ-edge latching) 0 50
Chapter 3 Timing Diagrams Using the Leading-Edge Protocol 1 4 3 ACK REQ Initial State 2 ACK and REQ are shown as active high. Steps 1-3 are repeated for each transfer. Reference Point Action Steps Initial State ACK is deasserted. The 653X device waits for an active REQ to indicate that the peripheral device is ready. The peripheral device may optionally drive the first data at this time.
Chapter 3 Timing Diagrams Initial State: ACK Cleared Wait For REQ When REQ Asserted Wait For Space Programmable Delay When 6533 Device has space for data, input data.* Clear ACK Pulse When REQ Unasserted Wait For REQ Send ACK Pulse Programmable Delay * With REQ-edge latching enabled, the data input is from the last active-going REQ edge. Figure 3-27. Leading Edge Input State Machine 653X User Manual 3-30 ni.
Chapter 3 Timing Diagrams taa* ACK tr*a* tar tr*r trr* REQ tdir(1) Input Data Valid (REQ-edge latching) trdi tdir(2) tadi Input Data Valid (REQ-edge latching disabled) ACK and REQ are shown as active high Parameter Description Minimum Maximum REQ pulse width 75 — REQ inactive duration 75 — ACK to next REQ 0 — Input data setup to REQ active (with REQ-edge latching) 0 — Input data hold from REQ active (with REQ-edge latching) 10 — tdir(2) Input data setup to REQ (with REQ-edge l
Chapter 3 Timing Diagrams With REQ edge latching enabled (default), the REQ edge determines when data will be latched. Input data valid has to be held before an active going REQ edge a minimum of trdi ns. With REQ edge disabled, it has to be held tadi after the next active-going ACK signal edge occurs. Note Initial State 1 3 ACK REQ 2 ACK and REQ are shown as active high. Steps 1-3 are repeated for each transfer. Reference Point Initial State Action Steps ACK is deasserted.
Chapter 3 Timing Diagrams Initial State: ACK Cleared Wait For REQ When REQ Asserted Wait For Data Programmable Delay When 653X Device has data to output, output data.* Clear ACK Pulse When REQ Unasserted Wait For REQ Send ACK Pulse Programmable Delay * With REQ-edge latching enabled, the data output is delayed until the next inactive-going REQ edge. Figure 3-30.
Chapter 3 Timing Diagrams taa* ACK tr*a* tar tr*r trr* REQ trdo Output Data Valid (REQ-edge latching disabled) tdoa tr*do Output Data Valid (REQ-edge latching) ACK and REQ are shown as active high Parameter Description Minimum Maximum REQ pulse width 75 — REQ inactive duration 75 — ACK to next REQ 0 — Input Parameters trr* tr*r tar Output Parameters 1 taa* tr*a* ACK pulse width 125 — REQ inactive to ACK inactive 150 — tr*do REQ inactive to new output data (with REQ-edge latc
Chapter 3 Timing Diagrams Using the Long-Pulse Protocol 1 ACK 2 4 REQ Initial State 3 ACK and REQ are shown as active high. Steps 1-4 are repeated for each transfer. Reference Point Initial State Action Steps ACK is deasserted. The 653X device waits for an active REQ to indicate that the peripheral device is ready. The peripheral device may optionally drive the first data at this time.
Chapter 3 Timing Diagrams Initial State: ACK Cleared Wait For REQ When REQ Asserted Wait For Space Programmable Delay Send ACK Pulse Clear ACK Pulse When REQ Unasserted When 6533 Device has space for data, input data.* Programmable Delay Wait For REQ * With REQ-edge latching enabled, the data input is from the last active-going REQ edge. Figure 3-33. Long Pulse Input State Machine 653X User Manual 3-36 ni.
Chapter 3 Timing Diagrams taa* ACK tr*a* tar tr*r trr* REQ tdir(1) Input Data Valid (REQ-edge latching) trdi tdir(2) tadi Input Data Valid (REQ-edge latching disabled) ACK and REQ are shown as active high Parameter Description Minimum Maximum Input Parameters trr* tr*r REQ pulse width 75 — REQ inactive duration 75 — tar ACK to next REQ 0 — Input data setup to REQ active (with REQ-edge latching) 0 — Input data hold from REQ active (with REQ-edge latching) 10 — tdir(2) Input
Chapter 3 Timing Diagrams With REQ edge latching enabled (default) REQ edge determines when data will be latched. Input data valid has to be held before active going REQ edge a minimum of trdi ns. With REQ edge disabled, it has to be held tadi after the next active going ACK signal edge occurs. Note Initial State 1 ACK 2 * REQ 3 ACK and REQ are shown as active high. Steps 1-3 are repeated for each transfer.
Chapter 3 Timing Diagrams Initial State: ACK Cleared Wait For REQ When REQ Asserted Wait For Data Programmable Delay Send ACK Pulse Clear ACK Pulse When REQ Unasserted When 6533 Device has data to output, output data.* Programmable Delay Wait For REQ * With REQ-edge latching enabled, the data output is delayed until the next inactive-going REQ edge. Figure 3-36.
Chapter 3 Timing Diagrams taa* ACK tar tr*r trr* REQ tdoa trdo Output Data Valid (REQ-edge latching disabled) tr*do Output Data Valid (REQ-edge latching) ACK and REQ are shown as active high Parameter Description Minimum Maximum Input Parameters trr* tr*r REQ pulse width 75 — REQ inactive duration 75 — tar ACK to next REQ 0 — 1251 — 0 50 0 — 25 — Output Parameters taa* ACK pulse width REQ inactive to new output data (with REQ-edge latching) REQ to new output data (with RE
A Specifications This appendix lists features and specifications for your 653X devices and the PCI/PXI-7030/6533 device. Specifications are typical at 25 °C unless otherwise noted. Digital I/O Number of channels ............................... 32 input/output; 4 dedicated output and control; 4 dedicated input and status Compatibility ......................................... TTL/CMOS (standard or wired-OR) Hysteresis ...............................................
Appendix A Specifications Level (Continued) Min Max — — 200 µA 1.4 mA — 4 µA Input high current for CPULL/DPULL (Vin = 2.4 V) — 140 µA Output low voltage (IOL = 24 mA) — 0.4 V 2.4 V — Input high current for control lines (Vin = 2.4 V) CPULL high CPULL low Input low current for CPULL/DPULL (Vin = 0.4 V) Output high voltage* (IOH = 24 mA) * When configured as standard outputs. Drivers configured as wired-OR outputs are in the high-impedance state when logically high.
Appendix A Specifications Pattern I/O Direction................................................. Input or output Maximum sample rate (internally timed, for small transfers1)..................... 20 MHz Minimum sample rate (internal clock rate) ................................ 1 S/10 min. Change Detection Change-detection resolution .................. 150 ns Triggers Start and Stop Triggers Compatibility ......................................... TTL/CMOS Trigger types ....................................
Appendix A Specifications Power Requirement +5 VDC (±5%) (with light output load) ...........................500 mA Power Available at I/O Connector PCI-DIO-32HS, PXI-6533, AT-DIO-32HS, PCI-6534, and PXI-6534 ........................+4.65 to +5.25 VDC at 1 A DAQCard-6533 for PCMCIA ................+4.65 to +5.25 VDC at 250 mA Physical Dimensions, not including connectors DAQCard-6533 for PCMCIA .........3.4 by 2.1 in. AT-DIO-32HS/PCI-653X................6.9 by 4.2 in. PXI-653X...........................
Appendix A Specifications Nonoperational random vibration (PXI only) .............................................. 5 to 500 Hz, 2.5 grms, 3 axes Random vibration profiles were developed in accordance with MIL-T-28800E and MIL-STD-810E Method 514. Test levels exceed those recommended in MIL-STD-810E for Category 1 (Basic Transportation, Figures 514.4-1 through 514.4-3).
B Using PXI with CompactPCI You can use your PXI-653X device as a plug-in device in a standard CompactPCI chassis, but you will not be able to access PXI-specific functions, such as RTSI bus features detailed in the PXI Specification, rev. 1.0. The CompactPCI specification permits vendors to develop sub-buses that coexist with the basic PCI interface on the CompactPCI bus.
C Connecting Signals with Accessories This appendix describes how to connect signals to your 653X device. Use the first part of the appendix to acquaint yourself with the device control signals. Then go to appropriate pinout diagrams (68 or 50-pin), which display the layout of pin locations. Control Signals Use the four control signals to regulate/control the timing of your data transfer when using the handshaking and pattern I/O modes.
Appendix C Connecting Signals with Accessories Making 68-Pin Signal Connections Caution Do not make connections that exceed any of the maximum input or output ratings on the 653X, listed in Appendix A, Specifications. This includes connecting any power signals to ground and vice versa. Doing so may damage your device and your computer. National Instruments is not liable for any damages resulting from these types of signal connections.
Appendix C Connecting Signals with Accessories In Figure C-1, the * indicates that you can reverse the pin assignments of the ACK1 (STARTTIG1) and REQ1 pins, or the ACK2 (STARTTIG2) and REQ2 pins. To do this, set the ACK-REQ Exchange attribute to ON in the DIO Parameter VI in LabVIEW or in set_DAQ_Device_Info in NI-DAQ. This allows you to perform handshaking I/O between two 653X devices using an SH-68-68-D1 cable.
Appendix C Connecting Signals with Accessories Table C-3. Signal Descriptions Pins 2, 9 Signal Name REQ<1..2> Signal Type Control Signal Description Based on Mode Used Group 1 and group 2 request lines Handshaking I/O—Request. A control line that indicates whether the peripheral device is ready to transfer data. Pattern I/O—REQ carries timing pulses either to or from the peripheral device. These strobe signals are comparable to the CONVERT* or UPDATE* signals of an analog DAQ device.
Appendix C Connecting Signals with Accessories Table C-3. Signal Descriptions (Continued) Pins Signal Name 23, 57–58, 25–26, 60–61, 28 DIOC<0..7> 29, 31–32, 34, 63–64, 66–67 DIOD<0..7> 40 CPULL Signal Type Data Signal Description Based on Mode Used Port C bidirectional data lines Port C is referred to as port number 2 in software. DIOC7 is the MSB; DIOC0 is the LSB. Data Port D bidirectional data lines Port D is referred to as port number 3 in software. DIOD7 is the MSB; DIOD0 is the LSB.
Appendix C Connecting Signals with Accessories Making 50-Pin Signal Connections DIOD1 DIOD3 DIOD6 DIOD2 DIOC5 DIOC3 DIOC2 DIOC6 GND GND GND GND GND ACK1 STOPTRIG1 (IN1) PCLK1 (OUT1) REQ1 DIOA4 DIOA0 DIOA1 DIOA7 DIOB5 DIOB7 DIOB0 DIOB4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 DIOD4 DIOD0 DIOD7 DIOD5 DIOC7 DIOC1 DIOC0 DIOC4 ACK2 STOPTRIG2 (IN2) PCLK2 (OUT2) REQ2 GND GND GND GND GND DIOA6 DIOA2 DIOA3 DIOA5
Appendix C Connecting Signals with Accessories Table C-4.
D Hardware Considerations This appendix covers several hardware considerations for your 653X device. As an advanced user, you can use these sections to understand how the hardware works in your 653X device.
Hardware Considerations Data Lines (16) Internal FIFOs Data Latches and Drivers DMA/ Interrupt Requests DAQ-DIO Handshaking and Control Counters and Timers Clock Selection Request Processing PCMCIA I/O Channel Bus Interface PCMCIA Interface Data Lines (32) Control Lines (8) I/O Connector Appendix D 20 MHz Oscillator Figure D-2. DAQCard-6533 for PCMCIA Block Diagram 653X User Manual D-2 ni.
Data Lines (32) Internal FIFOs Data Latches and Drivers DMA/ Interrupt Requests DAQ-DIO Handshaking and Control Counters and Timers Clock Selection Request Processing Bus Interface PCI I/O Channel MITE PCI Interface EEPROM 20 MHz Oscillator Hardware Considerations Data Lines (32) Control Lines (8) I/O Connector Appendix D RTSI Interface RTSI/PXI Trigger Bus Figure D-3.
Appendix D Hardware Considerations SCARAB Memory 0 PCI I/O Channel MITE PCI Interface MITE Interface Bus Interface Bus Interface Internal FIFOs Data Latches and Drives DMA/IRQ DAQ-DIO Handshaking and Control Counter and Timers Clock Selection Request Processing DMA/IRQ FPGA Data Lines (32) Handshaking and Control SCARAB Interface RTSI Interface Control Lines (8) I/O Connector SCARAB Interface 20 MHz Oscillator EEPROM SCARAB Memory 1 For PXI-6534 Only PLL 10 MHz PXI Clock RTSI/PXI T
Appendix D Hardware Considerations Power-On State When the computer is first turned on, all lines are configured for input and in the high-impedance state. By default, the data and control lines in the 653X device are pulled down, even if the CPULL and DPULL are disconnected. You can select the biasing of control and data signals using the CPULL and DPULL lines: • CPULL line—For control lines, it is a user-configurable 2.2 kΩ internal resistor.
Appendix D Hardware Considerations Table D-1. 653X Power Ratings (Continued) Device Power Rating PCI-6534 +4.65 to +5.25 VDC at 1 A PXI-6534 +4.65 to 5.25 VDC at 250 mA You can connect the +5 V pin to the CPULL and DPULL pins to control the bias of the 653X device control and data lines, as described in the Power-On State section earlier in this chapter.
Appendix D Hardware Considerations Using the Schottky-Diode Termination Scheme You can terminate a cable that acts as a uniform transmission line in several ways. If your 653X device is driving a cable, use the following termination scheme: connect two Schottky diodes to each line, one to +5 VDC and the other to ground. This termination will clamp any overshoot or undershoot that occurs. The +5 V and ground connections should be low-impedance connections.
Appendix D Hardware Considerations 653X Device Peripheral Device +5 V Data Control Line (Input) +5 V Data Control Line (Output) +5 V Data Control Line (Output) Figure D-5. Transmission Line Terminations Note Run the signal lines through special metal conduits to protect them from magnetic fields caused by electric motors, welding equipment, breakers, or transformers. If you are using the Schottky diode termination scheme, you do not need to know the exact input, output, or cable impedances.
Appendix D Hardware Considerations There is no specific cutoff frequency at which termination becomes necessary. A purely resistive termination scheme is not recommended because of the current drawn by the termination resistors. For example, a 90 Ω terminating resistor works well to dampen reflections, but sinks 27 mA even at 2.4 V. The DIO-32HS is only rated to sink 24 mA.
Appendix D Hardware Considerations RTSI and PXI Trigger Bus Interfaces You can use the seven bidirectional RTSI lines on the RTSI bus to share signals between devices. Use the RTSI bus interface to synchronize multiple cards or change control signals with multiple devices. The PCI-6534, PCI-DIO-32HS and AT-DIO-32HS each contain a RTSI connector and an interface to the National Instruments RTSI bus. The RTSI bus provides seven trigger lines and a system clock line.
Appendix D Hardware Considerations RTSI and PXI Bus Triggers The seven RTSI lines on the RTSI bus provide a very flexible interconnection scheme for any device sharing the RTSI or PXI-trigger bus. Any control signal on the device can connect to a RTSI or PXI-trigger bus line. You can drive output control signals onto the bus and receive input control signals from the bus. Figure D-6 shows the signal connection scheme.
E Optimizing Your Transfer Rates Use this appendix to determine the maximum transfer rate for your device, optimize transfer rates, and to see example benchmark results. Determining the Maximum Transfer Rates The maximum sustainable transfer rate a 653X device can achieve depends on the minimum available bus bandwidth and is based on your computer system.
Appendix E Optimizing Your Transfer Rates Table E-1. Peak Transfer Rates Based on Mode and Protocol Used (Continued) Mode/Protocol Peak Rate (MS/s) Handshaking Trailing-Edge Pulse 1.8 Handshaking Burst 20 Pattern I/O 20 Obtaining the Fastest Transfer Rates To achieve the highest transfer rates possible, consider the following: • Burst mode is the fastest handshaking protocol. You can further increase speed by using short cables. • Minimize the number of other I/O devices active in the system.
Appendix E Optimizing Your Transfer Rates Interpreting Benchmark Results Use benchmark results to get a general idea of what transfer rates to expect for an application. Since these results are system dependent, they are not to be used as specifications. View latest results on our website, ni.com Benchmark results are in megasamples per second and sample size is user defined. For example, if you are performing an eight-bit operation, then sample size is one byte.
Appendix E Optimizing Your Transfer Rates AT-DIO-32HS The following benchmarks are results using a Dell Dimension XPS, 600 MHz, PIII, and Windows 98 SE. Table E-3. AT-DIO-32HS Benchmark Results Benchmark Rate (MS/s) Mode 8 Bit 16 Bit 32 Bit Pattern I/O– Single Shot Input 1.67 .87 .83 Output 1.47 .74 .38 Pattern I/O– Continuous Input 1.67 .80 .31 Pattern I/O– Continuous Retransmit Output 1.43 .67 .39 Burst Protocol– Continuous Input 1.74 .87 .
Appendix E Optimizing Your Transfer Rates Table E-4. PCI-DIO-32HS Benchmark Results (Continued) Benchmark Rate (MS/s) Mode 8 Bit 16 Bit 32 Bit 4 1.81 1.81 Pattern I/O– Continuous Retransmit Output Burst Protocol– Continuous Input 19.93 19.6 19.05 Burst Protocol– Continuous Retransmit Output 19.92 19.58 18.54 PXI-6533 The following benchmarks are results using a PXI-8170, 450 MHz PIII, and Windows 98. Table E-5.
Appendix E Optimizing Your Transfer Rates DAQCard-6533 for PCMCIA The following benchmarks are results using a PXI-8170, 450 MHz PIII, and Windows 98. Table E-6. DAQCard-6533 for PCMCIA Benchmark Results Benchmark Rate (MS/s) Mode 8 Bit 16 Bit 32 Bit Pattern I/O– Single Shot Input 0.12 .11 .10 Output 0.12 .12 .10 Pattern I/O– Continuous Input 0.12 .11 .10 Pattern I/O– Continuous Retransmit Output 0.12 .12 .10 Burst Protocol– Continuous Input 0.24 .24 .
Appendix E Optimizing Your Transfer Rates Table E-7. PCI-6534 Benchmark Results (Continued) Benchmark Rate (MS/s) Mode 8 Bit 16 Bit 32 Bit Burst Protocol– Single Shot* Input 20 20 20 Output 20 20 20 Burst Protocol– Continuous Retransmit** Output 20 20 20 * Benchmarks made using buffer size ≤ onboard memory. ** Benchmarks made using buffer retransmitted ≤ onboard memory. PXI-6534 The following benchmarks are results using a PXI-8170, 450 MHz PIII, and Windows 98. Table E-8.
Appendix E Optimizing Your Transfer Rates PCI-7030/6533 with LabVIEW RT The following benchmarks are results using a 133 MHz AMD 486DX5 class processor, and the real-time operating system running on LabVIEW RT. Table E-9. PCI-7030/6533 Benchmark Results Benchmark Rate (MS/s) Mode 8 Bit 16 Bit 32 Bit Pattern I/O– Single Shot Input 1.82 .95 .49 Output 1.82 .91 .47 Pattern I/O– Continuous Input 1.67 .87 .48 Pattern I/O– Continuous Retransmit Output 1.25 .65 .
Appendix E Optimizing Your Transfer Rates Table E-10. PCI-7030/6533 Benchmark Results (Continued) Benchmark Rate (MS/s) Mode © National Instruments Corporation 8 Bit 16 Bit 32 Bit Pattern I/O– Continuous Retransmit Output 2.50 1.25 1.25 Burst Protocol– Continuous Input 19.98 19.97 19.97 Output 19.97 17.72 8.
Technical Support Resources F Web Support National Instruments Web support is your first stop for help in solving installation, configuration, and application problems and questions. Online problem-solving and diagnostic resources include frequently asked questions, knowledge bases, product-specific troubleshooting wizards, manuals, drivers, software updates, and more. Web support is available through the Technical Support section of ni.com NI Developer Zone The NI Developer Zone at ni.
Appendix F Technical Support Resources Worldwide Support National Instruments has offices located around the world to help address your support needs. You can access our branch office Web sites from the Worldwide Offices section of ni.com. Branch office web sites provide up-to-date contact information, support phone numbers, e-mail addresses, and current events.
Glossary Prefix Meaning Value k- kilo- 10 3 µ- micro- 10 – 6 m- milli- 10 –3 M- mega- 10 6 n- nano- 10 –9 Numbers/Symbols ° degrees – negative of, or minus < less than > greater than ≤ less than or equal to ≥ greater than or equal to Ω ohms / per % percent ± plus or minus + positive of, or plus +5 V (signal) +5 VDC source signal © National Instruments Corporation G-1 653X User Manual
Glossary A A amps ACK acknowledge—handshaking signal driven by the 653X device, indicating that it is ready to transfer data ADE Application Development Environment API Application Programming Interface—a standardized set of subroutines or functions along with the parameters that a program can call asynchronous For hardware, it is a property of an event that occurs at an arbitrary time, without synchronization to a reference clock.
Glossary channel Pin or wire lead to which you apply or from which you read the analog or digital signal. For digital signals, you group channels to form ports. Ports usually consist of either four or eight digital channels.
Glossary default setting A default parameter value recorded in the driver. In many cases, the default input of a control is a certain value (often 0) that means use the current default setting. device A plug-in data acquisition board, card, or pad that can contain multiple channels and conversion devices. Plug-in boards, PCMCIA cards, and devices that connects to your computer parallel port, are all examples of DAQ devices.
Glossary G group A collection of one, two, or four ports and an associated timing controller. All buffered operations must be performed on groups. H handshaking I/O Data-transfer mode in which the 653X device engages in a two-way communication with the peripheral device. The 653X asserts a signal, ACK, when it is ready for a data transfer and the peripheral device asserts a separate signal, REQ, when it is ready for a data transfer.
Glossary M M Mega—the standard metric prefix for 1 million or 10 6, when used with units of measure such as volts and hertz Measurement & Automation Explorer (MAX) a controlled centralized configuration environment that allows you to configure all of your National Instruments DAQ, GPIB, IMAQ, IVI, Motion, VISA, and VXI devices MB/s A unit for data transfer that means one million or 10 6 bits per second mask the bits that are significant for pattern detection, also applies to change detection MSB M
Glossary pretrigger acquiring data that occurs before a trigger propagation delay the amount of time required for a signal to pass through a circuit protocol the exact sequence of bits, characters and control codes used to transfer data between computers and peripherals through a communications channel, such as the GPIB PXI PCI eXtensions for Instrumentation—a rugged, open system for modular instrumentation based on CompactPCI, with special mechanical, electrical, and software features R real time
Glossary sample rate the number of samples a system takes over a given time period, usually expressed in samples per second software trigger a programmed event that triggers an event such as data acquisition STOPTRIG see control signals Strobed I/O Any operation where every data transfer is timed by hardware signals. In the case of pattern I/O, this hardware signal is a clock edge. In the case of handshaking I/O, hardware signals involve two or three handshaking lines.
Glossary W wired-OR output driver that drives its output pin to 0 V for logic low, but tri-states the pin (puts the pin in the high-impedance state) for logic high © National Instruments Corporation G-9 653X User Manual
Index Numbers output timing diagram (figure), 3-17 overview, 3-12 to 3-13 burst input timing diagrams default input timing diagram (figure), 3-8 PCLK reversed (figure), 3-10 transfer example (figure), 3-6 burst output timing diagrams output timing diagram (figure), 3-9 PCLK reversed (figure), 3-11 transfer example (figure), 3-6 connecting signals change detection, 2-31 handshaking I/O, 2-10 to 2-11 pattern I/O, 2-24 description (table), C-4 handshaking I/O and pattern I/O (table), C-1 leading-edge protocol
Index B long-pulse protocol input handshaking sequence (figure), 3-35 input state machine (figure), 3-36 input timing diagram (figure), 3-37 output handshaking sequence (figure), 3-38 output state machine (figure), 3-39 output timing diagram (figure), 3-40 polarity for handshaking I/O comparison of handshaking protocols (table), 3-4 to 3-5 controlling line polarity, 2-8 selecting polarity, 2-8 start and stop trigger change detection, 2-28 to 2-29 pattern I/O, 2-20 start trigger change detection, 2-28 patt
Index continuous output, 2-22 DMA or interrupt transfers, 2-22 finite, 2-21 control lines Group1 and Group2 controllers, 1-1 to 1-2 handshaking I/O and pattern I/O (table), C-1 using as extra unstrobed data lines, 2-3 to 2-4 CPULL signal description (table), C-5 power-on state, D-5 customer education, F-1 DMA or interrupt transfers, 2-31 finite, 2-30 overview, 2-26 port and timing controller combinations (table), 2-26 to 2-27 programming, 2-31 to 2-33 continuous change detection in NI-DAQ (figure), 2-32 L
Index H rate of data transfer, 2-18 to 2-19 triggering data transfer, 2-19 to 2-21 width of data to transfer, 2-17 delay, programmable, handshaking protocol, 2-8 to 2-9 digital I/O specifications, A-1 to A-2 digital lines. See static digital lines. digital patterns and waveforms. See pattern I/O. DIOA<0..7> signal (table), C-4 DIOB<0..7> signal (table), C-4 DIOC<0..7> signal (table), C-5 DIOD<0..
Index output handshaking sequence (figure), 3-38 output state machine (figure), 3-39 output timing diagram (figure), 3-40 signal edge-based protocols, 3-24 trailing-edge protocol, 3-25 to 3-28 input state machine (figure), 3-25 input timing diagram (figure), 3-26 output state machine (figure), 3-27 output timing diagram (figure), 3-28 hardware, D-1 to D-11 block diagrams AT-DIO-32HS, D-1 DAQCard-6533 for PCMCIA, D-2 PCI-DIO-32HS, PCI/PXI-7030/6533, and PXI-6533, D-3 PCI/PXI-6534, D-4 cable selection and te
Index input handshaking sequence (figure), 3-18 input state machine (figure), 3-19 input timing diagram (figure), 3-20 maximum transfer rate (table), E-2 output handshaking sequence (figure), 3-21 output state machine (figure), 3-22 output timing diagram (figure), 3-23 line state, monitoring. See change detection.
Index O timing diagrams, 3-1 to 3-3 external REQ signal source, 3-2 to 3-3 internal REQ signal source, 3-1 to 3-2 transfer direction, 2-18 transfer rate, 2-18 to 2-19 triggering data transfer, 2-19 to 2-21 pattern-matching trigger (input only), 2-20 to 2-21 start and stop trigger, 2-20 to 2-21 start trigger, 2-19 stop trigger, 2-19 to 2-20 when to use (table), 2-1 width of data to transfer, 2-17 pattern-matching trigger change detection, 2-29 to 2-30 input only, pattern I/O, 2-20 to 2-21 PCI-6534 device b
Index handshaking output in LabVIEW/LabVIEW RT (figure), 2-16 unbuffered handshaking I/O in NI-DAQ (figure), 2-14 pattern I/O, 2-24 to 2-26 continuous, in NI-DAQ, 2-25 LabVIEW/LabVIEW RT, 2-25 single buffer, in NI-DAQ, 2-24 unstrobed I/O, 2-4 to 2-6 control/timing lines as extra unstrobed data lines, 2-5 to 2-6 flowcharts, 2-5 PXI, using with CompactPCI, B-1 PXI bus interface. See RTSI and PXI trigger bus interfaces.
Index output handshaking sequence (figure), 3-38 output state machine (figure), 3-39 output timing diagram (figure), 3-40 polarity for handshaking I/O comparison of handshaking protocols (table), 3-4 to 3-5 controlling line polarity, 2-12 selecting polarity, 2-8 polarity for pattern I/O, 2-18 signal source for pattern I/O choosing internal or external source, 2-18 external REQ signal source, 3-2 to 3-3 internal REQ signal source, 3-1 to 3-2 trailing-edge protocol input handshaking sequence (figure), 3-25 i
Index standard output, unstrobed I/O, 2-2 start and stop trigger change detection, 2-28 to 2-29 pattern I/O, 2-20 to 2-21 trigger specifications, A-3 start trigger change detection, 2-28 pattern I/O, 2-19 STARTTRIG<1..
Index trigger bus interfaces. See RTSI and PXI trigger bus interfaces.
Index W waveforms. See pattern I/O. Web support from National Instruments, F-1 wired-OR output, unstrobed I/O, 2-2 to 2-3 Worldwide technical support, F-2 653X User Manual I-12 ni.
