PCI-DIO-96 User Manual A 96-Bit Parallel Digital I/O Interface for PCI Bus Computers January 1997 Edition Part Number 320938B-01 © Copyright 1996, 1997 National Instruments Corporation. All Rights Reserved.
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Important Information Warranty The PCI-DIO-96 is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
Table of Contents About This Manual Organization of This Manual ........................................................................................ix Conventions Used in This Manual................................................................................x National Instruments Documentation ...........................................................................xi Related Documentation.................................................................................................
Table of Contents Mode 1 Input Timing....................................................................... 3-10 Mode 1 Output Timing .................................................................... 3-11 Mode 2 Bidirectional Timing .......................................................... 3-12 Chapter 4 Theory of Operation Functional Overview .................................................................................................... 4-1 PCI Interface Circuitry...............................
Table of Contents Single Bit Set/Reset Feature ............................................................6-8 Mode 0–Basic I/O...........................................................................................6-8 Mode 0 Basic I/O Programming Example .......................................6-10 Mode 1–Strobed Input....................................................................................6-10 Port C Status-Word Bit Definitions for Input (Ports A and B) ........
Table of Contents Figures Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware ............................................................... 1-4 Figure 3-1. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. PCI-DIO-96 Cable-Assembly Connector Pinout for Pins 1 through 50 with the R1005050 Ribbon Cable .................................................... 3-2 PCI-DIO-96 Cable-Assembly Connector Pinout for Pins 51 through 100 with the R1005050 Ribbon Cable ..........
About This Manual This manual describes the electrical and mechanical aspects of the PCI-DIO-96 and contains information concerning its installation, operation, and programming. The PCI-DIO-96 is a member of the National Instruments PCI Series of expansion boards for PCI bus computers. These boards are designed for high-performance data acquisition and control for applications in laboratory testing, production testing, and industrial process monitoring and control.
About This Manual • Appendix B, MSM82C55A Data Sheet, contains a manufacturer data sheet for the MSM82C55A CMOS programmable peripheral interface (OKI Semiconductor). This device is used on the PCI-DIO-96. • Appendix C, MSM82C53 Data Sheet, contains a manufacturer data sheet for the MSM82C53 CMOS programmable interval timer (OKI Semiconductor). This timer is used on the PCI-DIO-96.
About This Manual SCXI SCXI stands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front-end signal conditioning for National Instruments plug-in DAQ boards. <> Angle brackets containing numbers separated by an ellipses represent a range of values associated with a bit, signal, or port (for example, ACH<0..7> stands for ACH0 through ACH7).
About This Manual • Accessory installation guides or manuals—If you are using accessory products, read the terminal block and cable assembly installation guides or accessory board user manuals. They explain how to physically connect the relevant pieces of the system. Consult these guides when you are making your connections. • SCXI Chassis User Manual—If you are using SCXI, read these manuals for maintenance information on the chassis and installation instructions.
Chapter 1 Introduction This chapter describes the PCI-DIO-96; lists what you need to get started, software programming choices, optional equipment; describes custom cabling options; and explains how to unpack the PCI-DIO-96. About the PCI-DIO-96 Thank you for purchasing a National Instruments PCI-DIO-96 board. The PCI-DIO-96 is a 96-bit, parallel, digital I/O interface for PCI bus computers. Four 82C55A programmable peripheral interface (PPI) chips control the 96 bits of TTL-compatible digital I/O.
Chapter 1 Introduction What You Need to Get Started To set up and use your PCI-DIO-96 board, you will need the following: ❑ PCI-DIO-96 board ❑ PCI-DIO-96 User Manual ❑ One of the following software packages and documentation: ComponentWorks LabVIEW for Macintosh LabVIEW for Windows LabWindows/CVI for Windows NI-DAQ for Macintosh NI-DAQ for PC Compatibles ❑ Your computer Software Programming Choices There are several options to choose from when programming your National Instruments DAQ hardware.
Chapter 1 Introduction LabWindows/CVI features interactive graphics, a state-of-the-art user interface, and uses the ANSI standard C programming language. The LabWindows/CVI Data Acquisition Library, a series of functions for using LabWindows/CVI with National Instruments DAQ hardware, is included with the NI-DAQ software kit. The LabWindows/CVI Data Acquisition Library is functionally equivalent to the NI-DAQ software.
Chapter 1 Introduction Conventional Programming Environment ComponentWorks, LabVIEW, or LabWindows/CVI NI-DAQ Driver Software DAQ or SCXI Hardware Personal Computer or Workstation Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware Register-Level Programming The final option for programming any National Instruments DAQ hardware is to write register-level software.
Chapter 1 Introduction Optional Equipment National Instruments offers a variety of products to use with your PCI-DIO-96 board, including cables, connector blocks, and other accessories, as follows: • Cables and cable assemblies • Connector blocks, 50-pin screw terminals • SCXI modules and accessories for isolating, amplifying, exciting, and multiplexing signals for relays and analog output. With SCXI you can condition and acquire up to 3,072 channels.
Chapter 1 Introduction Unpacking Your PCI-DIO-96 board is shipped in an antistatic package to prevent electrostatic damage to the board. Electrostatic discharge can damage several components on the board. To avoid such damage in handling the board, take the following precautions. PCI-DIO-96 User Manual • Ground yourself via a grounding strap or by holding a grounded object. • Touch the antistatic package to a metal part of your computer chassis before removing the board from the package.
Chapter Installation and Configuration 2 This chapter describes how to install and configure your PCI-DIO-96 board. Software Installation If you are using NI-DAQ, ComponentWorks, LabWindows/CVI, or LabVIEW, refer to the installation instructions in your documentation to install and configure your software. If you are a register-level programmer, refer to Chapter 5, Register Map and Description, and Chapter 6, Programming, of this manual.
Chapter 2 Installation and Configuration Board Configuration The PCI-DIO-96 is completely software configurable. The PCI-DIO-96 is fully compliant with the PCI Local Bus Specification, Revision 2.0. Therefore, all board resources are automatically allocated by the PCI system, including the base address and interrupt level. The base address for the PCI-DIO-96 is mapped into PCI memory space. You do not need to perform any configuration steps after the system powers up.
Chapter 3 Signal Connections This chapter describes how to make input and output signal connections to your PCI-DIO-96 via the board I/O connector. I/O Connector The I/O connector for the PCI-DIO-96 has 100 pins that you can connect to 50-pin accessories with the R1005050 cable. ! Warning: Connections that exceed any of the maximum ratings of input or output signals on the PCI-DIO-96 can damage the PCI-DIO-96 board and your computer.
Chapter 3 Signal Connections APC7 1 2 BPC7 APC6 3 4 BPC6 APC5 5 6 BPC5 APC4 7 8 BPC4 APC3 9 10 BPC3 APC2 11 12 BPC2 APC1 13 14 BPC1 APC0 15 16 BPC0 APB7 17 18 BPB7 APB6 19 20 BPB6 APB5 21 22 BPB5 APB4 23 24 BPB4 APB3 25 26 BPB3 APB2 27 28 BPB2 APB1 29 30 BPB1 APB0 31 32 BPB0 APA7 33 34 BPA7 APA6 35 36 BPA6 APA5 37 38 BPA5 APA4 39 40 BPA4 APA3 41 42 BPA3 APA2 43 44 BPA2 APA1 45 46 BPA1 APA0 47 48 BPA0 +5 V 49 50 GND Figure 3-1.
Chapter 3 CPC7 51 52 DPC7 CPC6 53 54 DPC6 CPC5 55 56 DPC5 CPC4 57 58 DPC4 CPC3 59 60 DPC3 CPC2 61 62 DPC2 CPC1 63 64 DPC1 CPC0 65 66 DPC0 CPB7 67 68 DPB7 CPB6 69 70 DPB6 CPB5 71 72 DPB5 CPB4 73 74 DPB4 CPB3 75 76 DPB3 CPB2 77 78 DPB2 CPB1 79 80 DPB1 CPB0 81 82 DPB0 CPA7 83 84 DPA7 CPA6 85 86 DPA6 CPA5 87 88 DPA5 CPA4 89 90 DPA4 CPA3 91 92 DPA3 CPA2 93 94 DPA2 CPA1 95 96 DPA1 CPA0 97 98 DPA0 +5 V 99 100 GND Signal Connections Figure
Chapter 3 Signal Connections Table 3-1 lists the signal descriptions for the PCI-DIO-96 I/O connector pins. Table 3-1. Signal Descriptions for PCI-DIO-96 I/O Connector Pins Pin Signal Name Description 1, 3, 5, 7, 9, 11, 13, 15 APC<7..0> Bidirectional data lines for port C of PPI A—APC7 is the MSB, APC0 the LSB. 2, 4, 6, 8, 10, 12, 14, 16 BPC<7..0> Bidirectional data lines for port C of PPI B—BPC7 is the MSB, BPC0 the LSB. 17, 19, 21, 23, 25, 27, 29, 31 APB<7..
Chapter 3 Signal Connections Table 3-1. Signal Descriptions for PCI-DIO-96 I/O Connector Pins (Continued) Pin Signal Name Description 83, 85, 87, 89, 91, 93, 95, 97 CPA<7..0> Bidirectional data lines for port A of PPI C—CPA7 is the MSB, CPA0 the LSB. 84, 86, 88, 90, 92, 94, 96, 98 DPA<7..0> Bidirectional data lines for port A of PPI D—DPA7 is the MSB, DPA0 the LSB. Port C Pin Assignments The signals assigned to port C depend on how the 82C55A is configured.
Chapter 3 Signal Connections Table 3-2.
Chapter 3 Signal Connections Figure 3-3 depicts signal connections for three typical digital I/O applications. +5 V LED 41 PPI A Port A 43 45 APA<3..0> 47 67 69 PPI C Port B TTL Signal 71 CPB<7..4> 73 +5 V Switch 50, 100 GND I/O Connector PCI-DIO-96 Board Figure 3-3. Digital I/O Connections Block Diagram In Figure 3-3, PPI A, port A, is configured for digital output, and PPI C, port B, is configured for digital input.
Chapter 3 Signal Connections Power Connections Pins 49 and 99 of the I/O connector supply +5 V from the computer’s power supply via a self-resetting fuse. The fuse will reset automatically within a few seconds after the overcurrent condition is removed. These pins are referenced to GND and can be used to power external digital circuitry. For more information on these output pins, see Appendix A, Specifications. • Power rating 1 A at +4.65 to +5.
Chapter 3 Signal Connections Table 3-3. Signal Names Used in Timing Diagrams (Continued) Name Type Description INTR Output Interrupt Request—This signal becomes high when the 82C55A requests service during a data transfer. The appropriate interrupt enable bits must be set to generate this signal. RD* Internal Read—This signal is the read signal generated from the control lines of the computer I/O expansion bus.
Chapter 3 Signal Connections Mode 1 Input Timing The timing specifications for an input transfer in mode 1 are as follows: T1 T2 T4 STB * T7 IBF T6 INTR RD * T3 T5 DATA Name Description Minimum Maximum T1 STB* Pulse Width 100 — T2 STB* = 0 to IBF = 1 — 150 T3 Data before STB* = 1 20 — T4 STB* = 1 to INTR = 1 — 150 T5 Data after STB* = 1 50 — T6 RD* = 0 to INTR = 0 — 200 — 150 T7 RD* = 1 to IBF = 0 All timing values are in nanoseconds. Figure 3-4.
Chapter 3 Signal Connections Mode 1 Output Timing The timing specifications for an output transfer in mode 1 are as follows: T3 WR* T4 OBF* T1 T6 INTR T5 ACK* DATA T2 Name Description Minimum Maximum T1 WR* = 0 to INTR = 0 — 250 T2 WR* = 1 to Output — 200 T3 WR* = 1 to OBF* = 0 — 150 T4 ACK* = 0 to OBF* = 1 — 150 T5 ACK* Pulse Width 100 — — 150 T6 ACK* = 1 to INTR = 1 All timing values are in nanoseconds. Figure 3-5.
Chapter 3 Signal Connections Mode 2 Bidirectional Timing The timing specifications for bidirectional transfers in mode 2 are as follows: T1 WR * T6 OBF * INTR T7 ACK * T3 STB * T10 T4 IBF RD * T2 T5 T8 T9 DATA Name Description Minimum Maximum T1 WR* = 1 to OBF* = 0 — 150 T2 Data before STB* = 1 20 — T3 STB* Pulse Width 100 — T4 STB* = 0 to IBF = 1 — 150 T5 Data after STB* = 1 50 — T6 ACK* = 0 to OBF* = 1 — 150 T7 ACK* Pulse Width 100 — T8 ACK* = 0 to Output
Chapter 4 Theory of Operation This chapter contains a functional overview of the PCI-DIO-96 and explains the operation of each functional unit comprising the PCI-DIO-96. Functional Overview The block diagram in Figure 4-1 illustrates the key functional components of the PCI-DIO-96 board.
Chapter 4 Theory of Operation Data/Address 37 82C55A PPI A Interface Control Port A 8 Port B 8 Port C 8 Port A 8 Port B 8 Port C 8 Port A 8 Port B 8 Port C 8 Port A 8 Port B 8 Port C 8 Error Reporting MITE PCI Interface Circuitry 2 Arbitration Data Bus 82C55A PPI B 2 System PCI 2 82C55A PPI C Interrupt 1 Interrupt Interrupt Control Circuitry 82C55A PPI D Interrupt Bus I/O Connector 6 82C53 Timer +5 VDC 1 A Fuse Figure 4-1.
Chapter 4 Theory of Operation 82C55A Programmable Peripheral Interface The four 82C55A PPI chips are the heart of the PCI-DIO-96. Each of these chips has 24 programmable I/O pins that represent three 8-bit ports: PA, PB, and PC. Each port can be programmed as an input or output port. The 82C55A has three modes of operation: simple I/O (mode 0), strobed I/O (mode 1), and bidirectional I/O (mode 2). In modes 1 and 2, the three ports are divided into two groups: group A and group B.
Chapter 4 Theory of Operation The block diagram in Figure 4-2 illustrates the PCI-DIO-96 interrupt control circuitry. 82C53 Counter/Timer CLK0 2 MHz +5 V OUT0 GATE0 CLK1 +5 V OUT1 PCI Interrupt GATE1 CLK2 OUT2 GATE2 PC3 82C55A PPI A PC0 Interrupt Control Circuitry PC3 82C55A PPI B PC0 PC3 82C55A PPI C PC0 PC3 82C55A PPI D PC0 PCI-DIO-96 Interrupt Control Registers Figure 4-2.
Chapter Register Map and Description 5 This chapter describes in detail the address and function of each PCI-DIO-96 register. Note: If you plan to use a programming software package such as ComponentWorks, LabVIEW, LabWindows/CVI, or NI-DAQ with your PCI-DIO-96 board, you need not read this chapter. Introduction The three 8-bit ports of the 82C55A are divided into two groups of 12 signals: group A and group B. One 8-bit control word selects the mode of operation for each group.
Chapter 5 Register Map and Description Register Map Table 5-1 lists the address map for the PCI-DIO-96. Table 5-1.
Chapter 5 Register Map and Description Table 5-1.
Chapter 5 Register Map and Description is 1, bits 6 through 0 select the I/O characteristics of the 82C55A ports. These bits also select the mode in which the ports are operating; that is, mode 0, mode 1, or mode 2. When the control word flag is 0, bits 3 through 0 select the bit set/reset format of port C.
Chapter 5 Register Map and Description Table 5-2 shows the control words for setting or resetting each bit in port C. Notice that bit 7 of the control word is cleared when programming the set/reset option for the bits of port C. Table 5-2.
Chapter 5 Register Map and Description D7 D6 D5 D4 D3 D2 D1 D0 Counter Select 00 = Counter 0 01 = Counter 1 10 = Counter 2 11 = Illegal BCD 1 = Count in BCD 0 = Count in Binary Access Mode 00 = Latch counter value 01 = Access LSB only 10 = Access MSB only 11 = Access LSB, then MSB Mode Select 000 = Mode 0 001 = Mode 1 010 = Mode 2 011 = Mode 3 100 = Mode 4 101 = Mode 5 110 = Mode 2 111 = Mode 3 Figure 5-2.
Chapter 5 Register Map and Description Interrupt Control Register 1 Address: Base address + 14 (hex) Type: Write-only Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 DIRQ1 DIRQ0 CIRQ1 CIRQ0 BIRQ1 BIRQ0 AIRQ1 AIRQ0 Bit Name Description 7 DIRQ1 PPI D Port B Interrupt Enable Bit—If this bit and the INTEN bit in Interrupt Control Register 2 are both set, PPI D sends an interrupt, INTRB, to the computer.
Chapter 5 Register Map and Description Bit Name Description (Continued) 3 BIRQ1 PPI B Port B Interrupt Enable Bit—If this bit and the INTEN bit in Interrupt Control Register 2 are both set, PPI B sends an interrupt, INTRB, to the computer. If this bit is cleared, PPI B does not send the interrupt INTRB to the computer, regardless of the setting of INTEN.
Chapter 5 Register Map and Description Interrupt Control Register 2 Address: Base address + 15 (hex) Type: Write-only Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 X X X X X INTEN CTRIRQ CTR1 Bit Name Description 7–3 X Don’t care bit. 2 INTEN Interrupt Enable Bit—If this bit is set, the PCI-DIO-96 can interrupt the computer. If this bit is cleared, the PCI-DIO-96 cannot generate interrupts to the computer, regardless of the status of the bits in Interrupt Control Register 2.
Chapter 5 Register Map and Description Interrupt Clear Register The interrupt clear register has no bits associated with it. Use this register to reset the state of the interrupt request signal once the interrupt routine has been entered. To clear the interrupt, perform an 8-bit write to this register address; the data is irrelevant.
Chapter 6 Programming This chapter contains instructions on how to operate the PCI-DIO-96 circuitry, and examples of the programming steps necessary to execute an operation. If you are not using NI-DAQ, you must first initialize your board. The initialization steps are unique for PC and Macintosh users, so refer to the section pertaining to your platform. Programming the PCI-DIO-96 involves writing to and reading from registers on the board.
Chapter 6 Programming Before you can implement any of the examples into a real application, you must know the base memory address for your board. To generate and process any interrupts, you must write and install an applicable interrupt service routine.
Chapter 6 Programming PCI Initialization for the PC To program at the register level without NI-DAQ, you must know the PCI-DIO-96 base memory address and install an interrupt handler to generate interrupts. Writing an interrupt handler is solely left to you and is not discussed in this manual. The PCI-DIO-96 uses the MITE Application Specific Integrated Circuit (ASIC) chip as the PCI bus interface. National Instruments designed this ASIC specifically for data acquisition.
Chapter 6 Programming 4. Create the window data value by masking the new board address: window data value = ((0xffffff00 and new board address) or (0x00000080)) If you are not remapping the board, then the new board address is the value in BAR1. 5. Write the window data value to offset 0xc0 from the new MITE address. If you are not remapping the board, then the new MITE address is the value in BAR0.
Chapter 6 Programming system. When you develop a driver using the toolkit, your driver plug-in has access to all the information and support functions it needs to control the device and respond to interrupts. When you use the toolkit, your application is divided into two parts—a driver and an interface to the driver. You use the driver to control the hardware and the interface to control the driver.
Chapter 6 Programming ) { unsigned short pciCommandRegister; unsigned long cardBaseAddress, miteBaseAddress; // configure the i/o space of the board such // that it is memory mapped. ExpMgrConfigReadWord(deviceNode, ((LogicalAddress) 0x00000004L), &pciCommandRegister); ExpMgrConfigWriteWord(deviceNode, ((LogicalAddress) 0x00000004L), (pciCommandRegister | 0x0002)); // get the base addresses for the board.
Chapter 6 Programming Table 6-1. Port Identification ComponentWorks, LabVIEW, LabWindows/CVI, and NI-DAQ PCI-DIO-96 User Manual 0 1 2 3 4 5 6 7 8 9 10 11 PPI A Port A PPI A Port B PPI A Port C PPI B Port A PPI B Port B PPI B Port C PPI C Port A PPI C Port B PPI C Port C PPI D Port A PPI D Port B PPI D Port C This manual also differs from the NI-DAQ, ComponentWorks, LabWindows/CVI, and LabVIEW documentation by using different terminology to describe the 82C55A configurations.
Chapter 6 Programming Mode 0 has the following features: • Two 8-bit ports (A and B) and two 4-bit ports (upper and lower nibbles of port C). • Any port can be input or output. • Outputs are latched, but inputs are not latched. Mode 1 This mode transfers data that is synchronized by handshaking signals. Ports A and B use the eight lines of port C to generate or receive the handshake signals.
Chapter 6 Programming Table 6-2.
Chapter 6 Programming Mode 0 Basic I/O Programming Example The following example shows how to configure PPI A for mode 0 input and output.
Chapter 6 Programming Figure 6-2 shows the control word written to the Configuration Register to configure port B for input in mode 1. Notice that port B does not have extra input or output lines from port C. D7 D6 D5 D4 D3 D2 D1 D0 1 X X X X 1 1 X Figure 6-2. Control Word to Configure Port B for Mode 1 Input During a mode 1 data read transfer, read port C to obtain the status of the handshaking lines and interrupt signals.
Chapter 6 Programming Port C Status-Word Bit Definitions for Input (Ports A and B) Address: Base address + 03 (hex) for PPI A Base address + 07 (hex) for PPI B Base address + 0B (hex) for PPI C Base address + 0F (hex) for PPI D Type: Read and write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB Bit Name Description 7–6 I/O Input/Output—These bits can be used for general-purpose I/O when port A is in mode 1 input.
Chapter 6 Programming At the digital I/O connector, port C has the pin assignments shown in Figure 6-3 when in mode 1 input. Notice that the status of STBA* and the status of STBB* are not included in the port C status word. Group A Group B PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 I/O I/O IBFA STBA* INTRA STBB* IBFB INTRB Figure 6-3.
Chapter 6 Programming D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1/0 X X X Port C bits PC4 and PC5 1 = Input 0 = Output Figure 6-4. Control Word to Configure Port A for Mode 1 Output The control word written to the Configuration Register to configure port B for output in mode 1 is shown in Figure 6-5. Notice that port B does not have extra input or output lines from port C. D7 D6 D5 D4 D3 D2 D1 D0 1 X X X X 1 0 X Figure 6-5.
Chapter 6 Programming Port C Status-Word Bit Definitions for Output (Ports A and B) Address: Base address + 03 (hex) for PPI A Base address + 07 (hex) for PPI B Base address + 0B (hex) for PPI C Base address + 0F (hex) for PPI D Type: Read and write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 OBFA* INTEA I/O I/O INTRA INTEB OBFB* INTRB Bit Name Description 7 OBFA* Output Buffer for Port A—A low setting indicates that the CPU has written data to port A.
Chapter 6 Programming At the digital I/O connector, port C has the pin assignments shown in Figure 6-6 when in mode 1 output. Notice that the status of ACKA* and ACKB* are not included when port C is read. Group A Group B PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 OBFA* ACKA* I/O I/O INTRA ACKB* OBFB* INTRB Figure 6-6. Port C Pin Assignments on I/O Connector when Port C Configured for Mode 1 Output Mode 1 Strobed Output Programming Example The following example shows how to configure PPI A for mode 1 output.
Chapter 6 D7 D6 D5 D4 D3 D2 D1 D0 1 1 X X X 1/0 1/0 1/0 Programming Port C PC <2..0> 1 = Input 0 = Output Port B 1 = Input 0 = Output Group B Mode 0 = Mode 0 1 = Mode 1 Figure 6-7. Control Word to Configure Port A as Mode 2 Bidirectional Data Bus During a mode 2 data transfer, you can obtain the status of the handshaking lines and interrupt signals by reading port C. The port C status-word bit definitions for a mode 2 transfer are shown as follows.
Chapter 6 Programming Port C Status-Word Bit Definitions for Bidirectional Data Path (Port A Only) Address: Base address + 03 (hex) for PPI A Base address + 07 (hex) for PPI B Base address + 0B (hex) for PPI C Base address + 0F (hex) for PPI D Type: Read and write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 OBFA* INTE1 IBFA INTE2 INTRA I/O I/O I/O Bit Name Description 7 OBFA* Output Buffer for Port A—A low setting indicates that the CPU has written data to port A.
Chapter 6 Programming Bit Name Description (Continued) 2-0 I/O Input/Output—Use these bits for general-purpose I/O lines if group B is configured for mode 0. If group B is configured for mode 1, refer to the bit explanations shown in the preceding mode 1 sections. Figure 6-8 shows the port C pin assignments on the digital I/O connector when port C is configured for mode 2. Notice that the status of STBA* and the status of ACKA* are not included in the port C status word.
Chapter 6 Programming Interrupt Handling You must set the INTEN bit of Interrupt Control Register 2 to enable interrupts from the PCI-DIO-96. Clear this bit first to disable unwanted interrupts. After all sources of interrupts have been disabled or placed in an inactive state, you can set INTEN. You must set INTEN before you generate an interrupt for proper operation. To interrupt the computer using one of the 82C55A devices, program the selected 82C55A for the I/O mode desired.
Chapter 6 Programming Mode 1 Strobed Input Programming Example The following example shows how to set up interrupts for mode 1 input for port A. Write (8255Cnfg, 0xB0) Write (8255Cnfg, 0x09) Write (IREG2, 0x04) Write (IREG1, 0x01) Set mode 1-port A is an input Set PC4 to enable interrupts from the 82C55A Set INTEN bit Set AIRQ0 to enable PPI A, port A interrupts Mode 1 Strobed Output Programming Example The following example shows how to set up interrupts for mode 1 output for port A.
Chapter 6 Programming Programming Considerations for the 82C53 A general overview of the 82C53 and how it is configured on the PCI-DIO-96 follows. General Information The 82C53 contains three counter/timers, each of which can operate in one of six different modes. However, only counter 0 and counter 1 are configured for operation; counter 2 is not connected, nor is it available on the external I/O connector.
Chapter 6 Programming The counter begins counting as soon as the most significant byte is written. When you are ready to exit your program, disable the counter and interrupts as shown below. Write(Cnfg, 0x30) Write(IREG2, 0x00) interrupts Note: Turn off counter 0 Disable all PCI-DIO-96 In order for any of the interrupts to be processed, you must write and install an interrupt service routine. Failure to do so could cause the system to fail upon the interrupt generation.
Appendix A Specifications This appendix lists the specifications for the PCI-DIO-96. These specifications are typical at 25° C unless otherwise noted. Digital I/O Number of channels ............................... 96 I/O Compatibility ......................................... TTL Reference voltage................................... +5 V Power on state ........................................
Appendix A Specifications Transfer rate1 (1 word = 8 bits), absolute max Language Macintosh PC Ca 900 kHz 845 kHz LabVIEWb 2.8 kHz 3.8 kHz a C routine is used to write/read data to/from a port VI is used to write/read data to/from a port b LabVIEW Handshaking ....................................3 wire, two port Data transfers...................................Interrupts, programmed I/O Bus Interface Type ........................................................
Appendix MSM82C55A Data Sheet* B This appendix contains a manufacturer data sheet for the MSM82C55A CMOS programmable peripheral interface (OKI Semiconductor). This interface is used on the PCI-DIO-96. * Copyright© OKI Semiconductor. 1993. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor. Microprocessor Data Book 1993.
Appendix MSM82C53 Data Sheet* C This appendix contains a manufacturer data sheet for the MSM82C53 CMOS programmable interval timer (OKI Semiconductor). This timer is used on the PCI-DIO-96. * Copyright© OKI Semiconductor. 1993. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor. Microprocessor Data Book 1993.
Appendix Customer Communication D For your convenience, this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation. When you contact us, we need the information on the Technical Support Form and the configuration form, if your manual contains one, about your system configuration to answer your questions as quickly as possible.
Fax-on-Demand Support Fax-on-Demand is a 24-hour information retrieval system containing a library of documents on a wide range of technical information. You can access Fax-on-Demand from a touch-tone telephone at (512) 418-1111. E-Mail Support (currently U.S. only) You can submit technical support questions to the applications engineering team through e-mail at the Internet address listed below. Remember to include your name, address, and phone number so we can contact you with solutions and suggestions.
Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
PCI-DIO-96 Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: PCI-DIO-96 User Manual Edition Date: January 1997 Part Number: 320938B-01 Please comment on the completeness, clarity, and organization of the manual.
Glossary Prefix Meaning Value p- pico- 10-12 n- nano- 10-9 µ- micro- 10-6 m- milli- 10-3 k- kilo- 103 M- mega- 106 G- giga- 109 Numbers/Symbols ˚ degrees > greater than ≥ greater than or equal to < less than - negative of, or minus Ω ohms / per % percent © National Instruments Corporation G-1 PCI-DIO-96 User Manual
Glossary ± plus or minus + positive of, or plus +5 V +5 Volts signal A A amperes ACK* acknowledge input signal AIRQ0 PPI A port A interrupt enable bit AIRQ1 PPI A port B interrupt enable bit ANSI American National Standards Institute APA PPI A port A APB PPI A port B APC PPI A port C ASIC Application Specific Integrated Circuit AWG American Wire Gauge B BIRQ0 PPI B port A interrupt enable bit BIRQ1 PPI B port B interrupt enable bit BPA PPI B port A BPB PPI B port B BPC PP
Glossary C C Celsius CIRQ0 PPI C port A interrupt enable bit CIRQ1 PPI C port B interrupt enable bit cm centimeters CPA PPI C port A CPB PPI C port B CPC PPI C port C CTR1 counter select bit CTRIRQ counter interrupt enable bit D DAQ a system that uses the personal computer to collect, measure, and generate electrical signals DI digital input DIO digital input/output DIRQ0 PPI D port A interrupt enable bit DIRQ1 PPI D port B interrupt enable bit DMA direct memory access—a method
Glossary F ft feet G GND ground signal H hex hexadecimal I IBF input buffer full signal in.
Glossary M m meters max maximum MB megabytes of memory min. minutes min minimum MSB most significant bit O OBF* output buffer full signal P PA, PB, PC <0..7> port A, B, or C 0 through 7 lines PCI Peripheral Component Interconnect—a high-performance expansion bus architecture originally developed by Intel to replace ISA and EISA. It is achieving widespread acceptance as a standard for PCs and work-stations; it offers a theoretical maximum transfer rate of 132 Mbytes/s.
Glossary S S samples s seconds SCXI Signal Conditioning eXtensions for Instrumentation—the National Instruments product line for conditioning low-level signals within an external chassis near sensors so only high-level signals are sent to DAQ boards in the noisy PC environment signal conditioning the manipulation of signals to prepare them for digitizing STB strobe input signal T TTL transistor-transistor logic typ typical V V volts VDC volts direct current VI virtual instrument—a combin
Index Numbers Port C status-word bit definitions, 6-12 to 6-13 programming example, 6-13 Mode 1 strobed output, 6-13 to 6-16 control word configuration Port A (figure), 6-14 Port B (figure), 6-14 Port C pin assignments (figure), 6-16 Port C status-word bit definitions, 6-15 to 6-16 programming example, 6-16 Mode 2 bidirectional bus, 6-16 to 6-19 control word configuration of Port A (figure), 6-17 Port C pin assignments (figure), 6-19 Port C status-word bit definitions, 6-18 to 6-19 programming example, 6-
Index control words 82C53 Register Group control word format (figure), 5-6 82C55A Register Group control word formats (figure), 5-4 Port C set/reset control words (table), 5-5 Mode 1 strobed input Port A configuration (figure), 6-10 Port B configuration (figure), 6-11 Mode 1 strobed output Port A configuration (figure), 6-14 Port B configuration (figure), 6-14 Mode 2 bidirectional bus (figure), 6-17 CPA<7..0> signal (table), 3-5 CPB<7..0> signal (table), 3-4 CPC<7..
Index INTE2 bit, 6-18 INTEA bit Mode 1 strobed input, 6-12 Mode 1 strobed output, 6-15 INTEB bit Mode 1 strobed input, 6-12 Mode 1 strobed output, 6-15 INTEN bit, 5-9 interrupt control circuitry block diagram, 4-4 theory of operation, 4-3 Interrupt Control Register Group address map (table), 5-3 Interrupt Clear Register, 5-10 Interrupt Control Register 1, 5-7 to 5-8 Interrupt Control Register 2, 5-9 interrupt generation developing your own driver, 6-5 to 6-6 simple access with Get_DAQ_device_Info, 6-5 usin
Index Port C pin assignments on I/O connector (figure), 6-13 Port C status-word bit definitions for input, 6-12 to 6-13 programming example, 6-13 timing (figure), 3-10 Mode 1 output interrupt programming example, 6-21 overview and features, 6-8 strobed output programming considerations, 6-13 to 6-16 control word to configure Port A (figure), 6-14 control word to configure Port B (figure), 6-14 Port C pin assignments on I/O connector (figure), 6-16 Port C status-word bit definitions for output, 6-15 to 6-16
Index LabVIEW application software, 1-2 LabWindows/CVI application software, 1-3 NI-DAQ driver software, 1-3 to 1-4 register-level programming, 1-4 unpacking, 1-6 physical specifications, A-2 Port C pin assignments correlation between mode and handshaking terminology (table), 3-5 to 3-6 I/O connector Mode 1 input (figure), 6-13 Mode 1 output (figure), 6-16 Mode 2 bidirectional bus, 6-19 mode configuration, 3-5 to 3-6 overview, 3-5 Port C set/reset control words (table), 5-5 Port C status-word bit definitio
Index Port C status-word bit definitions for input, 6-12 to 6-13 programming example, 6-13 Mode 1 strobed output, 6-13 to 6-16 control word to configure Port A (figure), 6-14 control word to configure Port B (figure), 6-14 Port C pin assignments on I/O connector (figure), 6-16 Port C status-word bit definitions for output, 6-15 to 6-16 programming example, 6-16 Mode 2 bidirectional bus, 6-16 to 6-19 control word to configure Port A (figure), 6-17 Port C pin assignments on I/O connector, 6-19 Port C status-
Index Mode 1 input timing, 3-10 Mode 1 output timing, 3-11 Mode 2 bidirectional timing, 3-12 signal names used in timing diagrams (table), 3-8 to 3-9 simple accesses using Get_DAQ_device_Info, 6-5 single bit set/reset feature, 6-8 software installation, 2-1 software programming choices, 1-2 to 1-4 ComponentWorks, 1-2 LabVIEW application software, 1-2 LabWindows/CVI, 1-3 NI-DAQ driver software, 1-3 to 1-4 register-level programming, 1-4 specifications bus interface, A-2 digital I/O, A-1 to A-2 environment,
Index signal names used in timing diagrams (table), 3-8 to 3-9 U unpacking the PCI-DIO-96, 1-6 W WR* signal description (table), 3-9 Mode 1 output timing (figure), 3-11 Mode 2 bidirectional timing (figure), 3-12 PCI-DIO-96 User Manual I -8 © National Instruments Corporation
