DAQ 6023E/6024E/6025E Multifunction I/O Devices User Manual
Table Of Contents
- 6023E/6024E/6025E User Manual
- Support
- Important Information
- Contents
- About This Manual
- Chapter 1 Introduction
- Chapter 2 Installation and Configuration
- Chapter 3 Hardware Overview
- Chapter 4 Signal Connections
- I/O Connector
- Analog Input Signal Overview
- Analog Input Signal Connections
- Analog Output Signal Connections
- Digital I/O Signal Connections
- Programmable Peripheral Interface (PPI)
- Power Connections
- Timing Connections
- Field Wiring Considerations
- Chapter 5 Calibration
- Appendix A Specifications
- Appendix B Custom Cabling and Optional Connectors
- Appendix C Common Questions
- Appendix D Technical Support Resources
- Glossary
- Index
- Figures
- Figure 1-1. The Relationship Between the Programming Environment, NI-DAQ, and Your Hardware
- Figure 3-1. PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E Block Diagram
- Figure 3-2. DAQCard-6024E Block Diagram
- Figure 3-3. Dithering
- Figure 3-4. CONVERT* Signal Routing
- Figure 3-5. PCI RTSI Bus Signal Connection
- Figure 3-6. PXI RTSI Bus Signal Connection
- Figure 4-1. I/O Connector Pin Assignment for the 6023E/6024E
- Figure 4-2. I/O Connector Pin Assignment for the 6025E
- Figure 4-3. Programmable Gain Instrumentation Amplifier (PGIA)
- Figure 4-4. Summary of Analog Input Connections
- Figure 4-5. Differential Input Connections for Ground Referenced Signals
- Figure 4-6. Differential Input Connections for Nonreferenced Signals
- Figure 4-7. Single Ended Input Connections for Nonreferenced or Floating Signals
- Figure 4-8. Single Ended Input Connections for Ground Referenced Signals
- Figure 4-9. Analog Output Connections
- Figure 4-10. Digital I/O Connections
- Figure 4-11. Digital I/O Connections Block Diagram
- Figure 4-12. DIO Channel Configured for High DIO Power-up State with External Load
- Figure 4-13. Timing Specifications for Mode 1 Input Transfer
- Figure 4-14. Timing Specifications for Mode 1 Output Transfer
- Figure 4-15. Timing Specifications for Mode 2 Bidirectional Transfer
- Figure 4-16. Timing I/O Connections
- Figure 4-17. Typical Posttriggered Acquisition
- Figure 4-18. Typical Pretriggered Acquisition
- Figure 4-19. SCANCLK Signal Timing
- Figure 4-20. EXTSTROBE* Signal Timing
- Figure 4-21. TRIG1 Input Signal Timing
- Figure 4-22. TRIG1 Output Signal Timing
- Figure 4-23. TRIG2 Input Signal Timing
- Figure 4-24. TRIG2 Output Signal Timing
- Figure 4-25. STARTSCAN Input Signal Timing
- Figure 4-26. STARTSCAN Output Signal Timing
- Figure 4-27. CONVERT* Input Signal Timing
- Figure 4-28. CONVERT* Output Signal Timing
- Figure 4-29. SISOURCE Signal Timing
- Figure 4-30. WFTRIG Input Signal Timing
- Figure 4-31. WFTRIG Output Signal Timing
- Figure 4-32. UPDATE* Input Signal Timing
- Figure 4-33. UPDATE* Output Signal Timing
- Figure 4-34. UISOURCE Signal Timing
- Figure 4-35. GPCTR0_SOURCE Signal Timing
- Figure 4-36. GPCTR0_GATE Signal Timing in Edge Detection Mode
- Figure 4-37. GPCTR0_OUT Signal Timing
- Figure 4-38. GPCTR1_SOURCE Signal Timing
- Figure 4-39. GPCTR1_GATE Signal Timing in Edge Detection Mode
- Figure 4-40. GPCTR1_OUT Signal Timing
- Figure 4-41. GPCTR Timing Summary
- Figure B-1. 68 Pin E Series Connector Pin Assignments
- Figure B-2. 68 Pin Extended Digital Input Connector Pin Assignments
- Figure B-3. 50 Pin E Series Connector Pin Assignments
- Figure B-4. 50-Pin Extended Digital Input Connector Pin Assignments
- Tables
- Table 3-1. Available Input Configurations
- Table 3-2. Measurement Precision
- Table 3-3. Pins Used by PXI E Series Device
- Table 4-1. I/O Connector Details
- Table 4-2. I/O Connector Signal Descriptions
- Table 4-3. I/O Signal Summary
- Table 4-4. Port C Signal Assignments
- Table 4-5. Signal Names Used in Timing Diagrams
Index
© National Instruments Corporation I-9 6023E/6024E/6025E User Manual
physical, A-18
power requirements, A-17
timing I/O, A-16 to A-17
triggers, A-17
STARTSCAN signal, 4-36 to 4-38
STB* signal
description (table), 4-25
mode 1 input timing (figure), 4-27
mode 2 bidirectional timing (figure), 4-29
storage environment specifications, PCI and
PXI buses, A-10
system integration, by National
Instruments, D-1
T
technical support resources, D-1
timing connections, 4-30 to 4-49
DAQ timing connections, 4-32 to 4-40
AIGATE signal, 4-39
CONVERT*signal,4-38to4-39
EXTSTROBE* signal, 4-33 to 4-34
SCANCLK signal, 4-33
SISOURCE signal, 4-40
STARTSCAN signal, 4-36 to 4-38
TRIG1 signal, 4-34 to 4-35
TRIG2 signal, 4-35 to 4-36
typical posttriggered acquisition
(figure), 4-32
typical pretriggered acquisition
(figure), 4-33
general-purpose timing signal
connections,4-43to4-49
FREQ_OUT signal, 4-49
GPCTR0_GATE signal, 4-44 to 4-45
GPCTR0_OUT signal, 4-45
GPCTR0_SOURCE signal,
4-43 to 4-44
GPCTR0_UP_DOWN signal, 4-45
GPCTR1_GATE signal, 4-46 to 4-47
GPCTR1_OUT signal, 4-47
GPCTR1_SOURCE signal, 4-46
GPCTR1_UP_DOWN
signal, 4-47 to 4-49
overview, 4-30
programmable function input
connections, 4-31 to 4-32
timing I/O connections (figure), 4-31
waveform generation timing
connections, 4-40 to 4-43
UISOURCE signal, 4-42 to 4-43
UPDATE* signal, 4-41 to 4-42
WFTRIG signal, 4-40 to 4-41
timing I/O
common questions, C-3 to C-5
specifications
PCI and PXI buses, A-8
PCMCIA bus, A-16 to A-17
timing signal routing, 3-7 to 3-11
CONVERT* signal routing (figure), 3-8
device and RTSI clocks, 3-9
programmable function inputs, 3-8 to 3-9
RTSI triggers, 3-9 to 3-11
timing specifications, 4-25 to 4-29
mode 1 input timing (figure), 4-27
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
signal names used in diagrams
(table), 4-25 to 4-26
TRIG1 signal, 4-34 to 4-35
TRIG2 signal, 4-35 to 4-36
trigger specifications
PCI and PXI buses
digital trigger, A-9
RTSI trigger, A-9
PCMCIA bus, A-17
digital trigger, A-17
triggers, RTSI. See RTSI trigger lines.