DAQ 6023E/6024E/6025E Multifunction I/O Devices User Manual
Table Of Contents
- 6023E/6024E/6025E User Manual
- Support
- Important Information
- Contents
- About This Manual
- Chapter 1 Introduction
- Chapter 2 Installation and Configuration
- Chapter 3 Hardware Overview
- Chapter 4 Signal Connections
- I/O Connector
- Analog Input Signal Overview
- Analog Input Signal Connections
- Analog Output Signal Connections
- Digital I/O Signal Connections
- Programmable Peripheral Interface (PPI)
- Power Connections
- Timing Connections
- Field Wiring Considerations
- Chapter 5 Calibration
- Appendix A Specifications
- Appendix B Custom Cabling and Optional Connectors
- Appendix C Common Questions
- Appendix D Technical Support Resources
- Glossary
- Index
- Figures
- Figure 1-1. The Relationship Between the Programming Environment, NI-DAQ, and Your Hardware
- Figure 3-1. PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E Block Diagram
- Figure 3-2. DAQCard-6024E Block Diagram
- Figure 3-3. Dithering
- Figure 3-4. CONVERT* Signal Routing
- Figure 3-5. PCI RTSI Bus Signal Connection
- Figure 3-6. PXI RTSI Bus Signal Connection
- Figure 4-1. I/O Connector Pin Assignment for the 6023E/6024E
- Figure 4-2. I/O Connector Pin Assignment for the 6025E
- Figure 4-3. Programmable Gain Instrumentation Amplifier (PGIA)
- Figure 4-4. Summary of Analog Input Connections
- Figure 4-5. Differential Input Connections for Ground Referenced Signals
- Figure 4-6. Differential Input Connections for Nonreferenced Signals
- Figure 4-7. Single Ended Input Connections for Nonreferenced or Floating Signals
- Figure 4-8. Single Ended Input Connections for Ground Referenced Signals
- Figure 4-9. Analog Output Connections
- Figure 4-10. Digital I/O Connections
- Figure 4-11. Digital I/O Connections Block Diagram
- Figure 4-12. DIO Channel Configured for High DIO Power-up State with External Load
- Figure 4-13. Timing Specifications for Mode 1 Input Transfer
- Figure 4-14. Timing Specifications for Mode 1 Output Transfer
- Figure 4-15. Timing Specifications for Mode 2 Bidirectional Transfer
- Figure 4-16. Timing I/O Connections
- Figure 4-17. Typical Posttriggered Acquisition
- Figure 4-18. Typical Pretriggered Acquisition
- Figure 4-19. SCANCLK Signal Timing
- Figure 4-20. EXTSTROBE* Signal Timing
- Figure 4-21. TRIG1 Input Signal Timing
- Figure 4-22. TRIG1 Output Signal Timing
- Figure 4-23. TRIG2 Input Signal Timing
- Figure 4-24. TRIG2 Output Signal Timing
- Figure 4-25. STARTSCAN Input Signal Timing
- Figure 4-26. STARTSCAN Output Signal Timing
- Figure 4-27. CONVERT* Input Signal Timing
- Figure 4-28. CONVERT* Output Signal Timing
- Figure 4-29. SISOURCE Signal Timing
- Figure 4-30. WFTRIG Input Signal Timing
- Figure 4-31. WFTRIG Output Signal Timing
- Figure 4-32. UPDATE* Input Signal Timing
- Figure 4-33. UPDATE* Output Signal Timing
- Figure 4-34. UISOURCE Signal Timing
- Figure 4-35. GPCTR0_SOURCE Signal Timing
- Figure 4-36. GPCTR0_GATE Signal Timing in Edge Detection Mode
- Figure 4-37. GPCTR0_OUT Signal Timing
- Figure 4-38. GPCTR1_SOURCE Signal Timing
- Figure 4-39. GPCTR1_GATE Signal Timing in Edge Detection Mode
- Figure 4-40. GPCTR1_OUT Signal Timing
- Figure 4-41. GPCTR Timing Summary
- Figure B-1. 68 Pin E Series Connector Pin Assignments
- Figure B-2. 68 Pin Extended Digital Input Connector Pin Assignments
- Figure B-3. 50 Pin E Series Connector Pin Assignments
- Figure B-4. 50-Pin Extended Digital Input Connector Pin Assignments
- Tables
- Table 3-1. Available Input Configurations
- Table 3-2. Measurement Precision
- Table 3-3. Pins Used by PXI E Series Device
- Table 4-1. I/O Connector Details
- Table 4-2. I/O Connector Signal Descriptions
- Table 4-3. I/O Signal Summary
- Table 4-4. Port C Signal Assignments
- Table 4-5. Signal Names Used in Timing Diagrams
Index
6023E/6024E/6025E User Manual I-8 ni.com
analog output, 4-19 to 4-20
digital I/O, 4-20 to 4-22
field wiring considerations, 4-49
I/O connectors, 4-1 to 4-8
exceeding maximum ratings
(warning), 4-1
I/O connector details (table), 4-1
I/O connector signal descriptions
(table),4-4to4-6
I/O signal summary (table),
4-7to4-8
pin assignments (figure), 4-2 to 4-3
I/O connectors, optional, B-2 to B-6
50-pin E Series connector pin
assignments (figure), B-5
50-pin extended digital input
connector pin assignments
(figure), B-6
68-pin E Series connector pin
assignments (figure), B-3
68-pin extended digital input
connector pin assignments
(figure), B-4
power connections, 4-30
Programmable Peripheral Interface
6025E only, 4-22 to 4-23
mode 1 input timing (figure), 4-27
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing
(figure), 4-29
Port C pin assignments, 4-23
power-upstate,4-24to4-25
signal names used in diagrams
(table), 4-25 to 4-26
timing specifications, 4-25 to 4-29
timing connections, 4-30 to 4-49
DAQ timing connections,
4-32 to 4-40
general-purpose timing signal
connections,4-43to4-49
programmable function input
connections, 4-31 to 4-32
waveform generation timing
connections, 4-40 to 4-43
signal sources, 4-8 to 4-9
floating signal sources, 4-9
ground-referenced signal sources, 4-9
single-ended connections, 4-17 to 4-19
floating signal sources (RSE
configuration), 4-18
grounded signal sources (NRSE
configuration), 4-18 to 4-19
when to use, 4-17
SISOURCE signal, 4-40
software installation, 2-1
software programming choices, 1-3 to 1-5
LabVIEW and LabWindows/CVI,
1-3to1-4
Measurement Studio software, 1-3 to 1-4
National Instruments application
software, 1-3 to 1-4
NI-DAQ driver software, 1-4 to 1-5
VirtualBench, 1-4
specifications
PCI and PXI buses
analog input, A-1 to A-4
analog output, A-4 to A-6
calibration, A-9
digital I/O, A-7 to A-8
operating environment, A-10
physical, A-9 to A-10
power requirement, A-9
storage environment, A-10
timing I/O, A-8
triggers, A-9
PCMCIA bus, A-11 to A-18
analog input, A-11 to A-14
analog output, A-14 to A-16
calibration, A-17
digital I/O, A-16
environment, A-18