GPIB-1014 User Manual March 1997 Edition Part Number 320030-01 © Copyright 1985, 1997 National Instruments Corporation. All Rights Reserved.
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Limited Warranty The GPIB-1014 is warranted against defects in materials and workmanship for a period of two years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
Warning Regarding Medical and Clinical Use of National Instruments Products National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer.
FCC/DOC Radio Frequency Interference Compliance This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual, may cause interference to radio and television reception. This equipment has been tested and found to comply with the following two regulatory agencies: Federal Communications Commission This device complies with Part 15 of the Federal Communications Commission (FCC) Rules for a Class A digital device.
Contents About This Manual ............................................................................................................ xiii Organization of This Manual ........................................................................................ xiii Conventions Used in This Manual ................................................................................ xiv Related Documentation .................................................................................................
Contents Register Description .......................................................................................... 4-2 Register Description Format ................................................................. 4-3 Interface Registers ......................................................................................................... 4-3 Data In Register (DIR) ...................................................................................... 4-6 Command/Data Out Register (CDOR)............
Contents Going from Standby to Active Controller ......................................................... 5-4 Going from Active to Idle Controller ................................................................ 5-5 The GPIB-1014 as GPIB Talker and Listener............................................................... 5-6 Programmed Implementation of Talker and Listener ....................................... 5-6 Addressed Implementation of the Talker and Listener .....................................
Contents 68450 DMAC ................................................................................................................ 6-14 DMAC Channel Operation................................................................................ 6-15 Initialization and Transfer Phases ......................................................... 6-15 Device (TLC)/DMAC Communication..................................... 6-15 DMA Requests ........................................................................
Contents Data Lines.......................................................................................................... E-2 Handshake Lines ............................................................................................... E-2 NRFD (not ready for data) .................................................................... E-2 NDAC (not data accepted) .................................................................... E-3 DAV (data valid) ...................................................
Contents Figure 6-3. Array Format for Linked Chaining Modes ...................................................... 6-21 Figure E-1. Figure E-2. Figure E-3. The GPIB Connector and Signal Assignments ................................................ E-4 Linear Configuration ........................................................................................ E-5 Star Configuration ............................................................................................
About This Manual The GPIB-1014 User Manual describes the mechanical and electrical aspects of the GPIB-1014, the data transfer features, and contains information concerning its operation and programming. Organization of This Manual The GPIB-1014 User Manual is organized as follows: • Chapter 1, Introduction, describes the GPIB-1014, lists the contents and optional equipment for your GPIB-1014 kit, and explains how to unpack the GPIB-1014 kit.
About This Manual • Appendix F, Mnemonics Key, contains a mnemonics key that defines the mnemonics (abbreviations) used throughout this manual for functions, remote messages, local messages, states, bits, registers, integrated circuits, system functions, and VMEbus operations and signals. • Appendix G, Customer Communication, contains forms for you to complete to facilitate communication with National Instruments concerning our products.
About This Manual • Motorola Semiconductor Technical Data MC68450 Advance Information Direct Memory Access Controller (DMAC) • Hitachi Microcomputer System HD68450 DMAC (Direct Memory Access Controller) Customer Communication National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them.
Chapter 1 Introduction This chapter describes the GPIB-1014, lists the contents and oiptional equipment for your GPIB-1014 kit, and explains how to unpack the GPIB-1014 kit. The GPIB-1014 is a high-performance IEEE 488 interface for the VMEbus. This interface permits IEEE 488 compatible engineering, scientific, or medical instruments to be controlled from a VMEbus-based computer.
Introduction Chapter 1 Figure 1-1 shows the GPIB-1014 interface board. Art not available in PDF version of document. Figure 1-1.
Chapter 1 Introduction The GPIB-1014 interface kit includes hardware and programming examples to implement the GPIB functions. Optional cables are supplied for interconnection with other devices on the GPIB.
Introduction Chapter 1 Unpacking Follow these steps when unpacking your GPIB-1014. 1. Verify that the pieces contained in the package you received match the kit parts list given earlier in this chapter. Do not remove the board from its plastic bag at this point. 2. Your GPIB-1014 board is shipped packaged in an antistatic plastic bag to prevent electrostatic damage to the board. Several components on the board can be damaged by electrostatic discharge.
Chapter 2 General Description This chapter contains the electrical specifications for the GPIB-1014, the data transfer features, and describes the characteristics of key interface board components. Electrical Characteristics All integrated circuit drivers and receivers used on the GPIB-1014 meet the requirements of the VMEbus specification and the IEEE 1014 standard.
General Description Chapter 2 Table 2-1. GPIB-1014 Signals (continued) Bus Signals Driver Device Part Number Receiver Device Part Number BR0*-BR3* AS756 LS241 BBSY* AS756 LS240 – LS240 IACKOUT* F1241 – IRQ1*-IRQ7* 74145 – – F1241 AS756 – – LS240 IACKIN* BERR* SYSFAIL* SYSRESET* All GPIB transceivers meet the requirements of the IEEE 488 standard.
Chapter 2 General Description to generate its board select signal. It then decodes the lowest eight lines, A8 through A1, to address the following items: • The 68450 DMA Controller (DMAC) • The µPD7210 GPIB Talker/Listener/Controller (TLC) • Two 8-bit, write-only Configuration Registers You can configure the base address of the board through the hardware jumper set W1 located on the interface board.
General Description Chapter 2 Table 2-3.
Chapter 2 General Description Table 2-3.
General Description Chapter 2 Memory addresses generated by the GPIB-1014 are 24 bits wide and the VMEbus Address Modifier Lines (AM5 through AM0) are fully programmable using function code registers located in the 68450 and three hardware jumpers (W3, W4, and W5). (See Chapter 3 for instructions on setting the hardware jumpers. See Chapter 4 for a description of the DMAC Function Code Registers.
Chapter 2 General Description Data Transfer Bus (DTB) Requester The GPIB-1014 arbitrates for the DTB before each DMA transfer. The board is designed for you to select, through software, one of four VMEbus request lines (BR0* through BR3*) using two bits in Configuration Register 1. To maximize the capabilities of the DTB, the board can be programmed to become a Release On Request (ROR) DTB master. Unless programmed, the GPIB-1014 is a Release When Done (RWD) master.
General Description Chapter 2 • GPIB Listener response time (DAV* low to NDAC* high) • GPIB Talker response time (NRFD* high to DAV* low) • GPIB-1014 transfer mode: Cycle Steal with hold, programmable timeout • T1 timing: high-speed Transfer rates of 250 to 350 kbytes/sec can be expected in typical systems, and rates up to 500 kbytes/sec can be achieved under optimum conditions. Programmed I/O Transfers The GPIB-1014 is able to transfer data to and from the GPIB using programmed I/O.
Chapter 2 General Description Device A VMEbus Computer with GPIB-1014 Able to Talk, Listen, and Control Frequency Counter Able to Talk Device B Printer Able to Listen Device C Digital Voltmeter Able to Talk and Listen 8 Lines Data Lines DIO1-DIO8 3 Lines Handshake Lines DAV (Data Valid) NRFD (Not Ready for Data) NDAC (Not Data Accepted) Management Lines 5 Lines IFC (Interface Clear) ATN (Attention) SRQ (Service Request) REN (Remote Enable) EOI (End or Identify) Figure 2-1.
General Description Chapter 2 R&D Lab Microprocessor Work Station IBM PC with GPIB-PC IEEE 488 Interface VMEbus Computer with GPIB-1014 IEEE 488 Interface GPIB-100 Bus Extender Up to 300 Meters (RS-422) Computer Center GPIB-100 Bus Extender Production & Testing PDP 11/44 with GPIB11-2 IEEE 488 Interface S-100 Computer GPIB-696P IEEE 488 Interface Figure 2-2.
Chapter 2 General Description Figure 2-3 is a block diagram of the GPIB-1014. Control Transceivers Timing State Machine Clock and Reset Circuitry Interrupter DTB Requester 68450 DMAC Data Transceivers Address Data DTB Control Transceivers Address Transceivers Address Decoding µPD7210 TLC GPIB Synchronization and Interrupt Control Configuration Registers DMA Gating and Control Data Transceivers GPIB Data Transfer Bus VMEbus Priority Interrupt DTB Arbitration Utility Figure 2-3.
General Description Chapter 2 The interface consists of these major components, which are discussed in greater detail in Chapter 6. • VMEbus Interface Consists of the buffers, drivers, and transceivers for the address, data, status, and control lines used on the VMEbus, plus other logic circuitry that converts internal signals to bus-compatible signals.
Chapter 2 General Description Table 2-5 lists the capabilities of the GPIB-1014 in terms of the IEEE 488 standard codes. Table 2-5.
General Description Chapter 2 Table 2-5.
Chapter 2 General Description • Receive control • Pass control • Conduct a Parallel Poll • Take control synchronously or asynchronously Table 2-6 contains the GPIB-1014 IEEE 1014 compliance levels. Table 2-6.
Chapter 3 Configuration and Installation This chapter describes the steps needed to configure and install the GPIB-1014 hardware.
Configuration and Installation Chapter 3 Figure 3-1 shows the locations of the GPIB-1014 configuration jumpers and switches. Art not available in PDF version of document. Figure 3-1.
Chapter 3 Configuration and Installation Access Mode The GPIB-1014 can be configured to respond to Supervisor (privileged) or User (non-privileged) access. Hardware jumper W2 is used to select the access mode that is automatically in effect upon a power-up or a system reset. The access mode then can be changed by software via a bit in Configuration Register 2. Figure 3-2 shows the placement of the jumper for the desired mode after a power-up or a system reset.
Configuration and Installation Chapter 3 Set Base Address Using Jumper Block W1 Move the jumper to the side labeled 1 to select a logical one for the corresponding address bit, or to the side labeled 0 to select a logical zero. Figure 3-3 shows the configuration for a base address 2000 (hex), which is the default address configured at the factory. 2 0 1 W1 0 15 BASE ADD 9 Figure 3-3.
Chapter 3 Configuration and Installation DMA Address Modifier Code Output During a DMA cycle, the GPIB-1014 sends out a 6-bit Address Modifier (AM) code to the VMEbus lines AM5 through AM0. The correct code is obtained by both programming the DMAC and setting jumpers W3, W4, and W5. Figure 3-4 shows the default settings of W3, W4, and W5.
Configuration and Installation Chapter 3 Table 3-1. Programming Values for Default Settings of W3, W4, and W5 AM Codes FCR Bits M2 through M0 29 000 2A 001 2D 100 2E 101 39 010 3A 011 3D 110 3E 111 If it is necessary to produce a code other than those listed in Table 3-1, you can produce any arbitrary AM code by changing jumpers W3, W4, and W5 along with programming the DMAC.
Chapter 3 Configuration and Installation For example, to produce an AM code of 17 hex (a binary value of 010111), complete the following steps: 1. Set jumper W3 to 0. 2. Set jumper W4 to 0. 3. Set jumper W5 to AM(1). 4. Write the pattern 00000111 to the FCR of the DMAC.
Configuration and Installation Chapter 3 Table 3-3. GPIB-1014 Pin Assignment on VMEbus Connector P1 Pin No. Signal Used Signal Not Used Pin No.
Chapter 3 Configuration and Installation Table 3-4. GPIB-1014 Pin Assignment on VMEbus Connector P2 Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Signal Used Signal Not Used CA15 CA13 CA11 CA9 Notes Pin No.
Configuration and Installation Chapter 3 Cabling Two options are available for GPIB I/O from the GPIB-1014: • A Front Panel Plug-In Connector • A VMEbus P2 Connector The Model GPIB-1014-1 interface board has a standard 24-pin IEEE 488 connector on the front panel of the board. A standard GPIB cable can plug in directly to this connector.
Chapter 4 Register Bit Descriptions This chapter contains a description of the register map, a list of interface registers, and a description of the DMA registers. Register Map The register map for the GPIB-1014 is shown in Table 4-1. This table gives the register name, the register address, the register size in bits, and the register type (read only, write only, or read and write). Note: For the sake of brevity, only Channel 0 addresses for the DMA Register Group are listed in Table 4-1.
Register Bit Descriptions Chapter 4 Table 4-1.
Chapter 4 Register Bit Descriptions Register Description Format The remainder of this chapter discusses each of the GPIB-1014 registers in the order shown in Table 4-1. Each register group is introduced, followed by a detailed bit description of each register. The register bit map shows a diagram of the register with the most significant bit (bit 15 for a 16-bit register, bit 7 for an 8-bit register) shown on the left, and the least significant bit (bit 0) shown on the right.
Register Bit Descriptions Chapter 4 Interface Registers Twenty-one GPIB Interface registers, eight of which are readable and 13 of which are writable, are located within the NEC µPD7210 Talker/Listener/Controller (TLC) integrated circuit. Each of the 21 interface registers is addressed relative to the GPIB-1014 VMEbus base address. Figures 4-1 and 4-2 show the register and bit mnemonics of each TLC internal register, its read/write accessibility, and its relative address.
Chapter 4 Register Bit Descriptions Bit 7 Bit 6 Legend (Contents of Read Register) Bit Bit Bit Bit 5 4 3 2 Bit 1 Bit 0 (Contents of Write Register) Address Offset (hex) DIR +111 +113 IMR1 ISR2 +115 SPSR +117 SPMR ADSR +119 ADMR +11B AUXMR ADR0 +11D ADR ADR1 EOSR CPT +11F DI6 DI5 CDO6 CDO5 APT DI4 DI3 DI2 DI1 INT SRQI DET END RX DEC LOK DI0 CDO4 CDO3 CDO2 CDO1 CDO0 ERR DO CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE 0 IMR2 CPTR DI7 CDO7 CDOR ISR1 Read/ Write CO REM
Register Bit Descriptions Chapter 4 Control Code +11B AUXMR CNT2 CNT1 Command Code CNT0 COM4 COM3 COM2 COM1 COM0 When CNT2-CNT0 is: 0 0 1 W ICR is loaded with: 0 CLK3 CLK2 CLK1 CLK0 PPR is loaded with: 0 1 1 U S P3 P2 P1 AUXRA is loaded with: 1 0 0 BIN XEOS REOS HLDE HLDA AUXRB is loaded with: 1 0 1 1 1 0 ISS 0 CPT SPEOI ENABLE AUXRE is loaded with: INV TRI 0 0 DHDC DHDT Figure 4-2.
Chapter 4 Register Bit Descriptions Data In Register (DIR) VMEbus Address: Base Address + 111 (hex) Attributes: Read Only, Internal to TLC 7 6 5 DI7 DI6 DI5 4 DI4 3 2 1 0 DI3 DI2 DI1 DI0 R The Data In Register (DIR) is used to move data from the GPIB to the computer when the interface is a Listener. The GPIB Ready For Data (RFD) message is held false until the byte is removed from the DIR, either by a DMA transfer to the VMEbus memory or by an I/O read from a VMEbus master.
Register Bit Descriptions Chapter 4 Command/Data Out Register (CDOR) VMEbus Address: Base Address + 111 (hex) Attributes: Write Only, Internal to TLC 7 6 5 4 3 2 1 0 CDO7 CDO6 CDO5 CDO4 CDO3 CDO2 CDO1 CDO0 The Command/Data Out Register (CDOR) is used to move data from the VMEbus to the GPIB when the interface (TLC) is the GPIB Talker or the Active Controller. Outgoing data is separately latched by this register and is not destroyed by a read from the DIR.
Chapter 4 Register Bit Descriptions Interrupt Status Register 1 (ISR1) VMEbus Address: Base Address + 113 (hex) Attributes: Read Only, Internal to TLC Bits are cleared when read Interrupt Mask Register 1 (IMR1) VMEbus Address: Base Address + 113 (hex) Attributes: Write Only, Internal to TLC 7 6 5 4 3 2 CPT CPT IE APT APT IE DET DET IE END RX END IE DEC DEC IE ERR ERR IE 1 0 DO DO IE R DI DI IE W The Interrupt Status Register 1 (ISR1) is composed of eight Interrupt Status bits.
Register Bit Descriptions Bit Mnemonic Chapter 4 Description undefined: GPIB command not automatically recognized and executed by TLC ACDS: GPIB Accept Data State CPT ENABLE: AUXRB[0]w UDPCF: Undefined Primary Command Function SCG: GPIB Secondary Command Group message pon: Power On Reset TAG: GPIB Talk Address Group message LAG: GPIB Listen Address Group message read ISR1: Bit is cleared immediately after it is read UDPCF is set on: [UCG + ACG & (TADS + LADS)] & undefined & ACDS & CPT ENABLE UDPCF is c
Chapter 4 Bit Register Bit Descriptions Mnemonic Description SCG: ACDS: pon: Read ISR1: GPIB Secondary Command Group GPIB Accept Data State Power On Reset Bit is cleared immediately after it is read The APT bit indicates that a secondary GPIB address has been received and is available in the CPTR for inspection Note: The application program must check this bit when using TLC address mode 3.
Register Bit Descriptions Bit Mnemonic Chapter 4 Description EOS: REOS: ACDS: pon: read ISR1: GPIB END Of String message Reception of GPIB EOS allowed, AUXRA[2]w GPIB Accept Data State Power On Reset Bit is cleared immediately after it is read The END RX bit is set when the TLC is a Listener and the GPIB uniline message, END, is received with a data byte from the GPIB Talker, or the data byte in the DIR matches the contents of the End Of String Register (EOSR).
Chapter 4 Bit Register Bit Descriptions Mnemonic Description write CDOR: Bit is set immediately after writing to the Command/Data Out Register SDYS to SIDS: Transition from GPIB Source Delay State to Source Idle State pon: Power On Reset read ISR1; Bit is cleared immediately after it is read The ERR bit indicates that the contents of the CDOR have been lost.
Register Bit Descriptions Bit Mnemonic Chapter 4 Description Notes LACS: ACDS: continuous mode: pon: read ISR1: finish Handshake: Holdoff mode: read DIR: GPIB Listener Active State GPIB Accept Data State Listen in continuous mode auxiliary command in effect Power On Reset Bit is cleared immediately after it is read Finish Handshake auxiliary command issued RFD Holdoff state Read Data In Register The DI bit indicates that the TLC, as a GPIB Listener, has accepted a data byte from the GPIB Talker.
Register Bit Descriptions Chapter 4 Interrupt Status Register 2 (ISR2) VMEbus Address: Base Address + 115 (hex) Attributes: Read Only, Internal to TLC Bits are cleared when read Interrupt Mask Register 2 (IMR2) VMEbus Address: Base Address + 115 (hex) Attributes: Write Only, Internal to TLC 7 6 5 4 3 2 INT 0 SRQI SRQI IE LOK DMAO REM DMAI CO CO IE LOKC LOKC IE 1 REMC REMC IE 0 R ADSC ADSC IE W The Interrupt Status Register 2 (ISR2) consists of six Interrupt Status bits and two TLC
Bit Mnemonic Description ERR IE: END RX: END IE: DEC: DEC IE: DO: DO IE: DI: DI IE: SRQI: SRQI IE: REMC: REMC IE: CO: CO IE: LOKC: LOKC IE: ADSC: ADSC IE: 7w 0 Enable Interrupt on Error Bit End Received Bit Enable Interrupt on End Received Bit Device Clear Bit Enable Interrupt on Device Clear Bit Data Out Bit Enable Interrupt on Data Out Bit Data In Bit Enable Interrupt on Data In Bit Service Request Input Bit Enable Interrupt on Service Request Input Bit Remote Change Bit Enable Interrupt on Remote Ch
Register Bit Descriptions Chapter 4 Bit Mnemonic Description 5r LOK Lockout Bit LOK is used, along with the REM bit, to indicate the status of the TLC GPIB Remote/Local (RL) function. If set, the LOK bit indicates that the TLC is in Local With Lockout State (LWLS) or Remote With Lockout State (RWLS). LOK is a Non-Interrupt bit. 5w DMAO DMA Out Enable Bit The DMAO bit must be set to allow data transfers from VMEbus memory to the CDOR.
Bit Mnemonic Description 2r 2w LOKC LOKC IE Lockout Change Bit Lockout Change Interrupt Enable Bit LOKC is set by: any change in LOK LOKC is cleared by: pon + (read ISR2) Notes LOK: ISR2[5]r pon: Power On Reset read ISR2: Bit is cleared immediately after it is read LOKC is set when there is a change in the LOK bit, ISR2[5]r, (REMS +RELS).
Register Bit Descriptions Bit Mnemonic Chapter 4 Description Notes TA: LA: CIC: MJMN: lon: ton: pon: read ISR2: ADSR: ADMR: Talker Active bit, ADSR[1]r Listener Active bit, ADSR[2]r Controller-In-Charge bit, ADSR[7]r Major/Minor bit, ADSR[0]r Listen Only bit, ADMR[6]w Talk Only bit, ADMR[7]w Power On Reset Bit is cleared immediately after it is read Address Status Register Address Mode Register ADSC is set when there is a change in one of the four bits–TA, LA, CIC, or MJMN–of the Address Status Regist
Serial Poll Status Register (SPSR) VMEbus Address: Base Address + 117 (hex) Attributes: Read Only, Internal to TLC Serial Poll Mode Register (SPMR) VMEbus Address: Base Address + 117 (hex) Attributes: Write Only, Internal to TLC 7 6 5 4 3 2 1 S8 S8 PEND rsv S6 S6 S5 S5 S4 S4 S3 S3 S2 S2 0 R S1 S1 W Bit Mnemonic Description 7r 7w, 5-0r, 5-0w S8 Serial Poll Status Bit 8 S[6-1] Serial Poll Status Bits 6 through 1 Cleared by Power On Reset (pon), and by issuing the Chip Reset aux
Register Bit Descriptions Chapter 4 Address Status Register (ADSR) VMEbus Address: Base Address + 119 (hex) Attributes: Read Only, Internal to TLC 7 6 5 4 3 CIC ATN* SPMS LPAS TPAS 2 1 0 LA TA MJMN R The Address Status Register (ADSR) contains information that can be used to monitor the TLC GPIB address status.
Bit Mnemonic Description 3r TPAS Talker Primary Addressed State Bit TPAS is used when the TLC is configured for extended GPIB addressing, and, when set, indicates that the TLC has received its primary GPIB talk address. In extended mode addressing (mode 3 addressing), TPAS=1 indicates that the secondary address being received as the next GPIB command message can represent the TLC extended (secondary) GPIB talk address.
Register Bit Descriptions Chapter 4 Address Mode Register (ADMR) VMEbus Address: Base Address + 119 (hex) Attributes: Write Only, Internal to TLC 7 6 5 4 3 2 1 0 ton 1on TRM1 TRM0 0 0 ADM1 ADM0 W Bit Mnemonic Description 7w ton Talk Only Bit By setting ton programs, the TLC becomes a GPIB Talker. If ton is set, the lon, ADM1, and ADM0 bits must be cleared. This method must be used in place of the addressing method when the TLC will be only a Talker.
Bit Mnemonic Description 1-0w ADM[1-0] Address Mode Bits 1 through 0 These bits state the addressing mode currently in effect–that is, the manner in which the information in ADR0 and ADR1 is interpreted (see Address Register 0 and Address Register 1 later in this chapter). If both bits are zero, then the TLC does not respond to GPIB address commands. Instead, the ton and lon bits are used to program the Talker and Listener functions, respectively.
Register Bit Descriptions Bit Mnemonic Chapter 4 Description ADM0 and ADM1 must be cleared when either of the two programmable bits ton or lon is set. For more information on the different addressing modes supported by the GPIB-1014, refer to the Addressed Implementation of Talker and Listener section in Chapter 5.
Command Pass Through Register (CPTR) VMEbus Address: Base Address + 11B (hex) Attributes: Read Only, Internal to TLC Bit 7-0r 7 6 5 4 3 2 1 CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 Mnemonic CPT[7-0] 0 R CPT0 Description Command Pass Through Bits 7 through 0 These bits are used to transfer undefined multiline GPIB command messages from the GPIB DIO lines to the computer.
Register Bit Descriptions Chapter 4 Table 4-3.
Auxiliary Mode Register (AUXMR) VMEbus Address: Base Address + 11B (hex) Attributes: Write Only, Internal to TLC Permits Access to Hidden Registers 7 6 5 4 3 2 1 0 CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0 W The Auxiliary Mode Register (AUXMR) is used to issue auxiliary commands.
Register Bit Descriptions Chapter 4 Table 4-4.
Table 4-5 shows the functions that are executed when the AUXMR Control Code (CNT2 through CNT0) is loaded with 000 (binary) and the Command Code (COM4 through COM0) is loaded. Table 4-5.
Register Bit Descriptions Chapter 4 Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code (COM4-COM0) 4 3 2 1 0 0 0 0 1 1 Description Finish Handshake (FH) The Finish Handshake command finishes a GPIB Handshake that was stopped because of a Holdoff on RFD or DAC. 0 0 1 0 0 Trigger Note: Trigger cannot be used with the GPIB-1014. The Trigger command generates a high pulse on the TRIG pin (T/R3 pin when TRM1=0) of the TLC.
Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code (COM4-COM0) 4 3 2 1 0 0 0 0 0 1 0 1 0 0 1 Description Clear Parallel Poll Flag Set Parallel Poll Flag These commands set the Parallel Poll Flag to the value of COM3. The value of the Parallel Poll Flag is used as the local message ist when bit four of Auxiliary Register B is zero. The value of SRQS is used as the ist when ISS=1.
Register Bit Descriptions Chapter 4 Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code (COM4-COM0) 4 3 2 1 0 Description 1 1 0 1 1 (continued) In continuous mode, the local message rdy is issued when the Acceptor Not Ready State (ANRS) is initiated unless data block transfer end is detected (END RX bit equals one). When END is detected, the TLC is placed in the RFD Holdoff state, preventing generation of the rdy message.
Chapter 4 Register Descriptions Hidden Registers The hidden registers are loaded through the Auxiliary Mode Register (AUXMR). AUXMR[7-5] is loaded with the hidden register number, and AUXMR[4-0] is loaded with the data to be transferred to the hidden register. The hidden registers cannot be read, and in some cases the contents are setable only; that is, they can be cleared or reset to initialized conditions only by issuing the Chip Reset auxiliary command, by a Power On Reset, or by LMR (CR0[2]w).
Register Descriptions Chapter 4 Internal Counter Register (ICR) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 001 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC Accessed through AUXMR 4 3 2 1 0 0 CLK3 CLK2 CLK1 CLK0 W Bit Mnemonic Description 4w 0 Reserved Bit Write zero to this bit.
Chapter 4 Register Descriptions Parallel Poll Register (PPR) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 011 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC Accessed through AUXMR 4 3 2 1 0 U S P3 P2 P1 W This 5-bit command code determines the manner in which the TLC responds to a Parallel Poll. When using the remote Parallel Poll Configure (IEEE 488 capability code PP1), do not write to the PPR.
Register Descriptions Chapter 4 Bit Mnemonic Description 3w S Status Bit Polarity (Sense) Bit The S bit is used to indicate the polarity (or sense) of the TLC local ist message. If S=1, the status is in phase, meaning that if, during a Parallel Poll response, S=ist=1, and U=0, the TLC responds to the Parallel Poll by driving one of the eight GPIB DIO lines low, thus asserting it to a logic one. If S=1 and ist=0, the TLC does not drive the DIO line.
Chapter 4 Register Descriptions Auxiliary Register A (AUXRA) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 100 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC Accessed through AUXMR 4 3 2 1 0 BIN XEOS REOS HLDE HLDA W Writing to Auxiliary Register A (AUXRA) is done via the AUXMR. Writing the binary value 100 into the Control Code (CNT[2-0]) and a bit pattern into the Command Code (COM[4-0]) portion of the AUXMR causes the Command Code to be written to AUXRA.
Register Descriptions Chapter 4 Bit Mnemonic Description 1-0w HLDE HLDA Holdoff on End Bit Holdoff on All Bit HLDE and HLDA together determine the GPIB data receiving mode. The four possible modes are as follows: HLDE HLDA 0 0 1 1 0 1 0 1 Data Receiving Mode Normal Handshake RFD Holdoff on All Data RFD Holdoff on END Continuous In Normal Handshake mode, the local message rdy is generated when data is received from the GPIB.
Chapter 4 Register Descriptions Auxiliary Register B (AUXRB) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 101 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC Accessed through AUXMR 4 3 2 1 ISS INV TRI SPEOI 0 CPT ENABLE W Writing to Auxiliary Register B (AUXRB) is done via the AUXMR. Writing the value 101 into the Control Code (CNT[2-0]) and a bit pattern into the Command Code portion (COM[4-0]) of the AUXMR causes the Command Code to be written to AUXRB.
Register Descriptions Chapter 4 Bit Mnemonic Description 2w TRI Three-State Timing Bit The TRI bit determines the TLC GPIB Source Handshake Timing, T1. TRI can be set to enable high-speed data transfers (T1 ≥ 500 nsec) when tri-state GPIB drivers are used. (The GPIB-1014D uses tri-state GPIB drivers except during Parallel Poll responses, in which case the GPIB drivers automatically switch to Open Collector.
Chapter 4 Register Descriptions Auxiliary Register E (AUXRE) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 110 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLC Accessed through AUXMR 4 3 2 1 0 0 0 0 DHDC DHDT W Writing to Auxiliary Register E (AUXRE) is done via the AUXMR. Writing the binary value 110 into the Control Code (CNT[2-0]) and a bit pattern into the the lower five bits of the AUXMR (COM[4-0]) causes the two lowest order bits to be written to AUXRE.
Register Descriptions Chapter 4 Address Register 0 (ADR0) VMEbus Address: Base Address + 11D (hex) Attributes: Read Only, Internal to TLC 7 6 5 4 3 2 1 0 X DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0 R Address Register 0 (ADR0) reflects the internal GPIB address status of the TLC as configured using the ADMR. In addressing mode 2, ADR0 indicates the address and enable bits for the primary GPIB address of the TLC.
Chapter 4 Register Descriptions Address Register (ADR) VMEbus Address: Base Address + 11D (hex) Attributes: Write Only, Internal to TLC 7 6 5 4 3 2 1 0 ARS DT DL AD5 AD4 AD3 AD2 AD1 W The Address Register (ADR) is used to load the internal registers ADR0 and ADR1. Both ADR0 and ADR1 must be loaded for all addressing modes.
Register Descriptions Chapter 4 Address Register 1 (ADR1) VMEbus Address: Attributes: Base Address + 11F (hex) Read Only, Internal to TLC 7 6 5 4 3 2 1 0 EOI DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1 R Address Register 1 (ADR1) indicates the status of the GPIB address and enable bits for the secondary address of the TLC if mode 2 addressing is used, or the minor primary address of the TLC if dual-primary addressing is used (modes 1 and 3).
Chapter 4 Register Descriptions End of String Register (EOSR) VMEbus Address: Base Address + 11F hex Attributes: Write Only, Internal to TLC 7 6 5 4 3 2 EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 1 EOS1 0 EOS0 W The End Of String Register (EOSR) holds the byte used by the TLC to detect the end of a GPIB data block transfer. A 7- or 8-bit byte (ASCII or binary) can be placed in the EOSR to be used in detecting the end of a block of data.
Register Descriptions Chapter 4 DMA Registers The onboard DMA Controller is a 68450 DMAC. This chip is extremely flexible and uses four independent DMA channels. The DMAC can support single address (flyby) transfers or dual address (flowthrough) transfers. The GPIB-1014 uses two channels (Channel 0 and 1) for 8-bit flyby DMA transfers between VMEbus memory and the GPIB. All four channels are available for 8- or 16-bit flowthrough memory-to-memory DMA transfers.
Chapter 4 Register Descriptions Key Null Bit Position. * The GCR is located at FF only.
Register Descriptions Chapter 4 The following paragraphs describe the channel configuration and status registers. More information on the 68450 can be found in the Motorola Semiconductor Technical Data MC68450 Advance Information Direct Memory Access Controller (DMAC) or the Hitachi Microcomputer System HD68450 DMAC (Direct Memory Access Controller). Each channel contains the same status and configuration registers.
Chapter 4 Register Descriptions Transfer Count Registers The Memory Transfer Counter Register (MTCR) and the Base Transfer Counter Register (BTCR) are 16-bit registers. The MTCR is used to specify how many operands will be transferred. (An operand can be either a byte (8 bits) or a word (16 bits)). This register is loaded prior to starting the channel and will be decremented with each operand transfer.
Register Descriptions Chapter 4 Function Code Registers VMEbus Address: Base Address + 29 (hex) for Memory Function Code Base Address + 31 (hex) for Device Function Code Base Address + 39 (hex) for Base Function Code Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 1 0 X X X X X M2 M1 M0 R/W On each of the four DMAC channels, there are three Function Code Registers (FCRs) associated with the three address registers (MAR, DAR, and BAR). The three FCRs are MFCR, DFCR, and BFCR.
Chapter 4 Register Descriptions Device Control Register VMEbus Address: Base Address + 04 (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 XRM DTYP 3 2 DPS 0 1 0 PCL R/W The Device Control Register (DCR) is a device-soriented control register. Bit Mnemonic Description 7-6r/w XRM External Request Mode Bits 7 through 6 The External Request Mode bits indicate whether the channel is in cycle steal or cycle steal with hold transfer mode.
Register Descriptions Chapter 4 Bit Mnemonic Description 2r/w 0 Reserved Bit Write a zero to this bit. 1-0r/w PCL Peripheral Control Line Bits 1 through 0 Each of the four DMAC channels has a Peripheral Control Line (called PCL0* through PCL3*). The two PCL bits define the function of each line. The GPIB-1014 uses the four lines as status inputs. On PCL0*, GPIB signal SRQ* is connected. On PCL2*, signal REN* is connected.
Chapter 4 Register Descriptions Operation Control Register VMEbus Address: Base Address + 05 (hex) Attributes: Read/Write, Internal to DMAC 7 6 DIR 0 5 4 3 SIZE 2 CHN 1 0 REQG R/W The Operation Control Register (OCR) is an operation-oriented register.
Register Descriptions Chapter 4 10 = Array Chaining 11 = Linked Chaining Bit Mnemonic Description In most GPIB applications, either no chaining or array chaining is used. See Chapter 5 for details. 1-0r/w REQG DMA Request Generation Bits 1 through 0 The DMA Request Generation method bits define how requests for transfers are generated. For the GPIB-to-memory DMA transfers, the request mode is always 10 (the REQ line initiates an operand transfer).
Chapter 4 Register Descriptions Sequence Control Register VMEbus Address: Base Address + 06 (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 0 0 0 0 3 2 MAC 1 0 DAC R/W The Sequence Control Register (SCR) is used to define the sequencing of memory and device addresses. Bit Mnemonic Description 7-4r/w 0 Reserved Bits Write zeros to these bits.
Register Descriptions Chapter 4 Channel Control Register VMEbus Address: Base Address + 07 (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 1 0 STR CNT HLT SAB EINT 0 0 0 R/W This register is used to control the operation of the channel. By writing to this register, a channel operation can be started and set to be continued, halted, and aborted. Also, the channel can be enabled to issue interrupts when an operation is terminated (normal or error termination).
Chapter 4 Register Descriptions Bit Mnemonic 0 = Channel operation not aborted 1 = Abort channel operation Description 3r/w EINT Interrupt Enable Bit The Interrupt Enable bit in used to enable or disable interrupts from the channel. GPIB-1014 interrupts are discussed in more detail in Chapter 5. 0 1 2-0r/w 0 = No interrupts enabled = Interrupts enabled Reserved Bits Write zeros to these bits.
Register Descriptions Chapter 4 Channel Status Register VMEbus Address: Base Address + 00 (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 1 0 COC BTC NDT ERR ACT 0 PCT PCS R/W The Channel Status Register (CSR) bits are set automatically by DMAC. Bits are cleared by writing a one (1) to each register bit or by resetting the DMAC. Bit Mnemonic Description 7r/w COC Channel Operation Complete bit The Channel Operation Complete bit is set if the DMA transfer has completed.
Chapter 4 Register Descriptions Bit Mnemonic Description 4r/w ERR Error Bit The Error bit is used to report the occurrence of error conditions. It is set if any errors have been signaled. If bit ERR is set, the CER logs the exact cause of the error. If this bit is cleared, the CER is also cleared. 0 1 3r/w ACT = No errors = Error as coded in CER Channel Active Bit The Channel Active bit is asserted after the channel has been started. The bit remains set until the channel operation terminates.
Register Descriptions Chapter 4 Channel Error Register VMEbus Address: Base Address + 01 (hex) Attributes: Read Only, Internal to DMAC 7 6 5 0 0 0 4 3 2 1 0 R ERROR CODE The Channel Error Register (CER) is an error condition register. The ERR bit of the CSR indicates if there is an error. Bits 0 through 4 of the CER indicate what type of error occurred.
Chapter 4 Register Descriptions Channel Priority Register VMEbus Address: Base Address + 2D (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 0 0 0 0 0 0 0 CP R/W The Channel Priority Register (CPR) is used to define the priority level for each channel. The priority of a channel is a number from 0 through 3, with 3 being the highest priority level. When multiple requests for DMA service are pending at the DMAC, the channel with the highest priority receives first service.
Register Descriptions Chapter 4 Interrupt Vector Registers Each channel has a Normal Interrupt Vector Register (NIVR) and an Error Interrupt Vector Register (EIVR), each consisting of eight bits. The CPU responds to an interrupt request from the DMAC by executing an Interrupt Acknowledge Cycle. The GPIB-1014 hardware detects this cycle and checks to see if the indicated priority matches its own programmable priority level (for the VMEbus this can be level 1 through 7).
Chapter 4 Register Descriptions General Control Register VMEbus Address: Base Address + FF (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 0 0 0 0 3 2 1 BT 0 BR R/W When the transfer mode is cycle steal with hold, the General Control Register (GCR) is used to define how long the DMAC, after transferring the last byte, will wait for another DMA request before relinquishing the bus. The DMAC will retain control of the bus unless the device (TLC) pauses.
Register Descriptions Chapter 4 Configuration Registers The GPIB-1014 contains two 8-bit write-only registers that are used to configure some of the board operating parameters. Configuration Register 1 (CFG1) VMEbus Address: Base Address + 101 (hex) Attributes: Write Only, Internal to DMAC 6 7 5 4 INTRQ 3 BRG 2 CC 1 ROR* 0 DIR W Configuration Register 1 (CFG1) is an 8-bit write-only register used to configure the GPIB-1014 parameters.
Chapter 4 Register Descriptions Bit Mnemonic Description 4-3w BRG Bus Request/Grant Bits The Bus Request/Grant bits are used to select which pair of the VMEbus request/grant lines are used by the GPIB-1014 to request and obtain control of the system bus. 00 01 10 11 = = = = BR0*/BG0IN*-BG0OUT* selected BR1*/BG1IN*-BG1OUT* selected BR2*/BG2IN*-BG2OUT* selected BR3*/BG3IN*-BG3OUT* selected BR0*/BG0IN*-BG0OUT* is selected automatically after power-up or after the board is reset.
Register Descriptions Chapter 4 Configuration Register 2 (CFG2) VMEbus Address: Base Address + 105 (hex) Attributes: Write Only, Internal to DMAC 7 6 5 4 3 2 1 0 0 0 0 0 SFL SUP LMR SC W Configuration Register 2 (CFG2) is an 8-bit write-only register that is used to set the board access mode, set the GPIB-1014 as System Controller, and drive the VMEbus SYSFAIL* line. It also contains a Local Master Reset bit that can be used to reset the GPIB-1014 to a known state.
Chapter 4 Register Descriptions Bit Mnemonic Description 1w LMR Local Master Reset Bit The Local Master Reset bit is used to reset the GPIB-1014 to a known state. Setting this bit to a 1 drives the local reset line active while clearing this bit releases the local reset line. The local reset line must be left in the active state for at least 10 msec to ensure that the onboard circuitry is reset properly.
Chapter 5 Programming Considerations This chapter explains the initialization process, sending/receiving messages, and the serial/parallel poll process. Additional information on programming the µPD7210 GPIB interface chip can be obtained from the µPD7210 GPIB-IFC User Manual by NEC Electronics U.S.A., Inc. More specific information on programming the 68450 DMAC chip can be obtained from Hitachi and Motorola technical data.
Programming Considerations • Chapter 5 The Transit Receive Mode 0 (TRM0) and Transit Receive Mode 1 (TRM1) bits in the Address Mode Register (ADMR) are cleared. All other TLC register contents should be considered as undefined while the LMR bit is set and after LMR has been cleared. While the TLC internal signal pon is set, all Auxiliary Mode Register (AUXMR) commands are cleared and cannot be executed. All other TLC registers can be programmed while pon is set.
Chapter 5 Programming Considerations 9. Load the Parallel Poll response in the Parallel Poll Register (PPR) if local configuration is used. If using remote configuration, clear the PPR. 10. Clear power on (pon) by issuing the Immediate Execute pon auxiliary command to the TLC to bring the TLC online. 11. Execute the desired TLC auxiliary commands. The registers associated with the 68450 DMAC do not need to be configured further until just prior to a DMA operation.
Programming Considerations Chapter 5 Sending Remote Multiline Messages (Commands) The GPIB-1014 sends commands as Active Controller simply by writing to the Command/Data Out Register (CDOR) in response to the CO status bit in ISR2. DMA transfers are not supported when the TLC is GPIB Active Controller, and should not be attempted. The TLC recognizes any commands applicable to itself, such as its own talk or listen address. Thus, to make the TLC a Listener, write its listen address to the CDOR.
Chapter 5 Programming Considerations Case 2: The TLC, as a Listener, takes control upon receipt of the Take Control Synchronously auxiliary command. If programmed I/O is used, the Take Control Synchronously auxiliary command should be issued between seeing a DI status bit and reading the last byte from the DIR. If DMA is used, a handshake holdoff must be in effect after the last data byte is read in order for the Take Control Synchronously auxiliary command to work properly.
Programming Considerations Chapter 5 The GPIB-1014 as GPIB Talker and Listener The TLC may be either GPIB Talker or Listener, but not both simultaneously. Either function is deactivated automatically if the other is activated. The TA, LA, and ATN* bits in the ADSR together indicate the specific state of the TLC.
Chapter 5 Programming Considerations Address Mode 2 Address Mode 2 is used when Talker Extended (TE) or Listener Extended (LE) functions are to be used. TE and LE functions require receipt of two addresses (primary and secondary) before setting TA or LA. The TLC GPIB primary address is indicated by the byte written to ADR0. The secondary address is indicated by the byte written to ADR1. Upon receipt of both the primary and secondary GPIB addresses, the TLC becomes an addressed Talker or Listener.
Programming Considerations Chapter 5 6. When the Valid auxiliary command is issued, the TLC assumes that the My Secondary Address (MSA) message has been received, which causes the following events to occur: • The LA bit to be set and the TA bit to be cleared (LADS=TIDS=1) if LPAS was set, or the TA bit to be set and the LA bit to be cleared (TADS=LIDS=1) if TPAS was set. • The GPIB DAC message to be sent true, and the GPIB handshake to be finished. 7.
Chapter 5 Programming Considerations In cycle steal without hold mode, upon receiving a DMA request from the TLC, the DMAC requests use of the VMEbus. Once the VMEbus is granted to the GPIB-1014, the DMAC performs the DMA transfer. Then it immediately releases the bus. In cycle steal with hold mode, after performing a DMA transfer, the DMAC will hold the VMEbus for a programmable time period waiting for another DMA request.
Programming Considerations Chapter 5 DMA Transfers without the Carry Cycle Channel 0 DMAC VMEbus interrupt Data Block A Data Block A OR PCL1 Data Block B TLC interrupt Bus Error GPIB Sync. Data Block C Total = N bytes NO CHAINING Total = N bytes CHAINING Figure 5-1. DMA Transfer without Carry Cycle If the carry cycle feature is not needed in a transfer sequence, little programming is needed.
Chapter 5 Programming Considerations b. A 0xFF (hex) must be written to the CSR of Channel 0 to clear any leftover error or status bits. c. The DCR of Channel 0 is loaded with the proper value to select the DMA transfer mode (cycle steal without hold or cycle steal with hold). The DTYP bits should be set to binary 10 (device with ACK*, implicitly addressed), the DPS bit must be set to 0 (8-bit port size), and the PCL bits should be set to binary 000 (status input).
Programming Considerations Chapter 5 4. For array or linked chaining, load the MFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the data blocks. See Tables 3-1 and 3-2 for recommended values. 5. Set up the data blocks and the address & transfer count array in VMEbus memory. Figures 6-1 and 6-2 describe how to set up the array for both chaining modes. Interrupts are generally not enabled for Channel 0.
Chapter 5 Programming Considerations DMA Transfers with the Carry Cycle Channel 1 Channel 0 Block A Data Block A (carry cycle byte) Data Block A OR Count=1 Data Bock B VMEbus interrupt TLC interrupt Bus Error GPIB Sync. Block B Data Block C (last data byte) Count=2 Total=N-1 bytes Total=N-1 bytes Carry Cycle byte + Nth data byte NO CHAINING CHAINING CHAINING (array or linked) (array or linked) Figure 5-2.
Programming Considerations Chapter 5 2. Channel 0 must be configured to provide a flyby transfer for the n-1 data bytes between the GPIB and the VME system memory. The sequence is as follows: a. Write the CCR of Channel 0 with the SAB bit set to abort the channel operation in case it is still active. b. Write a 0xFF (hex) to the CSR of Channel 0 to clear any remaining error or status bits. c.
Chapter 5 Programming Considerations • For array or linked chaining, load the MFCR of Channel 0 with the proper data to generate the required Address Modifier Code to access the data blocks. See Tables 3-1 and 3-2 for recommended values. • Set up the data blocks and the address & transfer count array in VMEbus memory. The total number of bytes in the data block should be n-1 bytes. Figures 6-1 and 6-2 describe how to set up the array for both chaining modes. h.
Programming Considerations Chapter 5 i. For array or linked chaining, load the MFCR of Channel 1 with the proper value to generate the desired address modifier code, which then accesses the data blocks. (See Tables 3-1 and 3-2 for recommended values.) Note: If you are using the array chaining mode, construct a special carry cycle array in memory. The array must begin at an even address and all addresses in the array must be even.
Chapter 5 Programming Considerations 4. Once channels 0 and 1 have been configured properly, start the DMA channels. Start Channel 1 before starting Channel 0. The channels are started by writing to the CCRs with the STR bits set. (Channel 1 should also have the EINT bit set if you are using interrupts.) 5. Finally, configure the TLC for a DMA operation. The sequence is as follows: a. Set the END IE bit in IMR1 if the TLC is a GPIB Listener. Set the ERR IE bit in IMR1 if the TLC is a GPIB Talker. b.
Programming Considerations Chapter 5 • An interrupt from the TLC • A bus or DMAC error that occurred during a DMA transfer • GPIB handshake synchronization To determine which condition caused the interrupt, you must first examine the CSR of Channel 1. If the ERR bit of Channel 1 is set, a DMAC error occurred while Channel 1 was transferring data. The CER of Channel 1 indicates the type of error that occurred.
Chapter 5 Programming Considerations accepted by all Listeners on the GPIB (indicating a GPIB synchronization). For this reason, Channel 1 is programmed to transfer two bytes to avoid a premature COC interrupt. After the last data byte (the nth byte) is transferred, the MTCR of Channel 1 contains a 1 and the next DMA request from the TLC is not allowed to reach the DMAC through onboard hardware. Channel 1 is still active, waiting for another request, but never detects one.
Programming Considerations Chapter 5 Whether terminating on the END message or the EOS message (or whenever the DMA transfer does not complete properly), the DMAC must be stopped by issuing a software abort to Channels 0 and 1 by writing to the CCR with the SAB bit set. You then must write to the CSR to clear the ERR flag set by the software abort. Using Programmed I/O Programming considerations for using programmed I/O data transfers are explained in the following paragraphs.
Chapter 5 Programming Considerations Interrupts If the GPIB-1014 is enabled for interrupts, there are three events that can cause an interrupt on the VMEbus. The first event is an interrupt from the TLC. The second event is a GPIB handshake synchronization that occurs when a DMA transfer is finished and the GPIB is synchronized. The last event is a bus error that occurs during a DMA transfer. Interrupts must be enabled in software to be recognized as described in the following paragraphs.
Programming Considerations Chapter 5 The TLC contains its own internal registers, which are used to control and enable interrupts. The interrupt output from the TLC, however, is sensed by the PCL of DMA Channel 1. If an interrupt operation is used, the DMAC Channel 1 must be configured to interrupt on a high-to-low transition of the PCL1. If the DMAC encounters a bus error during operation, a negative transition is caused on the PCL of Channel 1, thus causing an interrupt.
Chapter 5 Programming Considerations Serial Polls Conducting a Serial Poll The TLC, as CIC, can serial poll other devices as described in the IEEE 488 specification. From the programming point of view, the TLC must first become Active Controller to send the addressing and enabling commands to the device being polled, make itself a GPIB Listener by issuing the Listen auxiliary command, and then go to standby with the Go To Standby auxiliary command to read the status byte.
Programming Considerations Chapter 5 Although the Controller can obtain a Parallel Poll response quickly and at any time, there can be considerable front-end overhead during initialization to configure the devices to respond appropriately. This is contrasted with Serial Polls, where the overhead, in the form of addressing and enabling command messages, occurs with each poll. Conducting a Parallel Poll The TLC as Active Controller has the capability to conduct a Parallel Poll.
Chapter 5 Programming Considerations 2. Send the GPIB UNL message to unaddress all GPIB Listeners. 3. Send the listen address of the first device to be configured. 4. Send the GPIB PPC message to all devices followed by the PPE message for that device. 5. Repeat from the second step (UNL) for each additional device. Follow the same procedure to disable polling with PPD (for example, when changing responses during reconfiguration).
Chapter 6 Theory of Operation This chapter contains a functional overview of the GPIB-1014 board and explains the operation of each functional block making up the GPIB-1014. A brief description of the GPIB-1014 interface is given in Chapter 2 along with a functional block diagram (see Figure 2-4). The major elements of the GPIB-1014 are discussed in more detail in this chapter with references to signals and circuits shown in the schematic diagram in Appendix A.
Theory of Operation Chapter 6 accomplished using an F245 8-bit data transceiver, which gates the upper data byte to the TLC. This data transceiver is automatically controlled by the DMAC signal HIBYTE*. When the data transfer is on VMEbus data lines D07 through D00, the HIBYTE* is not active and the TLC data bus is connected to the lower eight bits of the VMEbus data bus.
Chapter 6 Theory of Operation Control Equations of Transceivers Table 6-1 lists the control equations for the address and data. Table 6-1.
Theory of Operation Chapter 6 address. If DS* from the master is also asserted, local signal BRDEN* is asserted. Further decoding is necessary to determine which register is being addressed. Eight data lines (A8 through A1) are latched by an AS573 8-bit register at the start of every slave cycle (that is, when AS* is low and DTACK* from the last cycle is high) to provide the address decoder with constant address information.
Chapter 6 Theory of Operation control the timing of local signal DTACK* when the board is a slave and signal to control RD* and WR* to the TLC (see Timing State Machine later in this chapter). The VMEbus signal SYSRESET* is monitored by the GPIB-1014. It is received with an LS240 receiver and is ORed with the LMR bit in CFG2 to generate the onboard RESET signal.
Theory of Operation Chapter 6 • Enabling the Release On Request feature. Writing a 0 to this bit (ROR*) enables the Release On Request feature while writing a 1 disables the Release On Request feature. This bit is set to 1 during reset or power up. This bit is used by the DTB Requester circuitry. • Selecting the direction of the DMA transfer.
Chapter 6 Theory of Operation Configuration Register 2 Four discrete 74LS74A D-type flip-flops are used to implement Configuration Register 2 (CFG2). Data is written into each bit of this register on the rising edge of the WR* signal generated by the Timing State Machine circuitry. The SC bits are cleared by the onboard RESET* signal generated by the Clock and Reset circuitry, while the LMR and SFL bits are cleared only by the VMEbus signal SYSRESET* or by writing to the register.
Theory of Operation Chapter 6 corresponds to the read access time of the TLC. Local signal SACK is asserted to drive VMEbus signal DTACK* active to indicate that the data is valid on the VMEbus data lines D07 through D00. The data remains valid and the DTACK* signal remains asserted until DS0* is released by the bus master. When DS0* is released, the board first disables the data transceiver and then releases DTACK*. At the same time, the circuitry delays for a recovery time of 250 nsec.
Chapter 6 Theory of Operation DMA Gating and Control The DMA Gating and Control circuitry is designed to control the DMA request/acknowledge interface between the DMAC and the TLC. The circuitry consists of an LS74 flip-flop and miscellaneous logic gates to generate the DMA request signals (DREQ0* and DREQ1*), the carry cycle byte (CCBYTE) strobe, and the DMA Acknowledge Enable signal (DACKEN*).
Theory of Operation Chapter 6 If the carry cycle feature is not used in a DMA transfer, the CC bit in CFG1 is 0, and DMA Gating and Control circuitry directs all DMA requests from the TLC to DMAC Channel 0. DMAC Channel 1 is not used and must not be started. Interrupter The GPIB-1014 requests service by using the Interrupter circuitry.
Chapter 6 Theory of Operation are some external requests for the bus. While the board is holding the bus and the DMAC requests the bus, the DMAC is immediately granted the bus, thus avoiding bus arbitration time. The circuitry consists of various components to drive and receive VMEbus signals BBSY*, BR0* through BR3*, BG0IN* through BG3IN*, and BG0OUT* through BG3OUT*. An S139 2- to 4-bit decoder is used to select one of the four VMEbus Request/Grant lines.
Theory of Operation Chapter 6 received. OWN* is asserted by the DMAC to indicate that it now has ownership of the bus. BUS_REL* is asserted by the DTB Requester and Controller circuitry to indicate that it is going to release the VMEbus. RESET* is asserted to reset all circuitry on the board. Based on the output of the flip-flops, there are numerous combinational outputs.
Chapter 6 Theory of Operation 4. The outputs of the 74S139 are connected to four 74LS02 gates, along with the LBROUT* signal, to assert one of the four VMEbus bus request lines (BR3* through BR0*). 5. The DTB Requester waits for the appropriate Bus Grant In line (BG3IN* through BG0IN*) to become active, at which time BGIN becomes high. 6. The 74S139 outputs are used to direct the others to the corresponding Bus Grant Out line (BG3OUT* through BG0OUT*).
Theory of Operation Chapter 6 This PCL is used to detect interrupts from the GPIB-1014 that are not internal to the DMAC. A negative transition on the PCL sets the PCT bit in the CSR of DMAC Channel 1. If interrupts are enabled in the CCR of Channel 1 (EINT=1), the setting of the PCT bit causes the DMAC to drive its IREQ* line, requesting an interrupt.
Chapter 6 Theory of Operation accepted the byte and the Talker may have already released DAV*. For this reason, the synchronization circuitry looks at the level of the DAV* line rather than for a transition. When the DAV* line is detected high, all devices have accepted the byte and a negative transition is generated on the PCL of Channel 1, requesting an interrupt.
Theory of Operation Chapter 6 4. Clear IMR2. 5. Write a value to CFG1 to release PCL1 line (perhaps use the same value as the last write to CFG1). 6. Write a software abort to Channel 0. 7. Check, then clear the COC and ERR bits in CSR0. 8. Write a software abort to Channel 1 (if a carry cycle is used). 9. Check, then clear the PCT and ERR bits in CSR1.
Chapter 6 Theory of Operation Device (TLC)/DMAC Communication. Communication between the TLC and the DMAC is accomplished mainly by two signals. Each of the four DMA channels has a DMA request input (REQ0* through REQ*3) and a DMA acknowledge output (ACK0* through ACK3*). The TLC requests service by first asserting its DMAREQ line, waits for its DMAACK* pin to assert, and finally waits for its RD* or WR* pins to assert before sending or receiving data.
Theory of Operation Chapter 6 DMA Requests. Internal or external requests activate the DMAC to transfer an operand. The REQG bits of the OCR determine the manner in which requests are generated. Requests can be externally generated by the device or internally generated by the DMAC using its internal automatic request mechanism. Internal automatic requests can be generated at a maximum rate, so that the channel always has a request pending, or at a limited rate, monitoring the bus bandwidth use.
Chapter 6 Theory of Operation Operands and Addressing. Three factors affect how the actual data is handled: device (destination) port size, operand (from source) size, and address sequencing. • Device Port Size The DCR is also used to program the device port size to be 8 or 16 bits. The port size is the number of data bits that the device can handle (transmit or receive) in a single bus cycle. For GPIB DMA data transfers, the device (or TLC) port size is eight bits.
Theory of Operation Chapter 6 address the device (VMEbus memory) in dual-address transfers. It is initiated before starting the channel operation. The BAR is used only in chaining or continue operations. Transfer Count Register Operation. The DMAC has two 16-bit transfer counter registers per channel: the Memory Transfer Counter (MTCR) and the Base Transfer Counter (BTCR). The MTCR is used in all operations to count the number of operands transferred in a block.
Chapter 6 Theory of Operation to service the request for the halted channel. When this bit is reset, the channel resumes operation and services any request that may have been received while the channel was halted. The HLT bit must be cleared to zero when writing to the STR bit to avoid immediate halt of the channel. Software Abort. The CCR has a software abort bit (SAB) that can abort the current operation of the channel. Writing a 1 into the SAB causes a channel abort error to be signaled.
Theory of Operation Chapter 6 If the interrupt bit in the CCR is set when the BTC bit is set, an interrupt is generated. The interrupt handler can reload the BFCR, BAR, and BTCR with information describing the next data block if necessary, clear the BTC bit and set the CNT to repeat the operation. In all cases, if the MTCR is loaded with a terminal count, the count error is signaled. The GPIB-1014 usually does not use continue operations for its GPIB DMA transfers. Array Chaining Operations.
Chapter 6 Theory of Operation DMAC Address and Transfer Count Array BAR Start of array Memory Address A BTC # of entries = 3 Transfer Count A Data Blocks Data Block A Memory Address B Transfer Count B Memory Address C Data Block B Transfer Count C Data Block C Figure 6-2. Array Format for Array Chaining Modes Linked Chaining Operations. This type of chaining is very similar to array chaining.
Theory of Operation Chapter 6 DMAC Address and Transfer Count Array BAR Start of array Memory Address A BTC xxxx (not used) Transfer Count A Data Blocks Data Block A Link to next entry Data Block B Memory Address B Transfer Count B Link to next entry Data Block C Memory Address B Transfer Count B 0000 (end link) Figure 6-3. Array Format for Linked Chaining Modes Error Conditions. When an error is signaled on a channel, all activity on that channel is stopped.
Chapter 6 Theory of Operation Sources of errors are as follows: • Configuration Error This occurs when any undefined or reserved bit pattern, or illegal device/operand size combination is programmed into a channel and an attempt is made to set the STR bit.
Theory of Operation Chapter 6 transfer, the Memory Address and Device Address Registers point to the location of the next operand and the Memory Transfer Counter contains the number of operands yet to be transferred. If an error occurs during a transfer, that transfer has not completed and the registers contain the values they had before the transfer was attempted. The DMAC logs the first error encountered in the Channel Error Register.
Chapter 6 Theory of Operation request is enabled for the condition. An important fact to remember is that ISR1 and ISR2 are always cleared when read, even if the condition that caused the bit to be initially set remains true. Data to and from the GPIB is pipelined through the CDOR and DIR respectively. An 8-MHz clock is used as the CLOCK input to the TLC. For proper GPIB timing, the internal counter must be programmed to eight. The TLC RESET pin is driven by the GPIB-1014 RESET signal.
Theory of Operation Chapter 6 limited assurance that the TLC and its associated circuitry are working and that the output signals can be manipulated properly. NDAC* is the GPIB Not Data Accepted signal. By programming the TLC to Listen or not Listen via the AUXMR, NDAC* can be asserted or not asserted, respectively. DIO1* is the GPIB Data Input/Output bit 1 (LSB).
Chapter 7 Diagnostic and Troubleshooting Test Procedures This chapter contains test procedures for determining if the GPIB-1014 is installed and operating correctly. The tests are similar to those used by National Instruments to verify correct hardware functioning. The method used is to program specific internal functions by writing to one or more registers, then reading other registers to confirm that the functions were implemented.
Diagnostic and Troubleshooting Test Procedures Chapter 7 2. Examine any read and write routines being used in connection with the checkout procedure for errors. 3. Recheck the jumper settings described in Chapter 3. After these items have been carefully checked, if the interface is still not functioning properly, gather together the information concerning what the GPIB-1014 is and is not doing with regard to the expected results and contact National Instruments. GPIB-1014 Hardware Installation Tests 1.
Chapter 7 105 065 065 067 067 105 105 065 067 Diagnostic and Troubleshooting Test Procedures CFG2 = 08 NIV1 = 55 NIV1 = 55? EIV1 = 55 EIV1 = 55? CFG2 = 0A CFG2 = 08 NIV1 = 0F? EIV1 = 0F? Clear LMR Set LMR and turn LED green Clear LMR 5. Test ton, DO, ERR, CPTR, TA.
Diagnostic and Troubleshooting Test Procedures 11B 11B 119 115 11B 119 AUXMR = 1E AUXMR = 16 ADSR = 80? ISR2 = 9? AUXMR = 10 ADSR = C0? Chapter 7 set IFC clear IFC CIC CO + ADSC go to standby CIC + ATN* 8. Test DMA Error. 105 105 007 007 000 000 000 CFG2 = 0A CFG2 = 08 CCR0 = 80 CCR0 = 10 CSR0 = 91? CSR0 = 90 CSR0 = 01? Set LMR and turn LED green Clear LMR start channel 0 abort channel 0 COC & Error clear bits bits cleared 9. Test DMAC Interrupt Detection.
Chapter 7 087 080 Diagnostic and Troubleshooting Test Procedures daddr=FF daddr+1=FE ...... daddr+9=F6 CCR2=80 CSR2=81? daddr+0A=FF? daddr+0B=FE? ...... daddr+13(hex)=F6? Set data values at source locations Start DMA on Channel 2 DMA completed without error? Bit 4 = 1 if error Verify data values at destination locations 11. Test DMA transfer (flyby) to GPIB, one byte, memory read.
Diagnostic and Troubleshooting Test Procedures 00A 004 005 006 000 040 045 029 00C 101 11B 119 007 115 11B 113 MTC0 = 0001 DCR0 = A0 OCR0 = 82 SCR0 = 0 CSR0 = FF CSR1 = FF OCR1 = 0 MFC0 = 06 MAR0 = daddr daddr= 0 CFG1 = 19 AUXMR = 2 ADMR = C0 CCR0 = 80 IMR2 = 10 AUXMR = 0 ISR1 = 02? 111 DIR = 55 000 040 113 CSR0 = 81? CSR1 = 02? ISR1 = 02? daddr= 55? 101 CFG1 = 18 040 040 CSR1 = 02 CSR1 = 01? Chapter 7 one byte 4-byte data address clear data location BRG3*, IN, enable ROR feature TLC Reset ton,
Chapter 7 Diagnostic and Troubleshooting Test Procedures 005 045 006 046 029 00C OCR0 = 02 OCR1 = 0A SCR0 = 04 SCR1 = 04 MFC0 = 06 MAR0 = 00003000 00A 069 079 05C 05A MTC0 = 0002 MFC1 = 06 BFC1 = 06 BAR1 = 00003004 BTC1 = 0002 000 040 11B 119 115 047 007 11B CSR0 = FF CSR1 = FF AUXMR = 2 ADMR = C0 IMR2 = 20 CCR1 = 80 CCR0 = 80 AUXMR = 0 113 ISR1 = 1? 111 CDOR = 1? 113 ISR1 = 1? 111 DIR = 2? 000 04A 113 CSR0 = 81? MTC1 = 0001? ISR1 = 13? 111 040 047 040 DIR = 3? CSR1 = 0A? CCR1 = 10 CSR1 =
Diagnostic and Troubleshooting Test Procedures 3000 data = 0000 3002 data = 0081 3004 3006 3008 300A 300C 300E 105 105 101 004 044 005 045 006 046 029 00C 00A 069 079 05C 05A data = 0000 data = 3003 data = 0001 data = 0000 data = 3002 data = 0002 CFG2 = 0A CFG2 = 08 CFG1 = 1D DCR0 = A0 DCR1 = A0 OCR0 = 82 OCR1 = 8A SCR0 = 04 SCR1 = 04 MFC0 = 06 MAR0 = 00003000 MTC0 = 0002 MFC1 = 06 BFC1 = 06 BAR1 = 00003004 BTC1 = 0002 000 040 11B 119 115 047 007 11B 113 111 CSR0 = FF CSR1 = FF AUXMR = 2 ADMR = C0 I
Chapter 7 Diagnostic and Troubleshooting Test Procedures 113 ISR1 = 2? 111 DIR = 3 04A MTC1 = 0001? 040 047 040 3000 CSR1 = 0A? CCR1 = 10 CSR1 = FF data = 01? 3001 3002 data = 02? data = 03? © National Instruments Corporation after transferred the first two bytes on Channel 0 and the carry cycle byte on Channel 1, check if DI is cleared before write the last data byte to DIR write the last data byte to TLC, since DIR is full, TLC will request for a DMA transfer to put the byte in DIR to memory
Appendix A Hardware Specifications This appendix specifies the electrical, environmental, and physical characteristics of the GPIB-1014 board and the conditions under which it should be operated. Table A-1. Electrical Characteristics Characteristic Specification Transfer Rates DMA Over 500 kbytes/sec* Programmed I/O Over 80 kbytes/sec* Power Requirement +5 VDC 1.6 A typical 2.0 A maximum *Actual speed may vary considerably from those shown due to instrumentation capabilities. Table A-2.
Hardware Specifications Appendix A Table A-3. Physical Characteristics Characteristic Dimensions Specification 6.3 in. by 9.2 in.
Appendix B Parts List and Schematic Diagrams This appendix contains the parts list and schematic diagrams for the GPIB-1014. Art not available in PDF version of document.
Appendix C Sample Programs This appendix contains listings of routines in 68000 assembly language code that implement the essential elements of these major utility functions: • Initialize the GPIB-1014 interface (INIT). • Initialize the interface functions of the GPIB devices (IFC). • Set or clear the GPIB REN line (REN). • Accept data bytes from a Talker (RCV). • Address Talker and read device-dependent messages (READ). • Send data bytes to Listeners (DSEND).
Sample Programs Appendix C ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; BASE DIR CDOR ISR1 IMR1 ISR2 IMR2 SPSR SPMR ADSR ADMR CPTR AUXMR ADR0 ADR ADR1 EOSR MTC0 MAR0 MFC0 CSR0 DCR0 OCR0 SCR0 CCR0 MTC1 MAR1 MFC1 BTC1 BAR1 BFC1 CSR1 DCR1 OCR1 SCR1 CCR1 CFG1 CFG2 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 0xFF2000 BASE + 0x111 BASE + 0x111 BASE + 0x113 BASE + 0x113 BASE + 0x115 BASE + 0x115 BASE + 0x117 BASE + 0x117 BASE + 0x119 BASE + 0x119 BASE
Appendix C Sample Programs DI DO ERR ENDRX = = = = 001 (octal) 002 004 020 | ISR1 Bits | Data in | Data out | Error | END received CO = 010 | ISR2 Bits | Command out NATN = 0100 | ADSR Bits | Not ATN MODE1 = TRM = 001 060 | ADMR Bits | Address Mode 1 | GPIB-1014 functions for T/R2 and T/R3 DT1 DL1 = = 0100 0-40 | ADR Bits | Disable Talker | Disable Listener ICR PPR AUXRA AUXRB AUXRE = = = = = 040 0140 0200 0240 0300 | AUXMR Hidden Registers | Internal Counter Register | Parallel Poll
Sample Programs Appendix C CLRS COC CERR ACT PCT = = = = = 0377 0200 020 010 002 | CSR Bits | Clear all status bits | Channel operation complete | Error in channel operation | Channel active | PCL transition occurred ECC IN OUT = = = 004 001 000 | CFG1 Bits | Enable Carry Cycle feature | Accepting data from GPIB | Sending data to GPIB SLMR CLMR = = 012 010 | CFG2 Bits | Set Local Master Reset bit | Clear Local Master Reset bit TCT UNL UNT = = = 011 077 0137 GPIB Commands | Take control | Un
Appendix C Sample Programs | | **************** | * INITIALIZE - INIT * | **************** | | Summary: | - Initialize the GPIB-1014 hardware | | Assumptions on entry: | - User-specified constants MA, ADMC, and SC have | been initialized | - Mode 1 primary addressing is used | - Low-speed timing is used | - Interrupts are not used | - Status byte will be set elsewhere | - Remote Parallel Poll configuration will be used | | Actions: | - Pulse LMR to put hardware in known reset state | - Disable interrupts
Sample Programs Appendix C | | Comments | -------------------------------------------------------------------------------------------------------------------------------------------INIT: movb #SLMR,CFG2 | Pulse Local Master Reset movb #CLMR,CFG2 | | movb #CRST,AUXMR | Chip Reset | movb #0,IMR1 | Disable TLC interrupts movb #0,IMR2 | | tstb ISR1 | Clear status bits by reading registers tstb ISR2 | | movb #MODE1+TRM,ADMR | Set address mode, Talker/Listener inactive, and proper | T/R signal mode | movb #MA+S
Appendix C Sample Programs | | ********************** | * INTERFACE CLEAR - IFC * | ********************** | | Summary: | - Initialize the interface function of other GPIB | devices | | Assumptions on entry: | - GPIB-1014 has been initialized | - GPIB-1014 is System Controller (SC is true) | | Actions: | - Assert GPIB IFC | - Wait at least 100 microseconds | - Unassert IFC | | Status on return: | - GPIB-1014 is Active Controller | - Interface functions of other GPIB devices are reset | to their idle state
Sample Programs Appendix C | | ******************** | * REMOTE ENABLE - REN * | ******************** | | Summary: | - Set or clear GPIB Remote Enable signal | | Assumptions on entry: | - User specified sre is non-zero if REN is to be | asserted and is zero if REN is to be unasserted | - GPIB-1014 is System Controller and Active | Controller | | Actions: | - Check sre flag.
Appendix C Sample Programs | | ************** * | * RECEIVE - RCV * | ************** * | | Summary: | - Called by READ to receive data if GPIB-1014 is | Controller-In-Charge | - Called directly from main program to receive data if | GPIB-1014 is Idle Controller | | Assumptions on entry: | - GPIB-1014 is Standby or Idle Controller | - GPIB-1014 is or will be addressed to listen | - The GPIB Talker has been or will be addressed | - The Talker will send END with last byte if the number | of bytes sent is les
Sample Programs Appendix C | 68000 Code | Comments -------------------------------------------------------------------------------------------------------------------------------------------| RCV: movb #TMODE,DCR0 | Set DMA transfer mode movb #TMODE,DCR1 | | movb #GTM,OCR0 | Set control registers movb #MCU,SCR0 | | movb #FF,CSR0 | Clear status registers movb #FF,CSR1 | | movl a0,MAR0 | Point channel 0 to buffer | cmpb #0,cic | Is GPIB-1014 Controller-In-Charge beq RCV1 | | | Yes, set up carry cycle featur
Appendix C Sample Programs RCV4: btst bne movw subw btst beq subw bra #COC,CSR0 RCV5 MTC0,d1 d1,d0 #ECC,CFG1 RCV6 #1,d0 RCV6 RCV5: btst bne movw subw addw #ECC, CFG1 RCV6 MTC1,d1 d1,d0 #1,d0 RCV6: movb movb movb #0,IMR2 #STOP,CCR1 #STOP,CCR0 rts © National Instruments Corporation | | Calculate number of bytes transferred | | | | If carry cycle, MTC0 was initialized to (d0)-1 | | | | | If no carry cyle, leave d0 as is | | | | | | Disable DMAs and stop DMA channels | | | | | C-11 GPIB-1014 User Ma
Sample Programs Appendix C | | ****** * | * READ * | ****** * | Summary: | - Called to read device-dependent (data) messages | when the GPIB-1014 is Controller-In-Charge (RCV | is called when the GPIB-1014 is Idle Controller) | | Assumptions on entry: | - GPIB-1014 is Controller-In-Charge | - The Talker address is placed in first location of | cmdbuf | - The variable cmdct is set to 1 | - The buffer datbuf is free to place incoming data | - The number of bytes to read is placed in datct | | Actions: | - S
Appendix C Sample Programs | 68000 Code | Comments -------------------------------------------------------------------------------------------------------------------------------------------| READ: movb cmdbuf,cmdbuf+2 | Put Untalk and Unlisten commands before movb #UNT,cmdbuf | Talker address in the buffer movb #UNL,cmdbuf+1 | addw #2,cmdct | | bsr CMD | Command routine will address the Talker | movb #LTN,AUXMR | Program GPIB-1014 to be a Listener movb #GTS,AUXMR | so it can take control synchronously |
Sample Programs Appendix C | | ****************** | * DATA SEND - DSEND * | ****************** | | Summary: | - Called directly from the main program if the | GPIB-1014 is not CIC | | Assumptions on entry: | - The GPIB-1014 is Standby or Idle Controller | - GPIB-1014 is or will be addressed to talk | - If the GPIB-1014 is Idle Controller, the current CIC | will go to standby | - The d0 register contains the byte count | - The a0 register contains the address of the data | buffer | - The user specified var
Appendix C Sample Programs | 68000 Code | Comments -------------------------------------------------------------------------------------------------------------------------------------------| DSEND: movb #TMODE,DCR0 | Set DMA transfer mode movb #TMODE,DCR1 | | movb #MTG,OCR0 | Set control registers movb #MCU,SCR0 | | movb #FF,CSR0 | Clear status registers movb #FF,CSR1 | | movl a0,MAR0 | Point channel 0 to buffer tstb vseoi | Send END with last byte? beq DSEND1 | | | Yes, enable carry cycle feature | movb
Sample Programs Appendix C DSEND4: btst bne movw subw btst beq subw bra #COC,CSR0 DSEND5 MTC0,d1 d1,d0 #ECC,CFG1 DSEND6 #1,d0 DSEND6 DSEND5: btst bne movw subw addw #ECC,CFG1 DSEND6 MTC1,d1 d1,d0 #1,d0 DSEND6: movb #0,IMR2 movb movb #STOP,CCR1 #STOP,CCR0 rts GPIB-1014 User Manual | Calculate number of bytes transferred | | | | | | | | | | | | | | | Disable DMAs | | Stop DMA channels | | | | C-16 © National Instruments Corporation
Appendix C Sample Programs | | ********* | * WRITE * | ********* | | Summary: | - Called to send device-dependent (data) messages | when the GPIB-1014 is Controller-In-Charge | (DSEND is called when the interface is Idle | Controller) | | Assumptions on entry: | - GPIB-1014 is CIC | - One Listener is addressed and its address is placed | in the variable ola | - The data to be sent is placed in datbuf | - The variable datct contains the number of bytes to | send | | Actions: | - Set up cmdbuf and cmdct and
Sample Programs Appendix C | 68000 Code | Comments -------------------------------------------------------------------------------------------------------------------------------------------| WRITE: movw #4,cmdct | Put Untalk, Unlisten, MTA, and OLA movb #UNT,cmdbuf | commands in the buffer movb #UNL,cmdbuf+1 | movb #MA+100,cmdbuf+2 | movb #ola,cmdbuf+3 | | bsr CMD | Call CMD to address GPIB devices | movb #GTS,AUXMR | Go to standby and drop ATN | movw #datct,d0 | Preset d0 register with byte count movl #
Appendix C Sample Programs | | ********************** | * COMMAND SEND - CSEND * | ********************** | | Summary: | - Called by CMD to send interface messages | | Assumptions on entry: | - The GPIB-1014 is Active Controller | - The d0 register contains the number of bytes to | send | - The a0 register contains the address oc cmdbuf | | Actions: | - Initialize a count variable | - Wait until the CDOR is empty | - Write a byte and increment the counter | - Check for a GPIB error | - Loop until all byte
Sample Programs Appendix C | | *************** | * COMMAND - CMD * | *************** | | Summary: | - Send GPIB interface or command messages | | Assumptions on entry: | - The GPIB-1014 is Controller-In-Charge | - The commands to be sent are in cmdbuf | - The variable cmdct contains the number of | commands to be sent, which must be less than 256 | - Interruption of any data transfer in progress is | acceptable | | Actions: | - Issue TCA command to assert ATN in case the | GPIB-1014 is at standby | - Load
Appendix C Sample Programs | | ********************** | * PASS CONTROL - PASSC * | ********************** | | Summary: | - Passes GPIB Controller-In-Charge status to another | device | | Assumptions on entry: | - The GPIB-1014 is Controller-In-Charge | - The primary GPIB address of the new controller is placed | in tctadr | | Actions: | - Send TCA command to take control in case the GPIB-1014 | is at standby | - Set up the command buffer and command count | - Call CMD to send the command bytes | | Status
Appendix D Multiline Interface Messages This appendix lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions. These functions include initializing the bus, addressing and unaddressing devices, and setting device modes for local or remote programming. The multiline interface messages are IEEE 488-defined commands that are sent and received with ATN TRUE.
Multiline Interface Messages Appendix D Multiline Interface Messages Hex Oct Dec ASCII 00 01 02 03 04 05 06 07 000 001 002 003 004 005 006 007 0 1 2 3 4 5 6 7 08 09 0A 0B 0C 0D 0E 0F 010 011 012 013 014 015 016 017 8 9 10 11 12 13 14 15 BS HT LF VT FF CR SO SI 10 11 12 13 14 15 16 17 020 021 022 023 024 025 026 027 16 17 18 19 20 21 22 23 DLE DC1 DC2 DC3 DC4 NAK SYN ETB 18 19 1A 1B 1C 1D 1E 1F 030 031 032 033 034 035 036 037 24 25 26 27 28 29 30 31 CAN EM SUB ESC FS GS RS US NUL SOH STX
Appendix D Multiline Interface Messages Multiline Interface Messages Hex Oct 40 41 42 43 44 45 46 47 100 101 102 103 104 105 106 107 64 65 66 67 68 69 70 71 48 49 4A 4B 4C 4D 4E 4F 110 111 112 113 114 115 116 117 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F PPE PPU SDC SPD Dec ASCII Msg Hex Oct @ A B C D E F G MTA0 MTA1 MTA2 MTA3 MTA4 MTA5 MTA6 MTA7 60 61 62 63 64 65 66 67 140 141 142 143 144 145 146 147 96 97 98 99 100 101 102 103 ` a b c d e f g MSA0,PPE MSA1,PPE MSA2,PPE MSA3,PPE
Appendix E Operation of the GPIB This chapter describes the operation of the GPIB. Communication among interconnected GPIB devices is achieved by passing messages through the interface system. Types of Messages The GPIB carries device-dependent messages and interface messages. • Device-dependent messages, often called data or data messages, contain device-specific information such as programming instructions, measurement results, machine status, and data files.
Operation of the GPIB Appendix E Some bus configurations do not require a Controller. For example, one device may always be a Talker (called a Talk-only device) and there may be one or more Listen-only devices. A Controller is necessary when the active or addressed Talker or Listener must be changed. The Controller function is usually handled by a computer. With the GPIB interface board and its software your personal computer plays all three roles.
Appendix E Operation of the GPIB NRFD (not ready for data) NRFD indicates when a device is ready or not ready to receive a message byte. The line is driven by all devices when receiving commands and by Listeners when receiving data messages. NDAC (not data accepted) NDAC indicates when a device has or has not accepted a message byte. The line is driven by all devices when receiving commands and by Listeners when receiving data messages.
Operation of the GPIB Appendix E Physical and Electrical Characteristics Devices are usually connected with a cable assembly consisting of a shielded 24 conductor cable with both a plug and receptacle connector at each end. This design allows devices to be linked in either a linear or a star configuration, or a combination of the two. See Figures E-1, E-2, and E-3. The standard connector is the Amphenol or Cinch Series 57 Microribbon or Amp Champ type.
Appendix E Operation of the GPIB Figure E-2.
Operation of the GPIB Appendix E Figure E-3. Star Configuration Configuration Requirements To achieve the high data transfer rate that the GPIB was designed for, the physical distance between devices and the number of devices on the bus are limited. The following restrictions are typical. • A maximum separation of 4 m between any two devices and an average separation of 2 m over the entire bus. • A maximum total cable length of 20 m.
Appendix E Operation of the GPIB Bus extenders are available from National Instruments and other manufacturers for use when these limits must be exceeded. Related Documents For more information on topics covered in this section, consult the following manuals: • ANSI/IEEE Std 488-1978, IEEE Standard Digital Interface for Programmable Instrumentation • ANSI/IEEE Std 488.1-1987, IEEE Standard Digital Interface for Programmable Instrumentation • ANSI/IEEE Std 488.
Appendix F Mnemonics Key This appendix contains a mnemonics key that defines the mnemonics (abbreviations) used throughout this manual for functions, remote messages, local messages, states, bits, registers, integrated circuits, system functions, and VMEbus operations and signals.
Mnemonics Key Mnemonic Appendix F Type Definition VBS ST VBS RM LS ST B B B B B B B R VBO R R R B B R ST ST VBS ST ST B B B VBS ST B R R R R ST Address Lines 1 through 31 Acceptor Data State (AH function) Power Fail Signal Addressed Command Group DMA Acknowledge Signal Acceptor Ready State Channel Active Bit Talker/Listener/Controller (TLC) GPIB Address Bits 5 through 1 Mode 2 Primary TLC GPIB Address Bits 5 through 1 Mode 2 Secondary TLC GPIB Address Bits 5 through 1 Addressed Status Change Bit Enabl
Appendix F BG[0-3]OUT* BIN BLT BR[0-3]* Mnemonics Key VBS B VBO VBS © National Instruments Corporation Bus Grant Out Lines Binary Bit Block Transfer Bus Request Lines F-3 GPIB-1014 User Manual
Mnemonics Key Appendix F C C CACS CADS CAWS CDOR CDO[7-0] CIC CIDS CLK[3-0] CNT CNT[2-0] CO COC CO IE COM[4-0] CPPS CPT CPT ENABLE CPT IE CPTR CPT[7-0] CPWS CS* CSBS CSHS CSNS CSRS CSWS CTRS F ST ST ST R B B ST B B B B B B B ST B B B R B ST LS ST ST ST ST ST ST Controller Controller Active State (C function) Controller Addressed State Controller Active Wait State Control/Data Out Register Control/Data Out Bits 7 through 0 Controller-In-Charge Bit Controller Idle State Clock Bits 3 through 0 Continue Bit
Appendix F DEN* DET DET IE DHDC DHDT DI DI [7-0] DI IE DIO[1-8] DIR DL DL0 DL1 DMA DMAI DMAO DO DO IE DS0* DS1* DT DT DT0 DT1 DTACK* DTAS DTIS Mnemonics Key LS B B B B B B B GS R B B B SF B B B B VBS VBS F B B B VBS ST ST Data Enable Device Execute Trigger Bit Enable Interrupt on Device Execute Trigger Bit DAC Holdoff on DCAS Data Accepted Holdoff on Device Trigger Active State Bit Data In Bit Data In Bits 7 through 0 Enable Interrupt on Data In Bit GPIB Data Lines 1 through 8 Data In Register Disable L
Mnemonics Key Appendix F F FH FIN LM LS Finish Handshake GPIB DMA Transfer Finished RM VBS RM LM Group Execute Trigger Ground Go To Local Go to Standby B B Holdoff on All Bit Holdoff on End Bit LS VBS VBS VBS LS R LS RM RM R R B LS LS B LM VBS R R B LM Interrupt Priority Code Bits Interrupt Acknowledge Signal Interrupt Acknowledge In Interrupt Acknowledge Out Interrupt Priority Code Bits Internal Counter Register Interrupt DTACK Identify Interface Clear Interrupt Mask Register 1 Interrupt Mask Reg
Appendix F Mnemonics Key L L LA LACS LADS LAG LD[0-7] LDTACK LE LIDS LLO LMR LOCS LOK LOKC LOKC IE lon lon LPAS LPAS lpe lpe* LPIS ltn lun LWLS LWORD* F B ST ST RM LS LS F ST RM B ST B B B B LM B ST LM LM ST LM LM ST VBS Listener Listener Active Bit Listener Active State (L function) Listener Addressed State (L function) Listener Address Group Local Data Bus Local DTACK Listener Extended Listener Idle State Local Lockout Local Master Reset Bit Local State Lockout Bit Lockout Change Bit Enable Interrupt
Mnemonics Key Appendix F O OSA OTA RM RM Other Secondary Address Other Talk Address B ST RM LM B LM LM F ST RM RM RM ST RM ST RM ST Parallel Poll Response Bits 3 through 1 Parallel Poll Addressed to Configure State Primary Command Group Pull-up Enable Pending Bit Power Off Power On Parallel Poll (scan all status flags) Parallel Poll Active State Parallel Poll Configure Parallel Poll Disable Parallel Poll Enable Parallel Poll Idle State Parallel Poll Response Parallel Poll Standby Active Parallel Poll
Appendix F rsv rtl RWD RWLS Mnemonics Key LM LM B ST Request Service Return To Local Release When Done Bit Remote With Lockout State B B ST RM RM ST B VBS VBS ST F ST LM ST ST ST ST ST F ST RM RM B ST R B ST R F ST LM ST ST RM B B ST RM ST LS ST Status Bit Polarity (Sense) Bit Serial Poll Status Bits 8 and 6 through 1 System Control Active State Secondary Command Group Selected Device Clear Source Delay State Send EOI Serial Clock Serial Data Source Generate State Source Handshake System Control Inter
Mnemonics Key SYSCLK* SYSFAIL* SYSRESET* Appendix F VBS VBS VBS System Clock System Fail System Reset F B ST ST RM LM LM LM TM SX F ST IC LS LS B LM B ST ST B LM B Talker Talker Active Bit Talker Active State (T function) Talker Addressed State Talk Address Group Take Control Asynchronously Take Control Synchronously Take Control Synchronously on End Take Control Terminate DMA Extended Talk Talker Idle State Talker/Listener/Controller (GPIB Adapter) TLC Chip Reset TLC Write Talker Only Bit Talker Only
Appendix F Mnemonics Key U U UAT UCG UDPCF UNL UNT B VBO RM LM RM RM Unconfigure Bit Unaligned Transfer Universal Command Group Undefined Primary Command Function Unlisten command Untalk command LS Interrupt Vector Bits LS VBS TLC Write Signal Read/Write Line B Transmit End with End Of String Bit V V[0-7] W WR* WRITE* X XEOS © National Instruments Corporation F-11 GPIB-1014 User Manual
Appendix G Customer Communication For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation. Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster. National Instruments provides comprehensive technical assistance around the world. In the U.S.
Technical Support Form ____________________________________________________ Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
GPIB-1014 Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Update this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.
• Type of other boards installed and their respective hardware settings: Board Type Base I/O Address Interrupt Level DMA Channel
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: GPIB-1014 User Manual Edition Date: March 1997 Part Number: 320030-01 Please comment on the completeness, clarity, and organization of the manual. If you find errors in the manual, please record the page numbers and describe the errors. Thank you for your help.
Glossary ___________________________________________________ Prefix nµmkM- Meaning nanomicromillikilomega- ≤ ≥ ° A ANSI C FCC GPIB hex Hz IEEE in.
Index Numbers 0 (Reserved Bit) Channel Error Register, 4-60 Channel Priority Register, 4-61 Channel Status Register, 4-59 Configuration Register 2 (CFG2), 4-66 Device Control Register, 4-52 General Control Register, 4-63 Operation Control Register, 4-53 Sequence Control Register, 4-55 0 (Reserved Bits) Address Mode Register (ADMR), 4-22 Auxiliary Register E (AUXRE), 4-41 Internal Counter Register (ICR), 4-34 68450 DMAC. See DMAC (68450).
Index Memory Address Register (MAR), 4-48 theory of operation, 6-17 Address Status Register (ADSR), 4-20 to 4-21 addressed implementation of Talker and Listener, 5-6 to 5-8 ADM[1-0] (Address Mode Bits 1 through 0), 4-23 to 4-24 ADMR. See Address Mode Register (ADMR). ADR. See Address Register (ADR). ADR0. See Address Register 0 (ADR0). ADR1. See Address Register 1 (ADR1). ADSC (Addressed Status Change Bit), 4-17 to 4-18 ADSC IE (Addressed Status Change Interrupt Enable Bit), 4-17 to 4-18 ADSR.
Index C cabling, 3-10 capability codes for GPIB-1014, 2-13 to 2-15 CC (Carry Cycle Bit), 4-65 CCR. See Channel Control Register (CCR). CDO[7-0] (Command/Data Out Bits 7 through 0), 4-7 CDOR. See Command/Data Out Register (CDOR). CER. See Channel Error Register (CER).
Index commands or command messages, E-1 multiline GPIB commands (table), 4-25 to 4-26, D-2 to D-3 compare address lines location of, 3-3 setting base address, 3-4 compliance levels for GPIB-1014 IEEE 1014 interrupter, 2-15 configuration access mode, 3-3 base address, 3-3 to 3-4 DMA address modifier code output, 3-5 to 3-7 hardware jumpers, 3-1 jumpers and switches (illustration), 3-2 other configuration parameters, 3-7 requirements, E-6 Supervisor or Non-privileged access, 3-3 Configuration Registers Confi
Index VMEbus, 6-3 data or data messages, E-1 DATA SEND-DSEND sample program, C-14 to C-16 data transfer bus (DTB) requester description of, 2-7 VMEbus modules not provided, 2-7 data transfer features. See also DMA data transfers. programmed I/O transfers, 2-8 throughput, 2-7 to 2-8 DAV (data valid) signal, E-3 DCL (Device Clear) command, 4-25 DCR. See Device Control Register (DCR).
Index DMA gating and control circuitry, 6-7 to 6-8 DMA registers 68450 internal DMA registers (chart), 2-5 Address Registers, 4-48 Base Address Register (BAR), 4-48 Base Transfer Counter Register (BTCR), 4-48 Channel Control Register (CCR), 4-56 to 4-57 Channel Error Register (CER), 4-60 Channel Priority Register (CPR), 4-61 Channel Status Register (CSR), 4-58 to 4-59 Configuration Register 1 (CFG1), 4-64 to 4-65 Configuration Register 2 (CFG2), 4-66 to 4-67 Device Address Register (DAR), 4-48 Device Contr
Index continue mode of operation, 6-18 halt, 6-18 initiating the operation, 6-18 interrupt enable, 6-19 software abort, 6-18 overview, 6-15 DMAI (DMA Input Enable Bit), 4-16 DMAO (DMA Out Enable Bit), 4-16 DO (Data Out Bit), 4-12 DO IE (Data Out Interrupt Enable Bit), 4-12 documentation abbreviations used in the manual, vi related documents, vi to vii, E-7 don't care bits, 4-3. See also X (Don't Care Bit).
Index E EINT (Interrupt Enable Bit), 4-57, 4-62, 6-19 electrical characteristics. See physical and electrical characteristics. END IE (End Received Interrupt Enable Bit), 4-10 to 4-11 End of String Register (EOSR), 4-45 END or EOS, sending/receiving, 5-17, 5-20 END RX (End Received Bit), 4-10 to 4-11 EOI (End or Identify Bit), 4-44 EOI (End or Identify) line, E-3 EOS[7-0] (End of String Bits 7 through 0), 4-45 EOSR. See End of String Register (EOSR).
Index parts list and schematic diagrams, B-1 to B-9 theory of operation 68450 DMAC, 6-14 to 6-23 address decoding, 6-3 to 6-4 clock and reset circuitry, 6-4 to 6-5 Configuration registers, 6-5 to 6-6 DMA gating and control, 6-7 to 6-8 DTB requester and controller, 6-9 to 6-12 GPIB interface, 6-23 to 6-24 GPIB synchronization and interrupt control, 6-12 to 6-14 interrupter, 6-9 test and troubleshooting, 6-24 timing state machine, 6-6 to 6-7 VMEbus interface, 6-1 to 6-3 with VMEbus computer (illustration), 2
Index GPIB-1014 compatibility, 1-1 GPIB-1014 compliance levels, 2-15 IFC (interface clear) line, E-3 Immediate Execute Pon command codes for, 4-28 description, 4-29 IMR1. See Interrupt Mask Register 1 (IMR1).
Index register map, 4-1 Serial Poll Mode Register (SPMR), 4-19 Serial Poll Status Register (SPSR), 4-19 writing to hidden registers, 4-4 Internal Counter Register (ICR), 4-34 interrupt control. See GPIB Synchronization and Interrupt Control. Interrupt Mask Register 1 (IMR1), 4-8 to 4-13 Interrupt Mask Register 2 (IMR2), 4-14 to 4-18 Interrupt Status Register 1 (ISR1), 4-8 to 4-13 Interrupt Status Register 2 (ISR2), 4-14 to 4-18 Interrupt Vector Registers, 4-62 interrupter.
Index LMR (Local Master Reset Bit), 4-67 Local Unlisten command codes for, 4-28 description, 4-32 LOK (Lockout Bit), 4-16 LOKC (Lockout Change Bit), 4-17 LOKC IE (Lockout Change Interrupt Enable Bit), 4-17 lon (Listen Only Bit), 4-22 LPAS (Listener Primary Addressed State Bit), 4-20 M M0 (Program/Data Access Bit), 4-50 M1 (Standard/Short Addressing Bit), 4-50 M2 (Supervisor/User Access Bit), 4-50 MAC (Memory Address Count Bits 3 through 2), 4-55 MAR. See Memory Address Register (MAR).
Index OCR. See Operation Control Register.
Index COMMAND SEND-CSEND, C-19 DATA SEND-DSEND, C-14 to C-16 GPIB-1014 Sample Functions for Driver, C-2 to C-4 INITIALIZE-INIT, C-5 to C-6 INTERFACE CLEAR-IFC, C-7 overview, C-1 PASS CONTROL-PASSC, C-21 READ, C-12 to C-13 RECEIVE-RCV, C-11 REMOTE ENABLE-REN, C-8 WRITE, C-17 to C-18 sending/receiving messages DMA transfers with carry cycle, 5-13 to 5-17 DMA transfers without carry cycle, 5-10 to 5-12 overview, 5-8 polling during DMAs, 5-17 sending and receiving data, 5-19 to 5-20 sending END or EOS, 5-17, 5
Index overview, 5-6 programmed implementation, 5-6 R READ sample program, C-12 to C-13 RECEIVE-RCV sample program, C-11 receiving messages. See sending/receiving messages.
Index Interrupt Status Register 1 (ISR1), 4-8 to 4-13 Interrupt Status Register 2 (ISR2), 4-14 to 4-18 µPD7210 internal GPIB interface registers (chart), 2-3 overview, 4-3 Serial Poll Mode Register (SPMR), 4-19 Serial Poll Status Register (SPSR), 4-19 writing to hidden registers, 4-4 mnemonics for, 4-3 register map, 4-1 to 4-2 size of, 4-2 terminology related to, 4-3 REM (Remote Bit), 4-16 REMC (Remote Change Bit), 4-17 REMC IE (Remote Change Interrupt Enable Bit), 4-17 REMOTE ENABLE-REN sample program, C-
Index SCR. See Sequence Control Register.
Index REN (remote enable), E-3 SRQ (service request), E-3 VMEbus signals chart of, 2-1 to 2-2 control signals, 6-2 operation, 6-1 to 6-3 SIZE (Size Bits 5 through 4), 4-53 slave-addressing, VMEbus, 2-2 to 2-3 slave cycles, Timing State Machine, 6-6 to 6-7 slave-data, VMEbus, 2-5 slave read and write transfers, 6-1 SPD (Serial Poll Disable) command, 4-26 SPE (Serial Poll Enable) command, 4-26 specifications electrical characteristics, 2-1 to 2-2 IEEE 488 bus transfer rate, A-1 operating environment, A-1 phy
Index codes for, 4-28 description, 4-31 Talker/Listener/Controller (TLC). See also Controller function; DMAC channel operation.
Index definition of, 2-12 theory of operation DMA cycles, 6-7 overview, 6-6 slave cycles, 6-6 to 6-7 TLC. See Talker/Listener/Controller (TLC).
Index troubleshooting test procedures DMA stand alone testing, 6-24 GPIB interface testing, 6-24 hardware installation tests, 7-2 to 7-8 interpreting test procedures, 7-1 overview, 7-1 verification of GPIB-1014 before installation, 3-10 U U (Parallel Poll Unconfigure Bit), 4-35 UNL (Unlisten) command, 4-26 unpacking the GPIB-1014, 1-4 UNT (Untalk) command, 4-26 V Valid Secondary Command or Address command codes for, 4-28 description, 4-30 verification of system compatibility, 3-7 to 3-9 testing, 3-10 VME
Index X X (Don't Care Bit), 4-42, 4-50 XEOS (Transmit END with EOS Bit), 4-37 XRM (External Request Mode Bits 7 through 6), 4-51 GPIB-1014 User Manual Index-23 © National Instruments Corporation
