Data Sheet

MCP3426/7/8
DS22226A-page 26 © 2009 Microchip Technology Inc.
TABLE 5-5: I
2
C SERIAL TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all limits are specified for T
A
= -40 to +85°C, V
DD
= +2.7V to +5.0V,
V
SS
= 0V, CHn+ = CHn- = V
REF
/2.
Parameters Sym Min Typ Max Units Conditions
Standard Mode (100 kHz)
Clock frequency f
SCL
0 — 100 kHz
Clock high time
T
HIGH
4000 — — ns
Clock low time
T
LOW
4700 — — ns
SDA and SCL rise time
T
R
— — 1000 ns From V
IL
to V
IH
(Note 1)
SDA and SCL fall time
T
F
— — 300 ns From V
IH
to V
IL
(Note 1)
START condition hold time
T
HD:STA
4000 — — ns After this period, the first clock
pulse is generated.
Repeated START condition
setup time
T
SU:STA
4700 — — ns Only relevant for repeated Start
condition
Data hold time
T
HD:DAT
0 — 3450 ns (Note 3)
Data input setup time
T
SU:DAT
250 — — ns
STOP condition setup time
T
SU:STO
4000 — — ns
Output valid from clock
T
AA
0 — 3750 ns (Note 2, Note 3)
Bus free time
T
BUF
4700 — — ns Time between START and STOP
conditions.
Fast Mode (400 kHz)
Clock frequency
T
SCL
0 — 400 kHz
Clock high time
T
HIGH
600 — — ns
Clock low time
T
LOW
1300 — — ns
SDA and SCL rise time
T
R
20 + 0.1C
b
— 300 ns From V
IL
to V
IH
(Note 1)
SDA and SCL fall time
T
F
20 + 0.1C
b
— 300 ns From V
IH
to V
IL
(Note 1)
START condition hold time
T
HD:STA
600 — — ns After this period, the first clock
pulse is generated
Repeated START condition
setup time
T
SU:STA
600 — — ns Only relevant for repeated Start
condition
Data hold time
T
HD:DAT
0 — 900 ns (Note 4)
Data input setup time
T
SU:DAT
100 — — ns
STOP condition setup time
T
SU:STO
600 — — ns
Output valid from clock
T
AA
0 — 1200 ns (Note 2, Note 3)
Bus free time
T
BUF
1300 — — ns Time between START and STOP
conditions.
Input filter spike suppression
T
SP
0 — 50 ns SDA and SCL pins (Note 5)
Note 1: This parameter is ensured by characterization and not 100% tested.
2: This specification is not a part of the I
2
C specification. This specification is equivalent to the Data Hold Time (T
HD:DAT
)
plus SDA Fall (or rise) time:
T
AA
= T
HD:DAT
+ T
F
(OR T
R
).
3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this
parameter is too long, Clock Low time (T
LOW
) can be affected.
4: For Data Input: This parameter must be longer than t
SP
. If this parameter is too long, the Data Input Setup (T
SU:DAT
) or
Clock Low time (T
LOW
) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing T
AA
parameter.
5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.