User manual

8X96 ADC and DAC User Manual Page 26 of 54
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8X96 DAC – Features
Jitter Immune Operation, Internal Sync, Wordclock Out
In the normal mode DACs are always slaved to incoming digital input. Incoming clock is
run through two PLL circuits for jitter reduction. The incoming data is present on all
outputs with certain limitations regarding the AES/EBU asynchronous mode. (See
“Asynchronous operations as 4 independent stereo DACs” below).
In normal mode wordclock stripped off the clock of incoming signal is present at the
wordclock output.. If AES/EBU input is selected, the wordclock is stripped from the pair
#1/2 only. The chapter “Special DIP Switch Options” describes how to set wordclock
output to be either 44/48 or 88/96, depending on application.. The wordclock output is
intended for special use to be determined by the user. The wordclock output is capable of
driving 75 Ohm terminated destination . This is recommended whenever long (over 10
ft.) cable is used.
There is a special “internal sync mode” which eliminates any relation of sound quality to
incoming jitter. In this mode the converters are clocked from internal crystal oscillator
with accuracy of 10ps of jitter. Wordclock generated by DAC is then driving the signal
source, rather than normal other way around. No matter how jittery the source is the
converters will always sound the same. This mode is recommended for experienced users
and for fixed installations as it requires special attention to overall digital system
clocking. Currently, this feature is implemented for signals originating from AES/EBU
inputs only.