User manual

8X96 ADC and DAC User Manual Page 25 of 54
for current literature, manuals and online email support check http://www.mytekdigital.com
and cleaned up from jitter. The data path is 24 bit. If a bit splitting method is used , a bit-
split signal arriving at the digital input can be decoded and output digitally at the proper
wordlength (see the next chapter).
During normal operation, the digital signal is present at both the AES outputs and the
output of the optional DIO cards.
The AES/EBU interface will pass through (from its inputs to outputs) even 4
asynchronous signals. The format conversion, however, requires pairs to be synchronous
as only the clock of pair #1/2 is used for format conversion. If less than 4 pairs are used,
at least one pair should be feeding channels #1/2.
For example: if you need to record a stereo AES/EBU signal on your eight channel MDM
machine on tracks #7/8 only, feed the signal to input #1/2 and the loop the AES output
#1/2 to the AES input #7/8. Arm only tracks #7/8 and you are ready to go.
The converters need a sampling clock of any frequency between 25-100 kHz. The
circuitry inside is divided into two ranges: 25-50kHz and 50-100kHz. The “Sampling”
switch has to be always set to x1 (Regular) for the lower range and x2 (Hi-speed) for the
higher range.
The conversion is 24 bit. 16, 18 and 20 bit signals are automatically converted with the
full wordlength, resulting in performance superior to 16, 18 or 20 bit DAC’s.
No sample rate conversion or noise shaping is implemented in the DAC.