Specifications

interface, the topology of the network changes, and the routes would need to be updated by the

GM mapper (see “Guide to Software”).

A summary of the specifications of the PCI64B and PCI64C Myrinet/PCI interfaces is listed

below:

PCI-bus Interface: 64/32-bit, 66/33MHz, supports all burst modes and write-invalidate, master

or slave. These interfaces are capable of sustained PCI data rates approaching the limits of the

PCI bus (528 MB/s for 64-bit, 66MHz; 264 MB/s for 64-bit, 33MHz or 32-bit, 66MHz; 132

MB/s for 32-bit, 33MHz). However, the data rate to/from system memory will depend upon

the host’s memory and PCI-bus implementation. The achievable performance can vary

greatly from one host PCI chipset to another. These interfaces function correctly in all PCI

slots that are compliant with PCI specifications version 2.2 or later, with either 3.3V or 5V PCI-

bus signal levels. (3.3V signaling is required of 66MHz PCI slots, but 33MHz PCI slots may use

either 5V or 3.3V signaling.) PCI parity generation and detection is provided. The interface

provides a 64-bit Base Address Register (BAR), but will also function properly when

programmed with a 32-bit address, per the PCI specifications.

DMA controller: DMA stands for Direct Memory Access. In order to support zero-copy APIs

efficiently, the DMA operations can be performed with arbitrary byte counts and byte

alignments. The DMA controller computes the IP checksum for each transfer. The DMA

controller also provides a “doorbell” signaling mechanism that allows the host to write anywhere

within the doorbell region, and have the address and data stored in a FIFO queue in the local

memory. The DMA controller traverses multiple lists in the interface’s local memory to initiate

DMA transfers, thus allowing multiple pending DMA operations.

Interface processor: LANai 9 RISC operating at up to 133MHz for the PCI64B interfaces, or at

up to 200MHz for the PCI64C interfaces. Note: the RISC core in the LANai 9 is similar to but

not binary-compatible with earlier LANai RISCs.

Local memory: 2MB (256Kx8B) in the –2 version; 4MB (512Kx8B) in the –4 version, 8MB

(1Mx8B) in the –8 version. (The –4 and –8 options are not currently available for all port types

and for PMC versus PCI form factors.) The local memory operates from the same clock as the

RISC, i.e., at up to 133MHz for the PCI64B interfaces, or at up to 200MHz for the PCI64C

interfaces. Up to 1,067 MB/s (PCI64B) or 1,600 MB/s (PCI64C) of memory bandwidth is

available to support the Myrinet port, the host DMA, and the RISC processor. Byte parity is

generated and checked.

The standard 2MB of local memory is sufficient for most applications.

Myrinet-2000-Fiber port: 2.0+2.0 Gb/s. An “LC” optical connector attaches to a fiber pair up

to 200m of 50/125 multi-node fiber. This is a Class I Laser Product (no biological hazard).