Specifications

© 2002 Myricom, Inc. 19
Principles of Operation
As illustrated in the following block diagram, all Myrinet/PCI interfaces include a RISC
processor to execute the Myrinet Control Program (MCP), local memory, a packet interface to
and from the Myrinet port, and a versatile DMA controller to support zero-copy APIs. Each of
these parts support high-availability and data-integrity features, such as “heartbeat” link-
continuity monitoring, packet checksums, and memory parity.
The difference between the PCI64B and PCI64C interfaces is the allowed clock rate of the RISC
and local memory: 133MHz for the PCI64B, and 200MHz for the PCI64C. The difference
between the Fiber, Serial, and SAN interfaces is in the conversion circuitry between the SAN
port of the LANai chip and the external port. For the Fiber (M3F) interface pictured and shown
in the block diagram, the conversion circuitry consists of a SerDes-SAN chip, a SerDes
(Serializer-Deserializer) chip, and the Fiber transceiver.
PCI64B card
Serializer-
Deserializer
(SerDes)
PCI connectorFiber connectorLEDs PCI-DMA
LANai Memory
Power regulator
SerDes-SAN