Specifications

The green “link” LED will illuminate when the board is powered, the firmware (such as

the GM-2 or MX-2G Myrinet Control Program) is loaded, and the link is active. The link

will be active if the port is plugged through a cable to a powered switch, to another

initialized NIC or to a loopback plug. The green LED blinks at up to ~5Hz to show when

packet traffic is flowing through the port. The green LEDs on Myrinet-2000 switches

operate similarly.

The yellow “Lanai” LED is controlled by the Lanai processor, and its interpretation is

different for different Myrinet Control Programs. For the GM-2 MCP, the yellow LED

will pulse like a heartbeat while the MCP is running, and will pulse faster when there is

more packet-sending activity (including sending acknowledge packets in reply to packets

received.) If the yellow LED is not pulsing, the GM-2 MCP is not loaded or is not

running.

It is safe electrically to plug or unplug the NIC from the switch while the host is powered

on. However, if you unplug the cable and plug it into another port on the switch or into a

different NIC, the topology of the network changes, and the routes would be

automatically updated by the GM-2 mapper (see “Myrinet Installation and

Troubleshooting Guide”).

A summary of the specifications of the PCIXD, PCIXE, and PCIXF Myrinet/PCI-X NICs

is listed below:

PCI bus: 64-bit, 133/66MHz. These NICs support both PCI-X and PCI protocols, and

can be used in any 3.3V PCI slot. The PCIXD NIC is capable of peak PCI data rates at

the limits of the PCI-X or PCI buses (1067 MB/s for 64-bit, 133MHz PCI-X; 533 MB/s

for 64-bit, 66MHz). However, the data rate to/from system memory will depend

upon the host’s memory and PCI-bus implementation. The achievable performance

can vary greatly from one host PCI chipset to another. These NICs function correctly

in PCI-X slots that are compliant with PCI-X (version 1.0) specifications, and in 3.3V

PCI slots (includes all 66MHz PCI slots) that are compliant with PCI specifications

(version 2.2). The card is keyed for 3.3V operation only. PCI parity generation and

detection is provided.

NIC processor: Lanai XP or Lanai 2XP RISC operating at 225MHz for the PCIXD

NICs, or Lanai 2XP RISC operating at 333MHz for the PCIXE and PCIXF NICs. See

the Lanai-X documentation linked from http://www.myri.com/vlsi/ for a complete

description of the host-DMA, network-DMA, and copy/CRC engines that augment the

RISC.

Local memory: 2MB (256Kx8B) in the -2 version; 4MB (512Kx8B) in the -4 version.

The local memory operates from the same clock as the RISC, i.e., at 225MHz for the

PCIXD NICs, or at 333MHz for the PCIXE and PCIXF NICs, and provides 1,800 MB/s

(PCIXD) or 2,664 MB/s (PCIXE and PCIXF) of memory bandwidth for the RISC

processor, the host-DMA engine, the network-DMA engines, and the copy/CRC engine.

Byte parity is generated and checked.